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Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_131( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_385( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_125( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
| module AsyncResetRegVec_w1_i0_23( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_155( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_110( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_131 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_49( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74]
wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [11:0] _is_aligned_T = {9'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_140( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_150 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_365( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_109 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File SegmentBuffer.scala:
package saturn.mem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
class LoadSegmentBuffer(doubleBuffer: Boolean)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Bundle {
val data = UInt(dLen.W)
val eew = UInt(2.W)
val nf = UInt(3.W)
val eidx = UInt(log2Ceil(maxVLMax).W)
val segstart = UInt(3.W)
val sidx = UInt(3.W)
val sidx_tail = Bool()
val tail = Bool()
val debug_id = UInt(debugIdSz.W)
}))
val out = Decoupled(new Bundle {
val data = UInt(dLen.W)
val debug_id = UInt(debugIdSz.W)
})
val busy = Output(Bool())
})
val nB = if (doubleBuffer) 2 else 1
val rows = 8
val cols = dLenB
val wdata = Wire(Vec(4, UInt((rows*8*8).W)))
val warr = wdata(io.in.bits.eew).asTypeOf(Vec(rows, Vec(8, UInt(8.W))))
val wrow = WireInit(0.U(rows.W))
val wcol = WireInit(0.U(cols.W))
val wmode = Wire(Bool())
val array = Seq.tabulate(rows, cols, nB) { case (_,_,_) => Reg(UInt(8.W)) }
for (r <- 0 until 8) {
for (c <- 0 until cols) {
for (s <- 0 until nB) {
when (wrow(r) && wcol(c) && wmode === s.U) {
array(r)(c)(s) := warr(r)(c % 8)
}
}
}
}
val modes = RegInit(VecInit.fill(nB)(false.B))
val in_sel = RegInit(false.B)
val out_sel = RegInit(false.B)
val out_nf = Reg(Vec(nB, UInt(3.W)))
val out_row = Reg(Vec(nB, UInt(3.W)))
val out_id = Reg(Vec(nB, UInt(debugIdSz.W)))
io.in.ready := !modes(in_sel)
io.out.valid := modes(out_sel)
io.out.bits.data := Mux1H(UIntToOH(out_row(out_sel)), array.map(row => VecInit(row.map(_(out_sel))).asUInt))
io.out.bits.debug_id := out_id(out_sel)
when (io.in.fire) {
wrow := ((1.U << (dLenB.U >> io.in.bits.eew)) - 1.U)(7,0) << io.in.bits.sidx
}
wcol := ((1.U << (1.U << io.in.bits.eew)) - 1.U)(7,0) << (io.in.bits.eidx(log2Ceil(dLenB)-1,0) << io.in.bits.eew)(log2Ceil(dLenB)-1,0)
wmode := in_sel
for (eew <- 0 until 4) {
val in_rows = 8 min (dLenB >> eew)
val in_cols = 8 >> eew
val in_elems = dLenB >> eew
val col = Wire(Vec(in_rows, UInt((8 << eew).W)))
val arr = Wire(Vec(in_rows, Vec(in_cols, UInt((8 << eew).W))))
col := io.in.bits.data.asTypeOf(Vec(in_rows, UInt((8 << eew).W)))
for (r <- 0 until in_rows) {
for (c <- 0 until in_cols) {
arr(r)(c) := col(r)
}
}
wdata(eew) := Fill(8 / in_rows, arr.asUInt)
}
when (io.in.fire && io.in.bits.sidx_tail && (wcol(cols-1) || io.in.bits.tail)) {
in_sel := (if (doubleBuffer) (!in_sel) else false.B)
modes(in_sel) := true.B
out_nf(in_sel) := io.in.bits.nf
out_row(in_sel) := io.in.bits.segstart
out_id(in_sel) := io.in.bits.debug_id
}
when (io.out.fire) {
when (out_row(out_sel) === out_nf(out_sel)) {
out_sel := (if (doubleBuffer) (!out_sel) else false.B)
modes(out_sel) := false.B
} .otherwise {
out_row(out_sel) := out_row(out_sel) + 1.U
}
}
io.busy := modes.orR
}
class StoreSegmentBuffer(doubleBuffer: Boolean)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val in = Flipped(Decoupled(new Bundle {
val data = UInt(dLen.W)
val mask = UInt(dLenB.W)
val debug_id = UInt(debugIdSz.W)
val eew = UInt(2.W)
val nf = UInt(3.W)
val rows = UInt(4.W)
val sidx = UInt(3.W)
val segstart = UInt(3.W)
val segend = UInt(3.W)
}))
val out = Decoupled(new Bundle {
val data = new StoreDataMicroOp
val head = UInt(log2Ceil(dLenB).W)
val tail = UInt(log2Ceil(dLenB).W)
})
val busy = Output(Bool())
})
val nB = if (doubleBuffer) 2 else 1
val rows = 8
val cols = dLenB
val wdata = Wire(Vec(4, UInt((rows*8*8).W)))
val warr = wdata(io.in.bits.eew).asTypeOf(Vec(rows, Vec(8, UInt(8.W))))
val wrow = WireInit(0.U(rows.W))
val wcol = WireInit(0.U(cols.W))
val wmode = Wire(Bool())
val array = Seq.tabulate(rows, cols, nB) { case (_,_,_) => Reg(UInt(8.W)) }
val mask = Seq.fill(nB) { Reg(UInt(dLenB.W)) }
for (r <- 0 until 8) {
for (c <- 0 until cols) {
for (s <- 0 until nB) {
when (wrow(r) && wcol(c) && wmode === s.U) {
array(r)(c)(s) := warr(r)(c % 8)
}
}
}
}
val modes = RegInit(VecInit.fill(nB)(false.B))
val in_sel = RegInit(false.B)
val out_sidx = Reg(Vec(nB, UInt(3.W)))
val out_row = RegInit(0.U(3.W))
val out_sel = RegInit(false.B)
val out_nf = Reg(Vec(nB, UInt(3.W)))
val out_eew = Reg(Vec(nB, UInt(2.W)))
val out_rows = Reg(Vec(nB, UInt(4.W)))
val out_segstart = Reg(Vec(nB, UInt(3.W)))
val out_id = Reg(Vec(nB, UInt(debugIdSz.W)))
def sidxOff(sidx: UInt, eew: UInt) = sidx & ~((1.U << (log2Ceil(cols).U - eew)) - 1.U)
io.in.ready := !modes(in_sel)
io.out.valid := modes(out_sel)
val row_sel = out_row + sidxOff(out_sidx(out_sel), out_eew(out_sel))
io.out.bits.data.tail := DontCare
io.out.bits.data.vat := DontCare
io.out.bits.data.stdata := Mux1H(UIntToOH(row_sel), array.map(row => VecInit(row.map(_(out_sel))).asUInt))
io.out.bits.data.stmask := Fill(dLenB, (Mux1H(UIntToOH(out_sel), mask) >> (out_row << out_eew(out_sel)))(0))
io.out.bits.data.debug_id := out_id(out_sel)
io.out.bits.head := out_sidx(out_sel) << out_eew(out_sel)
val remaining_bytes = (out_nf(out_sel) +& 1.U - out_sidx(out_sel)) << out_eew(out_sel)
io.out.bits.tail := Mux((remaining_bytes +& io.out.bits.head) >= dLenB.U, dLenB.U, remaining_bytes + io.out.bits.head)
when (io.in.fire) {
wrow := ((1.U << (1.U << (log2Ceil(cols).U - io.in.bits.eew))) - 1.U)(7,0) << sidxOff(io.in.bits.sidx, io.in.bits.eew)
for (s <- 0 until nB) {
when (wmode === s.U && io.in.bits.sidx === 0.U) {
mask(s) := io.in.bits.mask
}
}
}
wcol := ((1.U << (1.U << io.in.bits.eew)) - 1.U)(7,0) << (io.in.bits.sidx << io.in.bits.eew)(log2Ceil(cols)-1,0)
wmode := in_sel
for (eew <- 0 until 4) {
val in_rows = 8 min (dLenB >> eew)
val in_cols = 8 >> eew
val in_elems = cols >> eew
val col = Wire(Vec(in_rows, UInt((8 << eew).W)))
val arr = Wire(Vec(in_rows, Vec(in_cols, UInt((8 << eew).W))))
col := io.in.bits.data.asTypeOf(Vec(in_rows, UInt((8 << eew).W)))
for (r <- 0 until in_rows) {
for (c <- 0 until in_cols) {
arr(r)(c) := col(r)
}
}
wdata(eew) := Fill(8 / in_rows, arr.asUInt)
}
when (io.in.fire && io.in.bits.sidx === io.in.bits.nf) {
in_sel := (if (doubleBuffer) (!in_sel) else false.B)
modes(in_sel) := true.B
out_sidx(in_sel) := io.in.bits.segstart
out_nf(in_sel) := io.in.bits.segend
out_eew(in_sel) := io.in.bits.eew
out_rows(in_sel) := io.in.bits.rows
out_segstart(in_sel) := io.in.bits.segstart
out_id(in_sel) := io.in.bits.debug_id
}
when (io.out.fire) {
val sidx_tail = ((out_sidx(out_sel) +& (cols.U >> out_eew(out_sel))) > out_nf(out_sel))
when ((out_row +& 1.U === out_rows(out_sel)) && sidx_tail) {
out_sel := (if (doubleBuffer) (!out_sel) else false.B)
out_row := 0.U
modes(out_sel) := false.B
} .elsewhen (sidx_tail) {
out_sidx(out_sel) := out_segstart(out_sel)
out_row := out_row + 1.U
} .otherwise {
out_sidx(out_sel) := out_sidx(out_sel) + (cols.U >> out_eew(out_sel))
}
}
io.busy := modes.orR
}
| module LoadSegmentBuffer( // @[SegmentBuffer.scala:11:7]
input clock, // @[SegmentBuffer.scala:11:7]
input reset, // @[SegmentBuffer.scala:11:7]
output io_in_ready, // @[SegmentBuffer.scala:12:14]
input io_in_valid, // @[SegmentBuffer.scala:12:14]
input [63:0] io_in_bits_data, // @[SegmentBuffer.scala:12:14]
input [1:0] io_in_bits_eew, // @[SegmentBuffer.scala:12:14]
input [2:0] io_in_bits_nf, // @[SegmentBuffer.scala:12:14]
input [5:0] io_in_bits_eidx, // @[SegmentBuffer.scala:12:14]
input [2:0] io_in_bits_segstart, // @[SegmentBuffer.scala:12:14]
input [2:0] io_in_bits_sidx, // @[SegmentBuffer.scala:12:14]
input io_in_bits_sidx_tail, // @[SegmentBuffer.scala:12:14]
input io_in_bits_tail, // @[SegmentBuffer.scala:12:14]
input [15:0] io_in_bits_debug_id, // @[SegmentBuffer.scala:12:14]
input io_out_ready, // @[SegmentBuffer.scala:12:14]
output io_out_valid, // @[SegmentBuffer.scala:12:14]
output [63:0] io_out_bits_data, // @[SegmentBuffer.scala:12:14]
output [15:0] io_out_bits_debug_id, // @[SegmentBuffer.scala:12:14]
output io_busy // @[SegmentBuffer.scala:12:14]
);
reg [7:0] array_0_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_0_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_1_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_2_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_3_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_4_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_5_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_6_7_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_0_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_1_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_2_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_3_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_4_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_5_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_6_0; // @[SegmentBuffer.scala:41:65]
reg [7:0] array_7_7_0; // @[SegmentBuffer.scala:41:65]
reg modes_0; // @[SegmentBuffer.scala:53:22]
reg [2:0] out_nf_0; // @[SegmentBuffer.scala:56:20]
reg [2:0] out_row_0; // @[SegmentBuffer.scala:57:20]
reg [15:0] out_id_0; // @[SegmentBuffer.scala:58:19]
wire _GEN = ~modes_0 & io_in_valid; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_0 = {2'h0, io_in_bits_eew}; // @[SegmentBuffer.scala:66:31]
wire [15:0] _wrow_T_1 = 16'h1 << (4'h8 >> _GEN_0); // @[SegmentBuffer.scala:66:{19,31}]
wire [14:0] _wrow_T_5 = {7'h0, _wrow_T_1[7:0] - 8'h1} << io_in_bits_sidx; // @[OneHot.scala:58:35]
wire [7:0] wrow = _GEN ? _wrow_T_5[7:0] : 8'h0; // @[Decoupled.scala:51:35]
wire [15:0] _wcol_T_1 = 16'h1 << (4'h1 << _GEN_0); // @[SegmentBuffer.scala:66:31, :68:{17,25}]
wire [5:0] _wcol_T_6 = {3'h0, io_in_bits_eidx[2:0]} << io_in_bits_eew; // @[SegmentBuffer.scala:68:{76,98}]
wire [14:0] _wcol_T_8 = {7'h0, _wcol_T_1[7:0] - 8'h1} << _wcol_T_6[2:0]; // @[OneHot.scala:58:35]
wire [63:0] _wdata_1_T = {4{io_in_bits_data[15:0]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [63:0] _wdata_1_T_1 = {4{io_in_bits_data[31:16]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [63:0] _wdata_1_T_2 = {4{io_in_bits_data[47:32]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [63:0] _wdata_1_T_3 = {4{io_in_bits_data[63:48]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [63:0] _wdata_2_T = {2{io_in_bits_data[31:0]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [63:0] _wdata_2_T_1 = {2{io_in_bits_data[63:32]}}; // @[SegmentBuffer.scala:79:36, :86:41]
wire [3:0][511:0] _GEN_1 = {{{2{{2{{2{io_in_bits_data}}}}}}}, {{_wdata_2_T_1, _wdata_2_T, _wdata_2_T_1, _wdata_2_T, _wdata_2_T_1, _wdata_2_T, _wdata_2_T_1, _wdata_2_T}}, {{_wdata_1_T_3, _wdata_1_T_2, _wdata_1_T_1, _wdata_1_T, _wdata_1_T_3, _wdata_1_T_2, _wdata_1_T_1, _wdata_1_T}}, {{{8{io_in_bits_data[63:56]}}, {8{io_in_bits_data[55:48]}}, {8{io_in_bits_data[47:40]}}, {8{io_in_bits_data[39:32]}}, {8{io_in_bits_data[31:24]}}, {8{io_in_bits_data[23:16]}}, {8{io_in_bits_data[15:8]}}, {8{io_in_bits_data[7:0]}}}}}; // @[SegmentBuffer.scala:37:44, :79:36, :86:{23,41}]
wire _GEN_2 = _GEN & io_in_bits_sidx_tail & (_wcol_T_8[7] | io_in_bits_tail); // @[Decoupled.scala:51:35]
wire _GEN_3 = io_out_ready & modes_0; // @[Decoupled.scala:51:35]
wire _GEN_4 = out_row_0 == out_nf_0; // @[SegmentBuffer.scala:56:20, :57:20, :98:28]
always @(posedge clock) begin // @[SegmentBuffer.scala:11:7]
if (wrow[0] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_0_0 <= _GEN_1[io_in_bits_eew][7:0]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_1_0 <= _GEN_1[io_in_bits_eew][15:8]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_2_0 <= _GEN_1[io_in_bits_eew][23:16]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_3_0 <= _GEN_1[io_in_bits_eew][31:24]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_4_0 <= _GEN_1[io_in_bits_eew][39:32]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_5_0 <= _GEN_1[io_in_bits_eew][47:40]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_6_0 <= _GEN_1[io_in_bits_eew][55:48]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[0] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_0_7_0 <= _GEN_1[io_in_bits_eew][63:56]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_0_0 <= _GEN_1[io_in_bits_eew][71:64]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_1_0 <= _GEN_1[io_in_bits_eew][79:72]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_2_0 <= _GEN_1[io_in_bits_eew][87:80]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_3_0 <= _GEN_1[io_in_bits_eew][95:88]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_4_0 <= _GEN_1[io_in_bits_eew][103:96]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_5_0 <= _GEN_1[io_in_bits_eew][111:104]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_6_0 <= _GEN_1[io_in_bits_eew][119:112]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[1] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_1_7_0 <= _GEN_1[io_in_bits_eew][127:120]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_0_0 <= _GEN_1[io_in_bits_eew][135:128]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_1_0 <= _GEN_1[io_in_bits_eew][143:136]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_2_0 <= _GEN_1[io_in_bits_eew][151:144]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_3_0 <= _GEN_1[io_in_bits_eew][159:152]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_4_0 <= _GEN_1[io_in_bits_eew][167:160]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_5_0 <= _GEN_1[io_in_bits_eew][175:168]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_6_0 <= _GEN_1[io_in_bits_eew][183:176]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[2] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_2_7_0 <= _GEN_1[io_in_bits_eew][191:184]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_0_0 <= _GEN_1[io_in_bits_eew][199:192]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_1_0 <= _GEN_1[io_in_bits_eew][207:200]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_2_0 <= _GEN_1[io_in_bits_eew][215:208]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_3_0 <= _GEN_1[io_in_bits_eew][223:216]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_4_0 <= _GEN_1[io_in_bits_eew][231:224]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_5_0 <= _GEN_1[io_in_bits_eew][239:232]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_6_0 <= _GEN_1[io_in_bits_eew][247:240]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[3] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_3_7_0 <= _GEN_1[io_in_bits_eew][255:248]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_0_0 <= _GEN_1[io_in_bits_eew][263:256]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_1_0 <= _GEN_1[io_in_bits_eew][271:264]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_2_0 <= _GEN_1[io_in_bits_eew][279:272]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_3_0 <= _GEN_1[io_in_bits_eew][287:280]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_4_0 <= _GEN_1[io_in_bits_eew][295:288]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_5_0 <= _GEN_1[io_in_bits_eew][303:296]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_6_0 <= _GEN_1[io_in_bits_eew][311:304]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[4] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_4_7_0 <= _GEN_1[io_in_bits_eew][319:312]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_0_0 <= _GEN_1[io_in_bits_eew][327:320]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_1_0 <= _GEN_1[io_in_bits_eew][335:328]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_2_0 <= _GEN_1[io_in_bits_eew][343:336]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_3_0 <= _GEN_1[io_in_bits_eew][351:344]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_4_0 <= _GEN_1[io_in_bits_eew][359:352]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_5_0 <= _GEN_1[io_in_bits_eew][367:360]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_6_0 <= _GEN_1[io_in_bits_eew][375:368]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[5] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_5_7_0 <= _GEN_1[io_in_bits_eew][383:376]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_0_0 <= _GEN_1[io_in_bits_eew][391:384]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_1_0 <= _GEN_1[io_in_bits_eew][399:392]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_2_0 <= _GEN_1[io_in_bits_eew][407:400]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_3_0 <= _GEN_1[io_in_bits_eew][415:408]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_4_0 <= _GEN_1[io_in_bits_eew][423:416]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_5_0 <= _GEN_1[io_in_bits_eew][431:424]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_6_0 <= _GEN_1[io_in_bits_eew][439:432]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[6] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_6_7_0 <= _GEN_1[io_in_bits_eew][447:440]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[0]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_0_0 <= _GEN_1[io_in_bits_eew][455:448]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[1]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_1_0 <= _GEN_1[io_in_bits_eew][463:456]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[2]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_2_0 <= _GEN_1[io_in_bits_eew][471:464]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[3]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_3_0 <= _GEN_1[io_in_bits_eew][479:472]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[4]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_4_0 <= _GEN_1[io_in_bits_eew][487:480]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[5]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_5_0 <= _GEN_1[io_in_bits_eew][495:488]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[6]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_6_0 <= _GEN_1[io_in_bits_eew][503:496]; // @[SegmentBuffer.scala:37:44, :41:65]
if (wrow[7] & _wcol_T_8[7]) // @[SegmentBuffer.scala:38:22, :46:{19,23,30}, :65:21, :66:10, :68:57]
array_7_7_0 <= _GEN_1[io_in_bits_eew][511:504]; // @[SegmentBuffer.scala:37:44, :41:65]
if (_GEN_2) begin // @[SegmentBuffer.scala:89:{20,44}]
out_nf_0 <= io_in_bits_nf; // @[SegmentBuffer.scala:56:20]
out_id_0 <= io_in_bits_debug_id; // @[SegmentBuffer.scala:58:19]
end
if (~_GEN_3 | _GEN_4) begin // @[Decoupled.scala:51:35]
if (_GEN_2) // @[SegmentBuffer.scala:89:{20,44}]
out_row_0 <= io_in_bits_segstart; // @[SegmentBuffer.scala:57:20]
end
else // @[SegmentBuffer.scala:89:82, :97:22, :98:49]
out_row_0 <= out_row_0 + 3'h1; // @[SegmentBuffer.scala:57:20, :102:44]
if (reset) // @[SegmentBuffer.scala:11:7]
modes_0 <= 1'h0; // @[SegmentBuffer.scala:53:22]
else // @[SegmentBuffer.scala:11:7]
modes_0 <= ~(_GEN_3 & _GEN_4) & (_GEN_2 | modes_0); // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_503( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Breakpoint.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
def svaluePos : Int = 2
val mvalue = UInt(mvalueBits.W)
val mselect = Bool()
val pad2 = UInt((mselectPos - svalueBits - 2).W)
val svalue = UInt(svalueBits.W)
val pad1 = UInt(1.W)
val sselect = Bool()
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(vaddrBits.W)
val textra = new TExtra
def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
}
class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
val debug_if = Output(Bool())
val debug_ld = Output(Bool())
val debug_st = Output(Bool())
val bpwatch = Output(Vec(n, new BPWatch(1)))
})
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
io.debug_if := false.B
io.debug_ld := false.B
io.debug_st := false.B
(io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>
val en = bp.control.enabled(io.status)
val cx = bp.contextMatch(io.mcontext, io.scontext)
val r = en && bp.control.r && bp.addressMatch(io.ea) && cx
val w = en && bp.control.w && bp.addressMatch(io.ea) && cx
val x = en && bp.control.x && bp.addressMatch(io.pc) && cx
val end = !bp.control.chain
val action = bp.control.action
bpw.action := action
bpw.valid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }
(end || r, end || w, end || x)
}
}
| module BreakpointUnit_8( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module MulAddRecFNToRaw_preMul_e8_s24_78( // @[MulAddRecFN.scala:71:7]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:71:7, :74:16]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42]
wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire signProd; // @[MulAddRecFN.scala:97:42]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23]
assign signProd = _signProd_T; // @[MulAddRecFN.scala:97:{30,42}]
assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42]
wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}]
wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32]
wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42]
wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}]
assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56]
wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22]
wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20]
wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20]
wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20]
wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47]
wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42]
wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47]
assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_TLBEntryData_191( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
TLBuffer_a32d64s4k4z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready),
.auto_in_a_valid (auto_buffer_in_a_valid),
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode),
.auto_in_a_bits_param (auto_buffer_in_a_bits_param),
.auto_in_a_bits_size (auto_buffer_in_a_bits_size),
.auto_in_a_bits_source (auto_buffer_in_a_bits_source),
.auto_in_a_bits_address (auto_buffer_in_a_bits_address),
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask),
.auto_in_a_bits_data (auto_buffer_in_a_bits_data),
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt),
.auto_in_d_ready (auto_buffer_in_d_ready),
.auto_in_d_valid (auto_buffer_in_d_valid),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt),
.auto_out_a_ready (auto_tl_out_a_ready),
.auto_out_a_valid (auto_tl_out_a_valid),
.auto_out_a_bits_opcode (auto_tl_out_a_bits_opcode),
.auto_out_a_bits_param (auto_tl_out_a_bits_param),
.auto_out_a_bits_size (auto_tl_out_a_bits_size),
.auto_out_a_bits_source (auto_tl_out_a_bits_source),
.auto_out_a_bits_address (auto_tl_out_a_bits_address),
.auto_out_a_bits_mask (auto_tl_out_a_bits_mask),
.auto_out_a_bits_data (auto_tl_out_a_bits_data),
.auto_out_a_bits_corrupt (auto_tl_out_a_bits_corrupt),
.auto_out_d_ready (auto_tl_out_d_ready),
.auto_out_d_valid (auto_tl_out_d_valid),
.auto_out_d_bits_opcode (auto_tl_out_d_bits_opcode),
.auto_out_d_bits_param (auto_tl_out_d_bits_param),
.auto_out_d_bits_size (auto_tl_out_d_bits_size),
.auto_out_d_bits_source (auto_tl_out_d_bits_source),
.auto_out_d_bits_sink (auto_tl_out_d_bits_sink),
.auto_out_d_bits_denied (auto_tl_out_d_bits_denied),
.auto_out_d_bits_data (auto_tl_out_d_bits_data),
.auto_out_d_bits_corrupt (auto_tl_out_d_bits_corrupt)
); // @[Buffer.scala:75:28]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_80( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_80 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_182( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_192 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_194( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_450 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_8( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File LatencyInjectionQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
import freechips.rocketchip.util.DecoupledHelper
class LatencyInjectionQueue[T <: Data](data: T, depth: Int) extends Module {
val io = IO(new Bundle {
val latency_cycles = Input(UInt(64.W))
val enq = Flipped(Decoupled(data))
val deq = Decoupled(data)
})
val cur_cycle = RegInit(0.U(64.W))
cur_cycle := cur_cycle + 1.U
val queue = Module(new Queue(data, depth))
val release_ready_cycle_q = Module(new Queue(UInt(64.W), depth))
release_ready_cycle_q.io.enq.bits := cur_cycle + io.latency_cycles
queue.io.enq.bits := io.enq.bits
io.deq.bits := queue.io.deq.bits
val enq_fire = DecoupledHelper(
queue.io.enq.ready,
release_ready_cycle_q.io.enq.ready,
io.enq.valid
)
queue.io.enq.valid := enq_fire.fire(queue.io.enq.ready)
release_ready_cycle_q.io.enq.valid := enq_fire.fire(release_ready_cycle_q.io.enq.ready)
io.enq.ready := enq_fire.fire(io.enq.valid)
val deq_fire = DecoupledHelper(
queue.io.deq.valid,
release_ready_cycle_q.io.deq.valid,
release_ready_cycle_q.io.deq.bits <= cur_cycle,
io.deq.ready
)
queue.io.deq.ready := deq_fire.fire(queue.io.deq.valid)
release_ready_cycle_q.io.deq.ready := deq_fire.fire(release_ready_cycle_q.io.deq.valid)
io.deq.valid := deq_fire.fire(io.deq.ready)
}
| module LatencyInjectionQueue_21( // @[LatencyInjectionQueue.scala:9:7]
input clock, // @[LatencyInjectionQueue.scala:9:7]
input reset, // @[LatencyInjectionQueue.scala:9:7]
input [63:0] io_latency_cycles, // @[LatencyInjectionQueue.scala:10:14]
output io_enq_ready, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_valid, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_opcode, // @[LatencyInjectionQueue.scala:10:14]
input [1:0] io_enq_bits_param, // @[LatencyInjectionQueue.scala:10:14]
input [3:0] io_enq_bits_size, // @[LatencyInjectionQueue.scala:10:14]
input [4:0] io_enq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
input [2:0] io_enq_bits_sink, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_denied, // @[LatencyInjectionQueue.scala:10:14]
input [255:0] io_enq_bits_data, // @[LatencyInjectionQueue.scala:10:14]
input io_enq_bits_corrupt, // @[LatencyInjectionQueue.scala:10:14]
input io_deq_ready, // @[LatencyInjectionQueue.scala:10:14]
output io_deq_valid, // @[LatencyInjectionQueue.scala:10:14]
output [4:0] io_deq_bits_source, // @[LatencyInjectionQueue.scala:10:14]
output [255:0] io_deq_bits_data // @[LatencyInjectionQueue.scala:10:14]
);
wire _release_ready_cycle_q_io_enq_ready; // @[LatencyInjectionQueue.scala:19:37]
wire _release_ready_cycle_q_io_deq_valid; // @[LatencyInjectionQueue.scala:19:37]
wire [63:0] _release_ready_cycle_q_io_deq_bits; // @[LatencyInjectionQueue.scala:19:37]
wire _queue_io_enq_ready; // @[LatencyInjectionQueue.scala:18:21]
wire _queue_io_deq_valid; // @[LatencyInjectionQueue.scala:18:21]
wire [63:0] io_latency_cycles_0 = io_latency_cycles; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_valid_0 = io_enq_valid; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_enq_bits_param_0 = io_enq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_enq_bits_source_0 = io_enq_bits_source; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_enq_bits_sink_0 = io_enq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_denied_0 = io_enq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_enq_bits_data_0 = io_enq_bits_data; // @[LatencyInjectionQueue.scala:9:7]
wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_ready_0 = io_deq_ready; // @[LatencyInjectionQueue.scala:9:7]
wire _io_enq_ready_T; // @[Misc.scala:26:53]
wire _io_deq_valid_T_1; // @[Misc.scala:26:53]
wire io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_opcode; // @[LatencyInjectionQueue.scala:9:7]
wire [1:0] io_deq_bits_param; // @[LatencyInjectionQueue.scala:9:7]
wire [3:0] io_deq_bits_size; // @[LatencyInjectionQueue.scala:9:7]
wire [4:0] io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
wire [2:0] io_deq_bits_sink; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_denied; // @[LatencyInjectionQueue.scala:9:7]
wire [255:0] io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_bits_corrupt; // @[LatencyInjectionQueue.scala:9:7]
wire io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
reg [63:0] cur_cycle; // @[LatencyInjectionQueue.scala:16:26]
wire [64:0] _GEN = {1'h0, cur_cycle}; // @[LatencyInjectionQueue.scala:16:26, :17:26]
wire [64:0] _cur_cycle_T = _GEN + 65'h1; // @[LatencyInjectionQueue.scala:17:26]
wire [63:0] _cur_cycle_T_1 = _cur_cycle_T[63:0]; // @[LatencyInjectionQueue.scala:17:26]
wire [64:0] _release_ready_cycle_q_io_enq_bits_T = _GEN + {1'h0, io_latency_cycles_0}; // @[LatencyInjectionQueue.scala:9:7, :17:26, :21:50]
wire [63:0] _release_ready_cycle_q_io_enq_bits_T_1 = _release_ready_cycle_q_io_enq_bits_T[63:0]; // @[LatencyInjectionQueue.scala:21:50]
wire _queue_io_enq_valid_T = _release_ready_cycle_q_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_enq_valid_T = _queue_io_enq_ready & io_enq_valid_0; // @[Misc.scala:26:53]
assign _io_enq_ready_T = _queue_io_enq_ready & _release_ready_cycle_q_io_enq_ready; // @[Misc.scala:26:53]
assign io_enq_ready_0 = _io_enq_ready_T; // @[Misc.scala:26:53]
wire _T = _release_ready_cycle_q_io_deq_bits <= cur_cycle; // @[LatencyInjectionQueue.scala:16:26, :19:37, :38:39]
wire _queue_io_deq_ready_T = _release_ready_cycle_q_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T = _queue_io_deq_valid & _T; // @[Misc.scala:26:53]
wire _release_ready_cycle_q_io_deq_ready_T_1 = _release_ready_cycle_q_io_deq_ready_T & io_deq_ready_0; // @[Misc.scala:26:53]
wire _io_deq_valid_T = _queue_io_deq_valid & _release_ready_cycle_q_io_deq_valid; // @[Misc.scala:26:53]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _T; // @[Misc.scala:26:53]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[Misc.scala:26:53]
always @(posedge clock) begin // @[LatencyInjectionQueue.scala:9:7]
if (reset) // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= 64'h0; // @[LatencyInjectionQueue.scala:16:26]
else // @[LatencyInjectionQueue.scala:9:7]
cur_cycle <= _cur_cycle_T_1; // @[LatencyInjectionQueue.scala:16:26, :17:26]
always @(posedge)
Queue64_TLBundleD_a32d256s5k3z4u_6 queue ( // @[LatencyInjectionQueue.scala:18:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_queue_io_enq_ready),
.io_enq_valid (_queue_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits_opcode (io_enq_bits_opcode_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_param (io_enq_bits_param_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_size (io_enq_bits_size_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_source (io_enq_bits_source_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_sink (io_enq_bits_sink_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_denied (io_enq_bits_denied_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_data (io_enq_bits_data_0), // @[LatencyInjectionQueue.scala:9:7]
.io_enq_bits_corrupt (io_enq_bits_corrupt_0), // @[LatencyInjectionQueue.scala:9:7]
.io_deq_ready (_queue_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_queue_io_deq_valid),
.io_deq_bits_opcode (io_deq_bits_opcode),
.io_deq_bits_param (io_deq_bits_param),
.io_deq_bits_size (io_deq_bits_size),
.io_deq_bits_source (io_deq_bits_source_0),
.io_deq_bits_sink (io_deq_bits_sink),
.io_deq_bits_denied (io_deq_bits_denied),
.io_deq_bits_data (io_deq_bits_data_0),
.io_deq_bits_corrupt (io_deq_bits_corrupt)
); // @[LatencyInjectionQueue.scala:18:21]
Queue64_UInt64_13 release_ready_cycle_q ( // @[LatencyInjectionQueue.scala:19:37]
.clock (clock),
.reset (reset),
.io_enq_ready (_release_ready_cycle_q_io_enq_ready),
.io_enq_valid (_release_ready_cycle_q_io_enq_valid_T), // @[Misc.scala:26:53]
.io_enq_bits (_release_ready_cycle_q_io_enq_bits_T_1), // @[LatencyInjectionQueue.scala:21:50]
.io_deq_ready (_release_ready_cycle_q_io_deq_ready_T_1), // @[Misc.scala:26:53]
.io_deq_valid (_release_ready_cycle_q_io_deq_valid),
.io_deq_bits (_release_ready_cycle_q_io_deq_bits)
); // @[LatencyInjectionQueue.scala:19:37]
assign io_enq_ready = io_enq_ready_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_valid = io_deq_valid_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_source = io_deq_bits_source_0; // @[LatencyInjectionQueue.scala:9:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[LatencyInjectionQueue.scala:9:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_44( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
reg in_flight_10; // @[Monitor.scala:16:26]
reg in_flight_11; // @[Monitor.scala:16:26]
reg in_flight_12; // @[Monitor.scala:16:26]
reg in_flight_13; // @[Monitor.scala:16:26]
reg in_flight_14; // @[Monitor.scala:16:26]
reg in_flight_15; // @[Monitor.scala:16:26]
reg in_flight_16; // @[Monitor.scala:16:26]
reg in_flight_17; // @[Monitor.scala:16:26]
reg in_flight_18; // @[Monitor.scala:16:26]
reg in_flight_19; // @[Monitor.scala:16:26]
reg in_flight_20; // @[Monitor.scala:16:26]
reg in_flight_21; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46]
wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46]
wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46]
wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46]
wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46]
wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hA; // @[Monitor.scala:21:46]
wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hB; // @[Monitor.scala:21:46]
wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'hE; // @[Monitor.scala:21:46]
wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'hF; // @[Monitor.scala:21:46]
wire _GEN_13 = io_in_flit_0_bits_virt_channel_id == 5'h12; // @[Monitor.scala:21:46]
wire _GEN_14 = io_in_flit_0_bits_virt_channel_id == 5'h13; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File LoadSegmenter.scala:
package saturn.mem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
class LoadSegmenter(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val valid = Input(Bool())
val done = Output(Bool())
val op = Input(new VectorMemMacroOp)
val compactor = Decoupled(new CompactorReq(dLenB))
val compactor_data = Input(UInt(dLen.W))
val resp = Decoupled(new Bundle {
val data = UInt(dLen.W)
val debug_id = UInt(debugIdSz.W)
})
})
val segbuf = Module(new LoadSegmentBuffer(vParams.doubleBufferSegments))
val r_eidx = Reg(UInt(log2Ceil(maxVLMax).W))
val r_head = RegInit(true.B)
val r_sidx = Reg(UInt(3.W))
val eidx = Mux(r_head, io.op.vstart, r_eidx)
val sidx = Mux(r_head, io.op.segstart, r_sidx)
val mem_size = io.op.elem_size
val incr = (dLenB.U - (Mux(io.op.seg_nf === 0.U, eidx, sidx) << mem_size)(dLenOffBits-1,0)) >> mem_size
val eidx_incr = Mux(io.op.seg_nf =/= 0.U, 1.U, incr)
val sidx_incr = incr
val next_eidx = eidx +& eidx_incr
val next_sidx = sidx +& sidx_incr
val sidx_tail = next_sidx > io.op.seg_nf
val eidx_tail = next_eidx >= io.op.vl
when (io.op.seg_nf === 0.U) {
io.compactor.valid := io.valid && !segbuf.io.busy && io.resp.ready
io.compactor.bits.head := eidx << mem_size
io.compactor.bits.tail := Mux(eidx_tail, io.op.vl << mem_size, 0.U)
} .otherwise {
io.compactor.valid := io.valid && segbuf.io.in.ready
io.compactor.bits.head := sidx << mem_size
io.compactor.bits.tail := Mux(sidx_tail, (io.op.nf +& 1.U) << mem_size, 0.U)
}
segbuf.io.in.valid := io.valid && io.op.seg_nf =/= 0.U && io.compactor.ready
segbuf.io.in.bits.eew := mem_size
segbuf.io.in.bits.nf := io.op.nf
segbuf.io.in.bits.data := io.compactor_data
segbuf.io.in.bits.eidx := eidx
segbuf.io.in.bits.sidx := sidx
segbuf.io.in.bits.sidx_tail := sidx_tail
segbuf.io.in.bits.tail := eidx_tail
segbuf.io.in.bits.segstart := io.op.segstart
segbuf.io.in.bits.debug_id := io.op.debug_id
segbuf.io.out.ready := io.resp.ready
io.resp.valid := Mux(segbuf.io.busy,
segbuf.io.out.valid,
io.compactor.ready && io.valid && io.op.seg_nf === 0.U)
io.resp.bits.data := Mux(segbuf.io.busy, segbuf.io.out.bits.data, io.compactor_data)
io.resp.bits.debug_id := Mux(segbuf.io.busy, segbuf.io.out.bits.debug_id, io.op.debug_id)
val seg_ready = Mux(io.op.seg_nf === 0.U,
!segbuf.io.busy && io.compactor.ready && io.resp.ready,
segbuf.io.in.ready && io.compactor.ready && sidx_tail)
when (segbuf.io.in.fire) {
r_head := false.B
when (r_head) { r_eidx := io.op.vstart }
r_sidx := next_sidx
when (next_sidx > io.op.nf) {
r_sidx := 0.U
}
}
io.done := false.B
when (seg_ready && io.valid) {
r_head := eidx_tail
r_eidx := next_eidx
io.done := eidx_tail
}
}
File Bundles.scala:
package saturn.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
class VectorMemMacroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val debug_id = UInt(debugIdSz.W)
val base_offset = UInt(pgIdxBits.W)
val page = UInt((paddrBits - pgIdxBits).W)
val stride = UInt(pgIdxBits.W)
val segstart = UInt(3.W)
val segend = UInt(3.W)
val vstart = UInt(log2Ceil(maxVLMax).W)
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val mop = UInt(2.W)
val vm = Bool()
val nf = UInt(3.W)
val idx_size = UInt(2.W)
val elem_size = UInt(2.W)
val whole_reg = Bool()
val store = Bool()
val fast_sg = Bool()
def indexed = !mop.isOneOf(mopUnit, mopStrided)
def seg_nf = Mux(whole_reg, 0.U, nf)
def wr_nf = Mux(whole_reg, nf, 0.U)
}
class VectorIssueInst(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val pc = UInt(vaddrBitsExtended.W)
val bits = UInt(32.W)
val vconfig = new VConfig
val vstart = UInt(log2Ceil(maxVLMax).W)
val segstart = UInt(3.W)
val segend = UInt(3.W)
val rs1_data = UInt(xLen.W)
val rs2_data = UInt(xLen.W)
val page = UInt((paddrBits - pgIdxBits).W)
val vat = UInt(vParams.vatSz.W)
val rm = UInt(3.W)
val emul = UInt(2.W)
val fast_sg = Bool()
val debug_id = UInt(debugIdSz.W)
val mop = UInt(2.W) // stored separately from bits since dispatch may need to set this
def opcode = bits(6,0)
def store = opcode(5)
def mem_idx_size = bits(13,12)
def mem_elem_size = Mux(mop(0), vconfig.vtype.vsew, bits(13,12))
def vm = bits(25)
def orig_mop = bits(27,26)
def umop = bits(24,20)
def nf = bits(31,29)
def wr = orig_mop === mopUnit && umop === lumopWhole
def seg_nf = Mux(wr, 0.U, nf)
def wr_nf = Mux(wr, nf, 0.U)
def vmu = opcode.isOneOf(opcLoad, opcStore)
def rs1 = bits(19,15)
def rs2 = bits(24,20)
def rd = bits(11,7)
def may_write_v0 = rd === 0.U && opcode =/= opcStore
def funct3 = bits(14,12)
def imm5 = bits(19,15)
def imm5_sext = Cat(Fill(59, imm5(4)), imm5)
def funct6 = bits(31,26)
def writes_xrf = !vmu && ((funct3 === OPMVV && opmf6 === OPMFunct6.wrxunary0) || (funct3 === OPFVV && opff6 === OPFFunct6.wrfunary0))
def writes_frf = !vmu && (funct3 === OPFVV)
def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX)
def isOpm = funct3.isOneOf(OPMVV, OPMVX)
def isOpf = funct3.isOneOf(OPFVV, OPFVF)
def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal)
def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal)
def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal)
}
class BackendIssueInst(implicit p: Parameters) extends VectorIssueInst()(p) {
val reduction = Bool() // accumulates into vd[0]
val scalar_to_vd0 = Bool() // mv scalar to vd[0]
val wide_vd = Bool() // vd reads/writes at 2xSEW
val wide_vs2 = Bool() // vs2 reads at 2xSEW
val writes_mask = Bool() // writes dest as a mask
val reads_vs1_mask = Bool() // vs1 read as mask
val reads_vs2_mask = Bool() // vs2 read as mask
val rs1_is_rs2 = Bool()
val nf_log2 = UInt(2.W)
val renv1 = Bool()
val renv2 = Bool()
val renvd = Bool()
val renvm = Bool()
val wvd = Bool()
}
class IssueQueueInst(nSeqs: Int)(implicit p: Parameters) extends BackendIssueInst()(p) {
val seq = UInt(nSeqs.W)
}
class VectorWrite(writeBits: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eg = UInt(log2Ceil(32 * vLen / writeBits).W)
def bankId = if (vrfBankBits == 0) 0.U else eg(vrfBankBits-1,0)
val data = UInt(writeBits.W)
val mask = UInt(writeBits.W)
}
class ScalarWrite extends Bundle {
val data = UInt(64.W)
val fp = Bool()
val size = UInt(2.W)
val rd = UInt(5.W)
}
class VectorReadReq(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eg = UInt(log2Ceil(egsTotal).W)
val oldest = Bool()
}
class VectorReadIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val req = Decoupled(new VectorReadReq)
val resp = Input(UInt(dLen.W))
}
class VectorIndexAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val ready = Output(Bool())
val valid = Input(Bool())
val vrs = Input(UInt(5.W))
val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W))
val eew = Input(UInt(2.W))
val idx = Output(UInt(64.W))
}
class VectorMaskAccessIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val ready = Output(Bool())
val valid = Input(Bool())
val eidx = Input(UInt((1+log2Ceil(maxVLMax)).W))
val mask = Output(Bool())
}
class MaskedByte(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val debug_id = UInt(debugIdSz.W)
val data = UInt(8.W)
val mask = Bool()
}
class ExecuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val eidx = UInt(log2Ceil(maxVLMax).W)
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val rvs1_data = UInt(dLen.W)
val rvs2_data = UInt(dLen.W)
val rvd_data = UInt(dLen.W)
val rvm_data = UInt(dLen.W)
val rvs1_elem = UInt(64.W)
val rvs2_elem = UInt(64.W)
val rvd_elem = UInt(64.W)
val rvs1_eew = UInt(2.W)
val rvs2_eew = UInt(2.W)
val rvd_eew = UInt(2.W)
val vd_eew = UInt(2.W)
val rmask = UInt(dLenB.W)
val wmask = UInt(dLenB.W)
val full_tail_mask = UInt(dLen.W)
val wvd_eg = UInt(log2Ceil(egsTotal).W)
val funct3 = UInt(3.W)
def isOpi = funct3.isOneOf(OPIVV, OPIVI, OPIVX)
def isOpm = funct3.isOneOf(OPMVV, OPMVX)
def isOpf = funct3.isOneOf(OPFVV, OPFVF)
def opmf6 = Mux(isOpm, OPMFunct6(funct6), OPMFunct6.illegal)
def opif6 = Mux(isOpi, OPIFunct6(funct6), OPIFunct6.illegal)
def opff6 = Mux(isOpf, OPFFunct6(funct6), OPFFunct6.illegal)
def vd_eew8 = vd_eew === 0.U
def vd_eew16 = vd_eew === 1.U
def vd_eew32 = vd_eew === 2.U
def vd_eew64 = vd_eew === 3.U
val funct6 = UInt(6.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rd = UInt(5.W)
val vm = Bool()
val head = Bool()
val tail = Bool()
val vat = UInt(vParams.vatSz.W)
val acc = Bool()
val rm = UInt(3.W)
def vxrm = rm(1,0)
def frm = rm
}
class StoreDataMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val stdata = UInt(dLen.W)
val stmask = UInt(dLenB.W)
val debug_id = UInt(debugIdSz.W)
val tail = Bool()
val vat = UInt(vParams.vatSz.W)
def asMaskedBytes = {
val bytes = Wire(Vec(dLenB, new MaskedByte))
for (i <- 0 until dLenB) {
bytes(i).data := stdata(((i+1)*8)-1,i*8)
bytes(i).mask := stmask(i)
bytes(i).debug_id := debug_id
}
bytes
}
}
class LoadRespMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val wvd_eg = UInt(log2Ceil(egsTotal).W)
val wmask = UInt(dLenB.W)
val tail = Bool()
val debug_id = UInt(debugIdSz.W)
val vat = UInt(vParams.vatSz.W)
}
class PermuteMicroOp(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val renv2 = Bool()
val renvm = Bool()
val rvs2_data = UInt(dLen.W)
val eidx = UInt(log2Ceil(maxVLMax).W)
val rvs2_eew = UInt(2.W)
val rvm_data = UInt(dLen.W)
val vmu = Bool()
val vl = UInt((1+log2Ceil(maxVLMax)).W)
val tail = Bool()
}
class PipeHazard(pipe_depth: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val latency = UInt(log2Ceil(pipe_depth).W)
val eg = UInt(log2Ceil(egsTotal).W)
def eg_oh = UIntToOH(eg)
}
class SequencerHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val vat = UInt(vParams.vatSz.W)
val rintent = UInt(egsTotal.W)
val wintent = UInt(egsTotal.W)
}
class InstructionHazard(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val vat = UInt(vParams.vatSz.W)
val rintent = UInt(32.W)
val wintent = UInt(32.W)
}
| module LoadSegmenter( // @[LoadSegmenter.scala:11:7]
input clock, // @[LoadSegmenter.scala:11:7]
input reset, // @[LoadSegmenter.scala:11:7]
input io_valid, // @[LoadSegmenter.scala:12:14]
output io_done, // @[LoadSegmenter.scala:12:14]
input [15:0] io_op_debug_id, // @[LoadSegmenter.scala:12:14]
input [2:0] io_op_segstart, // @[LoadSegmenter.scala:12:14]
input [5:0] io_op_vstart, // @[LoadSegmenter.scala:12:14]
input [6:0] io_op_vl, // @[LoadSegmenter.scala:12:14]
input [2:0] io_op_nf, // @[LoadSegmenter.scala:12:14]
input [1:0] io_op_elem_size, // @[LoadSegmenter.scala:12:14]
input io_op_whole_reg, // @[LoadSegmenter.scala:12:14]
input io_compactor_ready, // @[LoadSegmenter.scala:12:14]
output io_compactor_valid, // @[LoadSegmenter.scala:12:14]
output [2:0] io_compactor_bits_head, // @[LoadSegmenter.scala:12:14]
output [2:0] io_compactor_bits_tail, // @[LoadSegmenter.scala:12:14]
input [63:0] io_compactor_data, // @[LoadSegmenter.scala:12:14]
input io_resp_ready, // @[LoadSegmenter.scala:12:14]
output io_resp_valid, // @[LoadSegmenter.scala:12:14]
output [63:0] io_resp_bits_data, // @[LoadSegmenter.scala:12:14]
output [15:0] io_resp_bits_debug_id // @[LoadSegmenter.scala:12:14]
);
wire _segbuf_io_in_ready; // @[LoadSegmenter.scala:26:22]
wire _segbuf_io_out_valid; // @[LoadSegmenter.scala:26:22]
wire [63:0] _segbuf_io_out_bits_data; // @[LoadSegmenter.scala:26:22]
wire [15:0] _segbuf_io_out_bits_debug_id; // @[LoadSegmenter.scala:26:22]
wire _segbuf_io_busy; // @[LoadSegmenter.scala:26:22]
reg [5:0] r_eidx; // @[LoadSegmenter.scala:28:19]
reg r_head; // @[LoadSegmenter.scala:29:23]
reg [2:0] r_sidx; // @[LoadSegmenter.scala:30:19]
wire [5:0] eidx = r_head ? io_op_vstart : r_eidx; // @[LoadSegmenter.scala:28:19, :29:23, :31:17]
wire [2:0] sidx = r_head ? io_op_segstart : r_sidx; // @[LoadSegmenter.scala:29:23, :30:19, :32:17]
wire [2:0] _seg_ready_T = io_op_whole_reg ? 3'h0 : io_op_nf; // @[Bundles.scala:33:19]
wire [5:0] _GEN = {3'h0, sidx}; // @[LoadSegmenter.scala:32:17, :35:29]
wire [8:0] _GEN_0 = {7'h0, io_op_elem_size}; // @[LoadSegmenter.scala:35:64]
wire [8:0] _incr_T_3 = {3'h0, (|_seg_ready_T) ? _GEN : eidx} << _GEN_0; // @[LoadSegmenter.scala:31:17, :35:{29,43,64}]
wire [3:0] incr = 4'h8 - {1'h0, _incr_T_3[2:0]} >> io_op_elem_size; // @[LoadSegmenter.scala:11:7, :35:{23,64,76,95}]
wire [6:0] next_eidx = {1'h0, eidx} + {3'h0, (|_seg_ready_T) ? 4'h1 : incr}; // @[LoadSegmenter.scala:11:7, :31:17, :35:95, :36:{22,36}, :38:24, :51:56]
wire [4:0] next_sidx = {2'h0, sidx} + {1'h0, incr}; // @[LoadSegmenter.scala:11:7, :32:17, :35:{23,95}, :39:24]
wire sidx_tail = next_sidx > {2'h0, _seg_ready_T}; // @[LoadSegmenter.scala:35:23, :39:24, :41:29]
wire eidx_tail = next_eidx >= io_op_vl; // @[LoadSegmenter.scala:38:24, :42:29]
wire [8:0] _io_compactor_bits_head_T = {3'h0, eidx} << _GEN_0; // @[LoadSegmenter.scala:31:17, :35:64, :46:36]
wire [9:0] _io_compactor_bits_tail_T = {3'h0, io_op_vl} << io_op_elem_size; // @[LoadSegmenter.scala:47:55]
wire [5:0] _io_compactor_bits_head_T_1 = _GEN << io_op_elem_size; // @[LoadSegmenter.scala:35:29, :50:36]
wire [6:0] _io_compactor_bits_tail_T_3 = {3'h0, {1'h0, io_op_nf} + 4'h1} << io_op_elem_size; // @[LoadSegmenter.scala:11:7, :51:{56,64}]
wire segbuf_io_in_valid = io_valid & (|_seg_ready_T) & io_compactor_ready; // @[LoadSegmenter.scala:54:{34,50,58}]
wire _GEN_1 = ((|_seg_ready_T) ? _segbuf_io_in_ready & io_compactor_ready & sidx_tail : ~_segbuf_io_busy & io_compactor_ready & io_resp_ready) & io_valid; // @[LoadSegmenter.scala:26:22, :35:43, :41:29, :74:22, :75:{5,21,43}, :76:{24,46}, :88:19]
wire _GEN_2 = _segbuf_io_in_ready & segbuf_io_in_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[LoadSegmenter.scala:11:7]
if (_GEN_1) // @[LoadSegmenter.scala:88:19]
r_eidx <= next_eidx[5:0]; // @[LoadSegmenter.scala:28:19, :38:24, :90:12]
else if (_GEN_2 & r_head) // @[Decoupled.scala:51:35]
r_eidx <= io_op_vstart; // @[LoadSegmenter.scala:28:19]
if (_GEN_2) // @[Decoupled.scala:51:35]
r_sidx <= next_sidx > {2'h0, io_op_nf} ? 3'h0 : next_sidx[2:0]; // @[LoadSegmenter.scala:30:19, :35:23, :39:24, :82:12, :83:{21,33}, :84:14]
if (reset) // @[LoadSegmenter.scala:11:7]
r_head <= 1'h1; // @[LoadSegmenter.scala:11:7, :29:23]
else // @[LoadSegmenter.scala:11:7]
r_head <= _GEN_1 ? eidx_tail : ~_GEN_2 & r_head; // @[Decoupled.scala:51:35]
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_preMul_e5_s11( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [16:0] io_a, // @[MulAddRecFN.scala:74:16]
input [16:0] io_b, // @[MulAddRecFN.scala:74:16]
input [16:0] io_c, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [10:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [21:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [6:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [3:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_isNaN = (&(io_a[15:14])) & io_a[13]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawB_isNaN = (&(io_b[15:14])) & io_b[13]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawC_isNaN = (&(io_c[15:14])) & io_c[13]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire signProd = io_a[16] ^ io_b[16] ^ io_op[1]; // @[rawFloatFromRecFN.scala:59:25]
wire [7:0] _sExpAlignedProd_T_1 = {2'h0, io_a[15:10]} + {2'h0, io_b[15:10]} - 8'h12; // @[rawFloatFromRecFN.scala:51:21]
wire doSubMags = signProd ^ io_c[16] ^ io_op[0]; // @[rawFloatFromRecFN.scala:59:25]
wire [7:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[15:10]}; // @[rawFloatFromRecFN.scala:51:21]
wire isMinCAlign = ~(|(io_a[15:13])) | ~(|(io_b[15:13])) | $signed(_sNatCAlignDist_T) < 8'sh0; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire CIsDominant = (|(io_c[15:13])) & (isMinCAlign | _sNatCAlignDist_T[6:0] < 7'hC); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire [5:0] CAlignDist = isMinCAlign ? 6'h0 : _sNatCAlignDist_T[6:0] < 7'h23 ? _sNatCAlignDist_T[5:0] : 6'h23; // @[MulAddRecFN.scala:106:42, :107:42, :108:{35,50}, :112:12, :114:{16,34}, :115:33]
wire [38:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[15:13])), ~(io_c[9:0])} : {1'h0, |(io_c[15:13]), io_c[9:0]}, {27{doSubMags}}}) >>> CAlignDist); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}]
wire [16:0] reduced4CExtra_shift = $signed(17'sh10000 >>> CAlignDist[5:2]); // @[primitives.scala:76:56]
wire [1:0] _GEN = {|(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[8], reduced4CExtra_shift[9]}; // @[primitives.scala:76:56, :77:20, :78:22, :120:{33,54}]
assign io_mulAddA = {|(io_a[15:13]), io_a[9:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddB = {|(io_b[15:13]), io_b[9:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddC = mainAlignedSigC[24:3]; // @[MulAddRecFN.scala:71:7, :120:100, :143:30]
assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[9]) | rawB_isNaN & ~(io_b[9]) | rawC_isNaN & ~(io_c[9]); // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfA = (&(io_a[15:14])) & ~(io_a[13]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroA = ~(|(io_a[15:13])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_isInfB = (&(io_b[15:14])) & ~(io_b[13]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroB = ~(|(io_b[15:13])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_signProd = signProd; // @[MulAddRecFN.scala:71:7, :97:{30,42}]
assign io_toPostMul_isNaNC = rawC_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfC = (&(io_c[15:14])) & ~(io_c[13]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroC = ~(|(io_c[15:13])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[15:10]} : _sExpAlignedProd_T_1[6:0] - 7'hB; // @[rawFloatFromRecFN.scala:51:21]
assign io_toPostMul_doSubMags = doSubMags; // @[MulAddRecFN.scala:71:7, :102:{30,42}]
assign io_toPostMul_CIsDominant = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
assign io_toPostMul_CDom_CAlignDist = CAlignDist[3:0]; // @[MulAddRecFN.scala:71:7, :112:12, :161:47]
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[37:25]; // @[MulAddRecFN.scala:71:7, :120:100, :163:20]
assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 2'h0 : (|{mainAlignedSigC[2:0], _GEN}); // @[MulAddRecFN.scala:71:7, :102:{30,42}, :120:100, :122:68, :130:11, :133:16, :134:{32,39,44}, :135:{39,44}]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_57( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74]
wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34]
wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34]
wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34]
wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_672; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [9:0] inflight; // @[Monitor.scala:614:27]
reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [39:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [9:0] a_set; // @[Monitor.scala:626:34]
wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [39:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [9:0] d_clr; // @[Monitor.scala:664:34]
wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [9:0] inflight_1; // @[Monitor.scala:726:35]
wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [9:0] d_clr_1; // @[Monitor.scala:774:34]
wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_24( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 3'h0; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_17( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_31 io_out_source_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_2( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1209 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1209; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1209; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1277 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1277; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1277; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1277; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1142 = _T_1209 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1142 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1142 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1142 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1142 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1142 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1188 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1188 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1157 = _T_1277 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1157 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1157 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1157 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1253 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1253 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1235 = _T_1277 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1235 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1235 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1235 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_160( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_58( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [13:0] source; // @[Monitor.scala:390:22]
reg [11:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [13:0] source_1; // @[Monitor.scala:541:22]
reg [8207:0] inflight; // @[Monitor.scala:614:27]
reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [8207:0] inflight_1; // @[Monitor.scala:726:35]
reg [32831:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_249( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_505 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit_155( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [19:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7]
wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54]
assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_182( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_199 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_55( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1151 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1151; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1151; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1224 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1224; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1224; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1224; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1074 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1074; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1074; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1151 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46]
wire _T_1123 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1123 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1092 = _T_1224 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1092 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1092 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1092 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1195 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1195 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1177 = _T_1224 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1177 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1177 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1177 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_148( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i64_e11_s53( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [64:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire intAsRawFloat_sign = io_signedIn & io_in[63]; // @[rawFloatFromIN.scala:51:{29,34}]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? 64'h0 - io_in : io_in; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [5:0] intAsRawFloat_adjustedNormDist =
intAsRawFloat_absIn[63]
? 6'h0
: intAsRawFloat_absIn[62]
? 6'h1
: intAsRawFloat_absIn[61]
? 6'h2
: intAsRawFloat_absIn[60] ? 6'h3 : intAsRawFloat_absIn[59] ? 6'h4 : intAsRawFloat_absIn[58] ? 6'h5 : intAsRawFloat_absIn[57] ? 6'h6 : intAsRawFloat_absIn[56] ? 6'h7 : intAsRawFloat_absIn[55] ? 6'h8 : intAsRawFloat_absIn[54] ? 6'h9 : intAsRawFloat_absIn[53] ? 6'hA : intAsRawFloat_absIn[52] ? 6'hB : intAsRawFloat_absIn[51] ? 6'hC : intAsRawFloat_absIn[50] ? 6'hD : intAsRawFloat_absIn[49] ? 6'hE : intAsRawFloat_absIn[48] ? 6'hF : intAsRawFloat_absIn[47] ? 6'h10 : intAsRawFloat_absIn[46] ? 6'h11 : intAsRawFloat_absIn[45] ? 6'h12 : intAsRawFloat_absIn[44] ? 6'h13 : intAsRawFloat_absIn[43] ? 6'h14 : intAsRawFloat_absIn[42] ? 6'h15 : intAsRawFloat_absIn[41] ? 6'h16 : intAsRawFloat_absIn[40] ? 6'h17 : intAsRawFloat_absIn[39] ? 6'h18 : intAsRawFloat_absIn[38] ? 6'h19 : intAsRawFloat_absIn[37] ? 6'h1A : intAsRawFloat_absIn[36] ? 6'h1B : intAsRawFloat_absIn[35] ? 6'h1C : intAsRawFloat_absIn[34] ? 6'h1D : intAsRawFloat_absIn[33] ? 6'h1E : intAsRawFloat_absIn[32] ? 6'h1F : intAsRawFloat_absIn[31] ? 6'h20 : intAsRawFloat_absIn[30] ? 6'h21 : intAsRawFloat_absIn[29] ? 6'h22 : intAsRawFloat_absIn[28] ? 6'h23 : intAsRawFloat_absIn[27] ? 6'h24 : intAsRawFloat_absIn[26] ? 6'h25 : intAsRawFloat_absIn[25] ? 6'h26 : intAsRawFloat_absIn[24] ? 6'h27 : intAsRawFloat_absIn[23] ? 6'h28 : intAsRawFloat_absIn[22] ? 6'h29 : intAsRawFloat_absIn[21] ? 6'h2A : intAsRawFloat_absIn[20] ? 6'h2B : intAsRawFloat_absIn[19] ? 6'h2C : intAsRawFloat_absIn[18] ? 6'h2D : intAsRawFloat_absIn[17] ? 6'h2E : intAsRawFloat_absIn[16] ? 6'h2F : intAsRawFloat_absIn[15] ? 6'h30 : intAsRawFloat_absIn[14] ? 6'h31 : intAsRawFloat_absIn[13] ? 6'h32 : intAsRawFloat_absIn[12] ? 6'h33 : intAsRawFloat_absIn[11] ? 6'h34 : intAsRawFloat_absIn[10] ? 6'h35 : intAsRawFloat_absIn[9] ? 6'h36 : intAsRawFloat_absIn[8] ? 6'h37 : intAsRawFloat_absIn[7] ? 6'h38 : intAsRawFloat_absIn[6] ? 6'h39 : intAsRawFloat_absIn[5] ? 6'h3A : intAsRawFloat_absIn[4] ? 6'h3B : intAsRawFloat_absIn[3] ? 6'h3C : intAsRawFloat_absIn[2] ? 6'h3D : {5'h1F, ~(intAsRawFloat_absIn[1])}; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_absIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
RoundAnyRawFNToRecFN_ie7_is64_oe11_os53 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (~(_intAsRawFloat_sig_T[63])), // @[rawFloatFromIN.scala:56:{22,41}, :62:{23,28}]
.io_in_sign (intAsRawFloat_sign), // @[rawFloatFromIN.scala:51:29]
.io_in_sExp ({3'h2, ~intAsRawFloat_adjustedNormDist}), // @[Mux.scala:50:70]
.io_in_sig ({1'h0, _intAsRawFloat_sig_T[63:0]}), // @[rawFloatFromIN.scala:52:31, :56:{22,41}, :65:20]
.io_roundingMode (io_roundingMode),
.io_out (io_out),
.io_exceptionFlags (io_exceptionFlags)
); // @[INToRecFN.scala:60:15]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UARTTx.scala:
package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
/** UARTTx module recives TL bus data from Tx fifo in parallel and transmits them to Port(Tx).
*
* ==datapass==
* TL bus -> Tx fifo -> io.in -> shifter -> Port(Tx)
*
* ==Structure==
* - baud rate divisor counter:
* generate pulse, the enable signal for data shift.
* - data shift logic:
* parallel in, serial out
*
* @note Tx fifo transmits TL bus data to Tx module
*/
class UARTTx(c: UARTParams) extends Module {
val io = IO(new Bundle {
/** Tx enable signal from top */
val en = Input(Bool())
/** data from Tx fifo */
val in = Flipped(Decoupled(UInt(c.dataBits.W)))
/** Tx port */
val out = Output(UInt(1.W))
/** divisor bits */
val div = Input(UInt(c.divisorBits.W))
/** number of stop bits */
val nstop = Input(UInt(log2Up(c.stopBits).W))
val tx_busy = Output(Bool())
/** parity enable */
val enparity = c.includeParity.option(Input(Bool()))
/** parity select
*
* 0 -> even parity
* 1 -> odd parity
*/
val parity = c.includeParity.option(Input(Bool()))
/** databit select
*
* ture -> 8
* false -> 9
*/
val data8or9 = (c.dataBits == 9).option(Input(Bool()))
/** clear to sned signal */
val cts_n = c.includeFourWire.option(Input(Bool()))
})
val prescaler = RegInit(0.U(c.divisorBits.W))
val pulse = (prescaler === 0.U)
private val n = c.dataBits + 1 + c.includeParity.toInt
/** contains databit(8or9), start bit, stop bit and parity bit*/
val counter = RegInit(0.U((log2Floor(n + c.stopBits) + 1).W))
val shifter = Reg(UInt(n.W))
val out = RegInit(1.U(1.W))
io.out := out
val plusarg_tx = PlusArg("uart_tx", 1, "Enable/disable the TX to speed up simulation").orR
val plusarg_printf = PlusArg("uart_tx_printf", 0, "Enable/disable the TX printf").orR
val busy = (counter =/= 0.U)
io.in.ready := io.en && !busy
io.tx_busy := busy
when (io.in.fire && plusarg_printf) {
printf("UART TX (%x): %c\n", io.in.bits, io.in.bits)
}
when (io.in.fire && plusarg_tx) {
if (c.includeParity) {
val includebit9 = if (c.dataBits == 9) Mux(io.data8or9.get, false.B, io.in.bits(8)) else false.B
val parity = Mux(io.enparity.get, includebit9 ^ io.in.bits(7,0).asBools.reduce(_ ^ _) ^ io.parity.get, true.B)
val paritywithbit9 = if (c.dataBits == 9) Mux(io.data8or9.get, Cat(1.U(1.W), parity), Cat(parity, io.in.bits(8)))
else Cat(1.U(1.W), parity)
shifter := Cat(paritywithbit9, io.in.bits(7,0), 0.U(1.W))
counter := Mux1H((0 until c.stopBits).map(i =>
(io.nstop === i.U) -> (n + i + 1).U)) - (!io.enparity.get).asUInt - io.data8or9.getOrElse(0.U)
// n = max number of databits configured at elaboration + start bit + parity bit
// n + i + 1 = n + stop bits + pad bit(when counter === 0 no bit is transmitted)
// n + i + 1 - 8_bit_mode(if c.dataBits == 9) - parity_disabled_at_runtime
}
else {
val bit9 = if (c.dataBits == 9) Mux(io.data8or9.get, 1.U(1.W), io.in.bits(8)) else 1.U(1.W)
shifter := Cat(bit9, io.in.bits(7,0), 0.U(1.W))
counter := Mux1H((0 until c.stopBits).map(i =>
(io.nstop === i.U) -> (n + i + 1).U)) - io.data8or9.getOrElse(0.U)
}
}
when (busy) {
prescaler := Mux(pulse || io.cts_n.getOrElse(false.B), io.div, prescaler - 1.U)
}
when (pulse && busy) {
counter := counter - 1.U
shifter := Cat(1.U(1.W), shifter >> 1)
out := shifter(0)
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
| module UARTTx_TestHarness_UNIQUIFIED( // @[UARTTx.scala:21:7]
input clock, // @[UARTTx.scala:21:7]
input reset, // @[UARTTx.scala:21:7]
input io_en, // @[UARTTx.scala:22:14]
output io_in_ready, // @[UARTTx.scala:22:14]
input io_in_valid, // @[UARTTx.scala:22:14]
input [7:0] io_in_bits, // @[UARTTx.scala:22:14]
output io_out, // @[UARTTx.scala:22:14]
input [15:0] io_div, // @[UARTTx.scala:22:14]
input io_nstop // @[UARTTx.scala:22:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
reg [15:0] prescaler; // @[UARTTx.scala:52:26]
reg [3:0] counter; // @[UARTTx.scala:57:24]
reg [8:0] shifter; // @[UARTTx.scala:58:20]
reg out; // @[UARTTx.scala:59:20]
wire io_in_ready_0 = io_en & ~(|counter); // @[UARTTx.scala:57:24, :65:23, :66:{24,27}]
wire _GEN = io_in_ready_0 & io_in_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_151( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_271 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File MuxLiteral.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.log2Ceil
import scala.reflect.ClassTag
/* MuxLiteral creates a lookup table from a key to a list of values.
* Unlike MuxLookup, the table keys must be exclusive literals.
*/
object MuxLiteral
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T =
MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) })
}
object MuxSeq
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T =
MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) })
}
object MuxTable
{
def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)*): T =
apply(index, default, first :: rest.toList)
def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = {
/* All keys must be >= 0 and distinct */
cases.foreach { case (k, _) => require (k >= 0) }
require (cases.map(_._1).distinct.size == cases.size)
/* Filter out any cases identical to the default */
val simple = cases.filter { case (k, v) => !default.isLit || !v.isLit || v.litValue != default.litValue }
val maxKey = (BigInt(0) +: simple.map(_._1)).max
val endIndex = BigInt(1) << log2Ceil(maxKey+1)
if (simple.isEmpty) {
default
} else if (endIndex <= 2*simple.size) {
/* The dense encoding case uses a Vec */
val table = Array.fill(endIndex.toInt) { default }
simple.foreach { case (k, v) => table(k.toInt) = v }
Mux(index >= endIndex.U, default, VecInit(table)(index))
} else {
/* The sparse encoding case uses switch */
val out = WireDefault(default)
simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) =>
acc.is (k.U) { out := v }
}
out
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Control.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
class InclusiveCacheControl(outer: InclusiveCache, control: InclusiveCacheControlParameters)(implicit p: Parameters) extends LazyModule()(p) {
val ctrlnode = TLRegisterNode(
address = Seq(AddressSet(control.address, InclusiveCacheParameters.L2ControlSize-1)),
device = outer.device,
concurrency = 1, // Only one flush at a time (else need to track who answers)
beatBytes = control.beatBytes)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val io = IO(new Bundle {
val flush_match = Input(Bool())
val flush_req = Decoupled(UInt(64.W))
val flush_resp = Input(Bool())
})
// Flush directive
val flushInValid = RegInit(false.B)
val flushInAddress = Reg(UInt(64.W))
val flushOutValid = RegInit(false.B)
val flushOutReady = WireInit(init = false.B)
when (flushOutReady) { flushOutValid := false.B }
when (io.flush_resp) { flushOutValid := true.B }
when (io.flush_req.ready) { flushInValid := false.B }
io.flush_req.valid := flushInValid
io.flush_req.bits := flushInAddress
when (!io.flush_match && flushInValid) {
flushInValid := false.B
flushOutValid := true.B
}
val flush32 = RegField.w(32, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data << 4 }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush32", "Flush the physical address equal to the 32-bit written data << 4 from the cache"))
val flush64 = RegField.w(64, RegWriteFn((ivalid, oready, data) => {
when (oready) { flushOutReady := true.B }
when (ivalid) { flushInValid := true.B }
when (ivalid && !flushInValid) { flushInAddress := data }
(!flushInValid, flushOutValid)
}), RegFieldDesc("Flush64", "Flush the phsyical address equal to the 64-bit written data from the cache"))
// Information about the cache configuration
val banksR = RegField.r(8, outer.node.edges.in.size.U, RegFieldDesc("Banks",
"Number of banks in the cache", reset=Some(outer.node.edges.in.size)))
val waysR = RegField.r(8, outer.cache.ways.U, RegFieldDesc("Ways",
"Number of ways per bank", reset=Some(outer.cache.ways)))
val lgSetsR = RegField.r(8, log2Ceil(outer.cache.sets).U, RegFieldDesc("lgSets",
"Base-2 logarithm of the sets per bank", reset=Some(log2Ceil(outer.cache.sets))))
val lgBlockBytesR = RegField.r(8, log2Ceil(outer.cache.blockBytes).U, RegFieldDesc("lgBlockBytes",
"Base-2 logarithm of the bytes per cache block", reset=Some(log2Ceil(outer.cache.blockBytes))))
val regmap = ctrlnode.regmap(
0x000 -> RegFieldGroup("Config", Some("Information about the Cache Configuration"), Seq(banksR, waysR, lgSetsR, lgBlockBytesR)),
0x200 -> (if (control.beatBytes >= 8) Seq(flush64) else Nil),
0x240 -> Seq(flush32)
)
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module InclusiveCacheControl( // @[Control.scala:38:9]
input clock, // @[Control.scala:38:9]
input reset, // @[Control.scala:38:9]
output auto_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input io_flush_match, // @[Control.scala:39:16]
input io_flush_req_ready, // @[Control.scala:39:16]
output io_flush_req_valid, // @[Control.scala:39:16]
output [63:0] io_flush_req_bits, // @[Control.scala:39:16]
input io_flush_resp // @[Control.scala:39:16]
);
wire out_bits_read; // @[RegisterRouter.scala:87:24]
wire [13:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [8:0] in_bits_index; // @[RegisterRouter.scala:73:18]
wire in_bits_read; // @[RegisterRouter.scala:73:18]
wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24]
wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire [8:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24]
wire auto_ctrl_in_a_valid_0 = auto_ctrl_in_a_valid; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_opcode_0 = auto_ctrl_in_a_bits_opcode; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_a_bits_param_0 = auto_ctrl_in_a_bits_param; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_a_bits_size_0 = auto_ctrl_in_a_bits_size; // @[Control.scala:38:9]
wire [13:0] auto_ctrl_in_a_bits_source_0 = auto_ctrl_in_a_bits_source; // @[Control.scala:38:9]
wire [25:0] auto_ctrl_in_a_bits_address_0 = auto_ctrl_in_a_bits_address; // @[Control.scala:38:9]
wire [7:0] auto_ctrl_in_a_bits_mask_0 = auto_ctrl_in_a_bits_mask; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_a_bits_data_0 = auto_ctrl_in_a_bits_data; // @[Control.scala:38:9]
wire auto_ctrl_in_a_bits_corrupt_0 = auto_ctrl_in_a_bits_corrupt; // @[Control.scala:38:9]
wire auto_ctrl_in_d_ready_0 = auto_ctrl_in_d_ready; // @[Control.scala:38:9]
wire io_flush_match_0 = io_flush_match; // @[Control.scala:38:9]
wire io_flush_req_ready_0 = io_flush_req_ready; // @[Control.scala:38:9]
wire io_flush_resp_0 = io_flush_resp; // @[Control.scala:38:9]
wire [3:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h60A0801};
wire [8:0] out_maskMatch = 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_13 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_14 = 8'h1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_prepend_T = 8'h1; // @[RegisterRouter.scala:87:24]
wire [11:0] out_prepend = 12'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_22 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_T_23 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [15:0] _out_prepend_T_1 = 16'h801; // @[RegisterRouter.scala:87:24]
wire [19:0] out_prepend_1 = 20'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_31 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_T_32 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [23:0] _out_prepend_T_2 = 24'hA0801; // @[RegisterRouter.scala:87:24]
wire [26:0] out_prepend_2 = 27'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_40 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_41 = 32'h60A0801; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_66 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_67 = 32'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_0 = 64'h60A0801; // @[MuxLiteral.scala:49:48]
wire [2:0] ctrlnodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17]
wire [63:0] _out_T_53 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_54 = 64'h0; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_WIRE_1_1 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_2 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48]
wire [63:0] ctrlnodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17]
wire auto_ctrl_in_d_bits_sink = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_denied = 1'h0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_bits_corrupt = 1'h0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17]
wire ctrlnodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17]
wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17]
wire ctrlnodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17]
wire [1:0] auto_ctrl_in_d_bits_param = 2'h0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17]
wire ctrlnodeIn_a_ready; // @[MixedNode.scala:551:17]
wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48]
wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10]
wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48]
wire ctrlnodeIn_a_valid = auto_ctrl_in_a_valid_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_opcode = auto_ctrl_in_a_bits_opcode_0; // @[Control.scala:38:9]
wire [2:0] ctrlnodeIn_a_bits_param = auto_ctrl_in_a_bits_param_0; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_a_bits_size = auto_ctrl_in_a_bits_size_0; // @[Control.scala:38:9]
wire [13:0] ctrlnodeIn_a_bits_source = auto_ctrl_in_a_bits_source_0; // @[Control.scala:38:9]
wire [25:0] ctrlnodeIn_a_bits_address = auto_ctrl_in_a_bits_address_0; // @[Control.scala:38:9]
wire [7:0] ctrlnodeIn_a_bits_mask = auto_ctrl_in_a_bits_mask_0; // @[Control.scala:38:9]
wire [63:0] ctrlnodeIn_a_bits_data = auto_ctrl_in_a_bits_data_0; // @[Control.scala:38:9]
wire ctrlnodeIn_a_bits_corrupt = auto_ctrl_in_a_bits_corrupt_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_ready = auto_ctrl_in_d_ready_0; // @[Control.scala:38:9]
wire ctrlnodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] ctrlnodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] ctrlnodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [13:0] ctrlnodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [63:0] ctrlnodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
wire [2:0] auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
wire [1:0] auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
wire [13:0] auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
wire [63:0] auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
wire auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
wire io_flush_req_valid_0; // @[Control.scala:38:9]
wire [63:0] io_flush_req_bits_0; // @[Control.scala:38:9]
wire in_ready; // @[RegisterRouter.scala:73:18]
assign auto_ctrl_in_a_ready_0 = ctrlnodeIn_a_ready; // @[Control.scala:38:9]
wire in_valid = ctrlnodeIn_a_valid; // @[RegisterRouter.scala:73:18]
wire [1:0] in_bits_extra_tlrr_extra_size = ctrlnodeIn_a_bits_size; // @[RegisterRouter.scala:73:18]
wire [13:0] in_bits_extra_tlrr_extra_source = ctrlnodeIn_a_bits_source; // @[RegisterRouter.scala:73:18]
wire [7:0] in_bits_mask = ctrlnodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18]
wire [63:0] in_bits_data = ctrlnodeIn_a_bits_data; // @[RegisterRouter.scala:73:18]
wire out_ready = ctrlnodeIn_d_ready; // @[RegisterRouter.scala:87:24]
wire out_valid; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_valid_0 = ctrlnodeIn_d_valid; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode_0 = ctrlnodeIn_d_bits_opcode; // @[Control.scala:38:9]
wire [1:0] ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_size_0 = ctrlnodeIn_d_bits_size; // @[Control.scala:38:9]
wire [13:0] ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign auto_ctrl_in_d_bits_source_0 = ctrlnodeIn_d_bits_source; // @[Control.scala:38:9]
wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_d_bits_data_0 = ctrlnodeIn_d_bits_data; // @[Control.scala:38:9]
reg flushInValid; // @[Control.scala:45:33]
assign io_flush_req_valid_0 = flushInValid; // @[Control.scala:38:9, :45:33]
reg [63:0] flushInAddress; // @[Control.scala:46:29]
assign io_flush_req_bits_0 = flushInAddress; // @[Control.scala:38:9, :46:29]
reg flushOutValid; // @[Control.scala:47:33]
wire flushOutReady; // @[Control.scala:48:34]
wire _out_in_ready_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18]
wire _in_bits_read_T; // @[RegisterRouter.scala:74:36]
wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24]
wire [8:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24]
wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24]
wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24]
wire [13:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24]
wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24]
assign _in_bits_read_T = ctrlnodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36]
assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36]
wire [22:0] _in_bits_index_T = ctrlnodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34]
assign in_bits_index = _in_bits_index_T[8:0]; // @[RegisterRouter.scala:73:18, :75:19]
wire _out_out_valid_T; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
wire _ctrlnodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25]
assign ctrlnodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24]
wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24]
wire _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_T_42 = out_front_bits_data; // @[RegisterRouter.scala:87:24]
wire out_front_ready; // @[RegisterRouter.scala:87:24]
wire out_front_valid; // @[RegisterRouter.scala:87:24]
wire [8:0] out_findex = out_front_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire [8:0] out_bindex = _out_back_front_q_io_deq_bits_index & 9'h1B7; // @[RegisterRouter.scala:87:24]
wire _GEN_0 = out_findex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T; // @[RegisterRouter.scala:87:24]
assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_2; // @[RegisterRouter.scala:87:24]
assign _out_T_2 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _out_T_4; // @[RegisterRouter.scala:87:24]
assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24]
wire _GEN_1 = out_bindex == 9'h0; // @[RegisterRouter.scala:87:24]
wire _out_T_1; // @[RegisterRouter.scala:87:24]
assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_3; // @[RegisterRouter.scala:87:24]
assign _out_T_3 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_T_5; // @[RegisterRouter.scala:87:24]
assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48]
wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_out_bits_data_WIRE_3 = _out_T_5; // @[MuxLiteral.scala:49:48]
wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_rivalid_0; // @[RegisterRouter.scala:87:24]
wire out_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_rivalid_4; // @[RegisterRouter.scala:87:24]
wire out_rivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wivalid_0; // @[RegisterRouter.scala:87:24]
wire out_wivalid_1; // @[RegisterRouter.scala:87:24]
wire out_wivalid_2; // @[RegisterRouter.scala:87:24]
wire out_wivalid_3; // @[RegisterRouter.scala:87:24]
wire out_wivalid_4; // @[RegisterRouter.scala:87:24]
wire out_wivalid_5; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire out_roready_0; // @[RegisterRouter.scala:87:24]
wire out_roready_1; // @[RegisterRouter.scala:87:24]
wire out_roready_2; // @[RegisterRouter.scala:87:24]
wire out_roready_3; // @[RegisterRouter.scala:87:24]
wire out_roready_4; // @[RegisterRouter.scala:87:24]
wire out_roready_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_woready_0; // @[RegisterRouter.scala:87:24]
wire out_woready_1; // @[RegisterRouter.scala:87:24]
wire out_woready_2; // @[RegisterRouter.scala:87:24]
wire out_woready_3; // @[RegisterRouter.scala:87:24]
wire out_woready_4; // @[RegisterRouter.scala:87:24]
wire out_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_rimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_wimask_T_4 = out_frontMask; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24]
wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24]
wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24]
wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_romask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [63:0] _out_womask_T_4 = out_backMask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask = |_out_rimask_T; // @[RegisterRouter.scala:87:24]
wire out_wimask = &_out_wimask_T; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T = out_backMask[7:0]; // @[RegisterRouter.scala:87:24]
wire out_romask = |_out_romask_T; // @[RegisterRouter.scala:87:24]
wire out_womask = &_out_womask_T; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24]
wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24]
wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_6 = _out_back_front_q_io_deq_bits_data[7:0]; // @[RegisterRouter.scala:87:24]
wire _out_T_9 = ~out_rimask; // @[RegisterRouter.scala:87:24]
wire _out_T_10 = ~out_wimask; // @[RegisterRouter.scala:87:24]
wire _out_T_11 = ~out_romask; // @[RegisterRouter.scala:87:24]
wire _out_T_12 = ~out_womask; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_1 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24]
wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_1 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24]
wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24]
wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_16 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24]
wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_17 = out_f_roready_1; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24]
wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_15 = _out_back_front_q_io_deq_bits_data[15:8]; // @[RegisterRouter.scala:87:24]
wire _out_T_18 = ~out_rimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_19 = ~out_wimask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_20 = ~out_romask_1; // @[RegisterRouter.scala:87:24]
wire _out_T_21 = ~out_womask_1; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_2 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24]
wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_2 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24]
wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24]
wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_25 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24]
wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_26 = out_f_roready_2; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24]
wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_24 = _out_back_front_q_io_deq_bits_data[23:16]; // @[RegisterRouter.scala:87:24]
wire _out_T_27 = ~out_rimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_28 = ~out_wimask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_29 = ~out_romask_2; // @[RegisterRouter.scala:87:24]
wire _out_T_30 = ~out_womask_2; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_rimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_wimask_T_3 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24]
wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_romask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_womask_T_3 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24]
wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24]
wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_34 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24]
wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_35 = out_f_roready_3; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24]
wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24]
wire [7:0] _out_T_33 = _out_back_front_q_io_deq_bits_data[31:24]; // @[RegisterRouter.scala:87:24]
wire _out_T_36 = ~out_rimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_37 = ~out_wimask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_38 = ~out_romask_3; // @[RegisterRouter.scala:87:24]
wire _out_T_39 = ~out_womask_3; // @[RegisterRouter.scala:87:24]
wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24]
wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24]
wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24]
wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_43 = ~flushInValid; // @[Control.scala:45:33, :71:23]
wire _out_T_44 = out_f_wivalid_4 & _out_T_43; // @[RegisterRouter.scala:87:24]
wire out_f_wiready = ~flushInValid; // @[Control.scala:45:33, :71:23, :72:8]
wire _out_T_45 = out_f_wivalid_4 & out_f_wiready; // @[RegisterRouter.scala:87:24]
wire _out_T_46 = flushOutValid & out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_47 = ~out_rimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_48 = ~out_wimask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_49 = out_f_wiready | _out_T_48; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_2 = _out_T_49; // @[RegisterRouter.scala:87:24]
wire _out_T_50 = ~out_romask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_51 = ~out_womask_4; // @[RegisterRouter.scala:87:24]
wire _out_T_52 = flushOutValid | _out_T_51; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_2 = _out_T_52; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_rimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_wimask_T_5 = out_frontMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24]
wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_romask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_womask_T_5 = out_backMask[31:0]; // @[RegisterRouter.scala:87:24]
wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24]
wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24]
wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24]
wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24]
wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24]
wire [31:0] _out_T_55 = out_front_bits_data[31:0]; // @[RegisterRouter.scala:87:24]
assign flushOutReady = out_f_woready_5 | out_f_woready_4; // @[RegisterRouter.scala:87:24]
wire _out_T_56 = ~flushInValid; // @[Control.scala:45:33, :64:23, :71:23]
wire _out_T_57 = out_f_wivalid_5 & _out_T_56; // @[RegisterRouter.scala:87:24]
wire [35:0] _out_flushInAddress_T = {_out_T_55, 4'h0}; // @[RegisterRouter.scala:87:24]
wire out_f_wiready_1 = ~flushInValid; // @[Control.scala:45:33, :65:8, :71:23]
wire _out_T_58 = out_f_wivalid_5 & out_f_wiready_1; // @[RegisterRouter.scala:87:24]
wire _out_T_59 = flushOutValid & out_f_woready_5; // @[RegisterRouter.scala:87:24]
wire _out_T_60 = ~out_rimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_61 = ~out_wimask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_62 = out_f_wiready_1 | _out_T_61; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_out_3 = _out_T_62; // @[RegisterRouter.scala:87:24]
wire _out_T_63 = ~out_romask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_64 = ~out_womask_5; // @[RegisterRouter.scala:87:24]
wire _out_T_65 = flushOutValid | _out_T_64; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_out_3 = _out_T_65; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_iindex = {_out_iindex_T_6, _out_iindex_T_3}; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T = _out_back_front_q_io_deq_bits_index[0]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_1 = _out_back_front_q_io_deq_bits_index[1]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_2 = _out_back_front_q_io_deq_bits_index[2]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_3 = _out_back_front_q_io_deq_bits_index[3]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_4 = _out_back_front_q_io_deq_bits_index[4]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_5 = _out_back_front_q_io_deq_bits_index[5]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_6 = _out_back_front_q_io_deq_bits_index[6]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_7 = _out_back_front_q_io_deq_bits_index[7]; // @[RegisterRouter.scala:87:24]
wire _out_oindex_T_8 = _out_back_front_q_io_deq_bits_index[8]; // @[RegisterRouter.scala:87:24]
wire [1:0] out_oindex = {_out_oindex_T_6, _out_oindex_T_3}; // @[RegisterRouter.scala:87:24]
wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35]
wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35]
wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35]
wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35]
wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35]
wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35]
wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35]
wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35]
wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35]
wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35]
wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24]
wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_2 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_rivalid_3 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_7 = _out_rifireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rifireMux_T_15 = _out_rifireMux_T_14 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_rivalid_5 = _out_rifireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rifireMux_T_16 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24]
assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_2 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_3 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_8 = _out_wifireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24]
assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all = _out_wifireMux_T_12 & _out_T_49; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_14 = out_wifireMux_out_2 | _out_wifireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_2 = _out_wifireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wifireMux_T_16 = _out_wifireMux_T_15 & _out_T_4; // @[RegisterRouter.scala:87:24]
assign out_wivalid_5 = _out_wifireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wifireMux_all_1 = _out_wifireMux_T_16 & _out_T_62; // @[ReduceOthers.scala:47:21]
wire _out_wifireMux_T_17 = ~_out_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_T_18 = out_wifireMux_out_3 | _out_wifireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wifireMux_WIRE_3 = _out_wifireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_3 = {{_out_wifireMux_WIRE_3}, {_out_wifireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wifireMux = _GEN_3[out_iindex]; // @[MuxLiteral.scala:49:10]
wire _GEN_4 = _out_back_front_q_io_deq_valid & out_ready; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T = _GEN_4; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_1 = _out_rofireMux_T & _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_2 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_3 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_7 = _out_rofireMux_T_6; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_rofireMux_T_15 = _out_rofireMux_T_14 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_roready_5 = _out_rofireMux_T_15; // @[RegisterRouter.scala:87:24]
wire _out_rofireMux_T_16 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_1 = ~_out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24]
assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_2 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
assign out_woready_3 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_8 = _out_wofireMux_T_7; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24]
assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all = _out_wofireMux_T_12 & _out_T_52; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_14 = out_wofireMux_out_2 | _out_wofireMux_T_13; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_2 = _out_wofireMux_T_14; // @[MuxLiteral.scala:49:48]
wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24]
assign _out_wofireMux_T_16 = _out_wofireMux_T_15 & _out_T_5; // @[RegisterRouter.scala:87:24]
assign out_woready_5 = _out_wofireMux_T_16; // @[RegisterRouter.scala:87:24]
wire out_wofireMux_all_1 = _out_wofireMux_T_16 & _out_T_65; // @[ReduceOthers.scala:47:21]
wire _out_wofireMux_T_17 = ~_out_T_5; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_T_18 = out_wofireMux_out_3 | _out_wofireMux_T_17; // @[RegisterRouter.scala:87:24]
wire _out_wofireMux_WIRE_3 = _out_wofireMux_T_18; // @[MuxLiteral.scala:49:48]
wire [3:0] _GEN_5 = {{_out_wofireMux_WIRE_3}, {_out_wofireMux_WIRE_2}, {1'h1}, {1'h1}}; // @[MuxLiteral.scala:49:{10,48}]
wire out_wofireMux = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10]
wire out_iready = out_front_bits_read | out_wifireMux; // @[MuxLiteral.scala:49:10]
wire out_oready = _out_back_front_q_io_deq_bits_read | out_wofireMux; // @[MuxLiteral.scala:49:10]
assign _out_in_ready_T = out_front_ready & out_iready; // @[RegisterRouter.scala:87:24]
assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24]
assign _out_front_valid_T = in_valid & out_iready; // @[RegisterRouter.scala:73:18, :87:24]
assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24]
wire _out_front_q_io_deq_ready_T = out_ready & out_oready; // @[RegisterRouter.scala:87:24]
assign _out_out_valid_T = _out_back_front_q_io_deq_valid & out_oready; // @[RegisterRouter.scala:87:24]
assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24]
wire [3:0] _GEN_6 = {{_out_out_bits_data_WIRE_3}, {_out_out_bits_data_WIRE_2}, {1'h1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}]
wire _out_out_bits_data_T_1 = _GEN_6[out_oindex]; // @[MuxLiteral.scala:49:10]
wire [63:0] _out_out_bits_data_T_3 = _GEN[out_oindex]; // @[MuxLiteral.scala:49:10]
assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10]
assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24]
assign ctrlnodeIn_d_bits_size = ctrlnodeIn_d_bits_d_size; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_source = ctrlnodeIn_d_bits_d_source; // @[Edges.scala:792:17]
assign ctrlnodeIn_d_bits_opcode = {2'h0, _ctrlnodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}]
wire _T_1 = ~io_flush_match_0 & flushInValid; // @[Control.scala:38:9, :45:33, :56:{11,27}]
always @(posedge clock) begin // @[Control.scala:38:9]
if (reset) begin // @[Control.scala:38:9]
flushInValid <= 1'h0; // @[Control.scala:45:33]
flushOutValid <= 1'h0; // @[Control.scala:47:33]
end
else begin // @[Control.scala:38:9]
flushInValid <= out_f_wivalid_5 | out_f_wivalid_4 | ~(_T_1 | io_flush_req_ready_0) & flushInValid; // @[RegisterRouter.scala:87:24]
flushOutValid <= _T_1 | io_flush_resp_0 | ~flushOutReady & flushOutValid; // @[Control.scala:38:9, :47:33, :48:34, :50:{26,42}, :51:{26,42}, :56:{27,44}, :58:21]
end
if (_out_T_57) // @[Control.scala:64:20]
flushInAddress <= {28'h0, _out_flushInAddress_T}; // @[Control.scala:46:29, :64:{55,63}]
else if (_out_T_44) // @[Control.scala:71:20]
flushInAddress <= _out_T_42; // @[RegisterRouter.scala:87:24]
always @(posedge)
TLMonitor_51 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (ctrlnodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (ctrlnodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (ctrlnodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (ctrlnodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (ctrlnodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (ctrlnodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (ctrlnodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (ctrlnodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (ctrlnodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (ctrlnodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (ctrlnodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (ctrlnodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (ctrlnodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (ctrlnodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (ctrlnodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (ctrlnodeIn_d_bits_data) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue1_RegMapperInput_i9_m8 out_back_front_q ( // @[RegisterRouter.scala:87:24]
.clock (clock),
.reset (reset),
.io_enq_ready (out_front_ready),
.io_enq_valid (out_front_valid), // @[RegisterRouter.scala:87:24]
.io_enq_bits_read (out_front_bits_read), // @[RegisterRouter.scala:87:24]
.io_enq_bits_index (out_front_bits_index), // @[RegisterRouter.scala:87:24]
.io_enq_bits_data (out_front_bits_data), // @[RegisterRouter.scala:87:24]
.io_enq_bits_mask (out_front_bits_mask), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_source (out_front_bits_extra_tlrr_extra_source), // @[RegisterRouter.scala:87:24]
.io_enq_bits_extra_tlrr_extra_size (out_front_bits_extra_tlrr_extra_size), // @[RegisterRouter.scala:87:24]
.io_deq_ready (_out_front_q_io_deq_ready_T), // @[RegisterRouter.scala:87:24]
.io_deq_valid (_out_back_front_q_io_deq_valid),
.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
.io_deq_bits_extra_tlrr_extra_source (out_bits_extra_tlrr_extra_source),
.io_deq_bits_extra_tlrr_extra_size (out_bits_extra_tlrr_extra_size)
); // @[RegisterRouter.scala:87:24]
assign out_bits_read = _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24]
assign auto_ctrl_in_a_ready = auto_ctrl_in_a_ready_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_valid = auto_ctrl_in_d_valid_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_opcode = auto_ctrl_in_d_bits_opcode_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_size = auto_ctrl_in_d_bits_size_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_source = auto_ctrl_in_d_bits_source_0; // @[Control.scala:38:9]
assign auto_ctrl_in_d_bits_data = auto_ctrl_in_d_bits_data_0; // @[Control.scala:38:9]
assign io_flush_req_valid = io_flush_req_valid_0; // @[Control.scala:38:9]
assign io_flush_req_bits = io_flush_req_bits_0; // @[Control.scala:38:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Plic.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.tilelink
import chisel3._
import chisel3.experimental._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet}
import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice}
import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode}
import freechips.rocketchip.util.{Annotated, MuxT, property}
import scala.math.min
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.SeqToAugmentedSeq
class GatewayPLICIO extends Bundle {
val valid = Output(Bool())
val ready = Input(Bool())
val complete = Input(Bool())
}
class LevelGateway extends Module {
val io = IO(new Bundle {
val interrupt = Input(Bool())
val plic = new GatewayPLICIO
})
val inFlight = RegInit(false.B)
when (io.interrupt && io.plic.ready) { inFlight := true.B }
when (io.plic.complete) { inFlight := false.B }
io.plic.valid := io.interrupt && !inFlight
}
object PLICConsts
{
def maxDevices = 1023
def maxMaxHarts = 15872
def priorityBase = 0x0
def pendingBase = 0x1000
def enableBase = 0x2000
def hartBase = 0x200000
def claimOffset = 4
def priorityBytes = 4
def enableOffset(i: Int) = i * ((maxDevices+7)/8)
def hartOffset(i: Int) = i * 0x1000
def enableBase(i: Int):Int = enableOffset(i) + enableBase
def hartBase(i: Int):Int = hartOffset(i) + hartBase
def size(maxHarts: Int): Int = {
require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}")
1 << log2Ceil(hartBase(maxHarts))
}
require(hartBase >= enableBase(maxMaxHarts))
}
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1)
}
case object PLICKey extends Field[Option[PLICParams]](None)
case class PLICAttachParams(
slaveWhere: TLBusWrapperLocation = CBUS
)
case object PLICAttachKey extends Field(PLICAttachParams())
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
val extra = Map(
"interrupt-controller" -> Nil,
"riscv,ndev" -> Seq(ResourceInt(nDevices)),
"riscv,max-priority" -> Seq(ResourceInt(nPriorities)),
"#interrupt-cells" -> Seq(ResourceInt(1)))
Description(name, mapping ++ extra)
}
}
val node : TLRegisterNode = TLRegisterNode(
address = Seq(params.address),
device = device,
beatBytes = beatBytes,
undefZero = true,
concurrency = 1) // limiting concurrency handles RAW hazards on claim registers
val intnode: IntNexusNode = IntNexusNode(
sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) },
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
outputRequiresInput = false,
inputRequiresOutput = false)
/* Negotiated sizes */
def nDevices: Int = intnode.edges.in.map(_.source.num).sum
def minPriorities = min(params.maxPriorities, nDevices)
def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1
def nHarts = intnode.edges.out.map(_.source.num).sum
// Assign all the devices unique ranges
lazy val sources = intnode.edges.in.map(_.source)
lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten
ResourceBinding {
flatSources.foreach { s => s.resources.foreach { r =>
// +1 because interrupt 0 is reserved
(s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) }
} }
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
Annotated.params(this, params)
val (io_devices, edgesIn) = intnode.in.unzip
val (io_harts, _) = intnode.out.unzip
// Compact the interrupt vector the same way
val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
// This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence
val harts = io_harts.flatten
def getNInterrupts = interrupts.size
println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):")
flatSources.foreach { s =>
// +1 because 0 is reserved, +1-1 because the range is half-open
println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}")
}
println("")
require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}")
require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}")
require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}")
require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}")
// For now, use LevelGateways for all TL2 interrupts
val gateways = interrupts.map { case i =>
val gateway = Module(new LevelGateway)
gateway.io.interrupt := i
gateway.io.plic
}
val prioBits = log2Ceil(nPriorities+1)
val priority =
if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nDevices max 1)(1.U))
val threshold =
if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W)))
else WireDefault(VecInit.fill(nHarts)(0.U))
val pending = RegInit(VecInit.fill(nDevices max 1){false.B})
/* Construct the enable registers, chunked into 8-bit segments to reduce verilog size */
val firstEnable = nDevices min 7
val fullEnables = (nDevices - firstEnable) / 8
val tailEnable = nDevices - firstEnable - 8*fullEnables
def enableRegs = (Reg(UInt(firstEnable.W)) +:
Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++
(if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None)
val enables = Seq.fill(nHarts) { enableRegs }
val enableVec = VecInit(enables.map(x => Cat(x.reverse)))
val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W))))
val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W)))
val pendingUInt = Cat(pending.reverse)
if(nDevices > 0) {
for (hart <- 0 until nHarts) {
val fanin = Module(new PLICFanIn(nDevices, prioBits))
fanin.io.prio := priority
fanin.io.ip := enableVec(hart) & pendingUInt
maxDevs(hart) := fanin.io.dev
harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages)
}
}
// Priority registers are 32-bit aligned so treat each as its own group.
// Otherwise, the off-by-one nature of the priority registers gets confusing.
require(PLICConsts.priorityBytes == 4,
s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}")
def priorityRegDesc(i: Int) =
RegFieldDesc(
name = s"priority_$i",
desc = s"Acting priority of interrupt source $i",
group = Some(s"priority_${i}"),
groupDesc = Some(s"Acting priority of interrupt source ${i}"),
reset = if (nPriorities > 0) None else Some(1))
def pendingRegDesc(i: Int) =
RegFieldDesc(
name = s"pending_$i",
desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.",
group = Some("pending"),
groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."),
volatile = true)
def enableRegDesc(i: Int, j: Int, wide: Int) = {
val low = if (j == 0) 1 else j*8
val high = low + wide - 1
RegFieldDesc(
name = s"enables_${j}",
desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.",
group = Some(s"enables_${i}"),
groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source."))
}
def priorityRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, priorityRegDesc(i))
} else {
RegField.r(prioBits, x, priorityRegDesc(i))
}
val priorityRegFields = priority.zipWithIndex.map { case (p, i) =>
PLICConsts.priorityBase+PLICConsts.priorityBytes*(i+1) ->
Seq(priorityRegField(p, i+1)) }
val pendingRegFields = Seq(PLICConsts.pendingBase ->
(RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))}))
val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) =>
RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) }
// When a hart reads a claim/complete register, then the
// device which is currently its highest priority is no longer pending.
// This code exploits the fact that, practically, only one claim/complete
// register can be read at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note: PLIC doesn't care which hart reads the register.
val claimer = Wire(Vec(nHarts, Bool()))
assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot
val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_|_)
val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools)
((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) =>
g.ready := !p
when (c || g.valid) { p := !c }
}
// When a hart writes a claim/complete register, then
// the written device (as long as it is actually enabled for that
// hart) is marked complete.
// This code exploits the fact that, practically, only one claim/complete register
// can be written at a time. We check for this because if the address map
// were to change, it may no longer be true.
// Note -- PLIC doesn't care which hart writes the register.
val completer = Wire(Vec(nHarts, Bool()))
assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot
val completerDev = Wire(UInt(log2Up(nDevices + 1).W))
val completedDevs = Mux(completer.reduce(_ || _), UIntToOH(completerDev, nDevices+1), 0.U)
(gateways zip completedDevs.asBools.tail) foreach { case (g, c) =>
g.complete := c
}
def thresholdRegDesc(i: Int) =
RegFieldDesc(
name = s"threshold_$i",
desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.",
reset = if (nPriorities > 0) None else Some(1))
def thresholdRegField(x: UInt, i: Int) =
if (nPriorities > 0) {
RegField(prioBits, x, thresholdRegDesc(i))
} else {
RegField.r(prioBits, x, thresholdRegDesc(i))
}
val hartRegFields = Seq.tabulate(nHarts) { i =>
PLICConsts.hartBase(i) -> Seq(
thresholdRegField(threshold(i), i),
RegField(32-prioBits),
RegField(32,
RegReadFn { valid =>
claimer(i) := valid
(true.B, maxDevs(i))
},
RegWriteFn { (valid, data) =>
assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),
"completerDev should be consistent for all harts")
completerDev := data.extract(log2Ceil(nDevices+1)-1, 0)
completer(i) := valid && enableVec0(i)(completerDev)
true.B
},
Some(RegFieldDesc(s"claim_complete_$i",
s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." +
s"Writing the interrupt number back completes the interrupt.",
reset = None,
wrType = Some(RegFieldWrType.MODIFY),
rdAction = Some(RegFieldRdAction.MODIFY),
volatile = true))
)
)
}
node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_*)
if (nDevices >= 2) {
val claimed = claimer(0) && maxDevs(0) > 0.U
val completed = completer(0)
property.cover(claimed && RegEnable(claimed, false.B, claimed || completed), "TWO_CLAIMS", "two claims with no intervening complete")
property.cover(completed && RegEnable(completed, false.B, claimed || completed), "TWO_COMPLETES", "two completes with no intervening claim")
val ep = enables(0).asUInt & pending.asUInt
val ep2 = RegNext(ep)
val diff = ep & ~ep2
property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle")
if (nPriorities > 0)
ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)),
"THRESHOLD", "interrupt pending but less than threshold")
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc)
}
}
class PLICFanIn(nDevices: Int, prioBits: Int) extends Module {
val io = IO(new Bundle {
val prio = Flipped(Vec(nDevices, UInt(prioBits.W)))
val ip = Flipped(UInt(nDevices.W))
val dev = UInt(log2Ceil(nDevices+1).W)
val max = UInt(prioBits.W)
})
def findMax(x: Seq[UInt]): (UInt, UInt) = {
if (x.length > 1) {
val half = 1 << (log2Ceil(x.length) - 1)
val left = findMax(x take half)
val right = findMax(x drop half)
MuxT(left._1 >= right._1, left, (right._1, half.U | right._2))
} else (x.head, 0.U)
}
val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) }
val (maxPri, maxDev) = findMax(effectivePriority)
io.max := maxPri // strips the always-constant high '1' bit
io.dev := maxDev
}
/** Trait that will connect a PLIC to a subsystem */
trait CanHavePeripheryPLIC { this: BaseSubsystem =>
val (plicOpt, plicDomainOpt) = p(PLICKey).map { params =>
val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere)
val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain")
val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) }
plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } }
plicDomainWrapper { plic.intnode :=* ibus.toPLIC }
(plic, plicDomainWrapper)
}.unzip
}
| module PLICFanIn_4( // @[Plic.scala:338:7]
input clock, // @[Plic.scala:338:7]
input reset, // @[Plic.scala:338:7]
input io_prio_0, // @[Plic.scala:339:14]
input io_ip, // @[Plic.scala:339:14]
output io_dev, // @[Plic.scala:339:14]
output io_max // @[Plic.scala:339:14]
);
wire io_prio_0_0 = io_prio_0; // @[Plic.scala:338:7]
wire io_ip_0 = io_ip; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_0 = 2'h2; // @[Plic.scala:355:32]
wire _effectivePriority_T = io_ip_0; // @[Plic.scala:338:7, :355:55]
wire maxDev; // @[Misc.scala:35:36]
wire io_dev_0; // @[Plic.scala:338:7]
wire io_max_0; // @[Plic.scala:338:7]
wire [1:0] effectivePriority_1 = {_effectivePriority_T, io_prio_0_0}; // @[Plic.scala:338:7, :355:{55,100}]
wire [1:0] maxPri = effectivePriority_1 != 2'h3 ? 2'h2 : effectivePriority_1; // @[Misc.scala:35:9]
assign maxDev = &effectivePriority_1; // @[Misc.scala:35:36]
assign io_dev_0 = maxDev; // @[Misc.scala:35:36]
assign io_max_0 = maxPri[0]; // @[Misc.scala:35:9]
assign io_dev = io_dev_0; // @[Plic.scala:338:7]
assign io_max = io_max_0; // @[Plic.scala:338:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_508( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File consts.scala:
//******************************************************************************
// Copyright (c) 2011 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common.constants
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util.Str
import freechips.rocketchip.rocket.RVCExpander
/**
* Mixin for issue queue types
*/
trait IQType
{
val IQT_SZ = 3
val IQT_INT = 1.U(IQT_SZ.W)
val IQT_MEM = 2.U(IQT_SZ.W)
val IQT_FP = 4.U(IQT_SZ.W)
val IQT_MFP = 6.U(IQT_SZ.W)
}
/**
* Mixin for scalar operation constants
*/
trait ScalarOpConstants
{
val X = BitPat("b?")
val Y = BitPat("b1")
val N = BitPat("b0")
//************************************
// Extra Constants
// Which branch predictor predicted us
val BSRC_SZ = 2
val BSRC_1 = 0.U(BSRC_SZ.W) // 1-cycle branch pred
val BSRC_2 = 1.U(BSRC_SZ.W) // 2-cycle branch pred
val BSRC_3 = 2.U(BSRC_SZ.W) // 3-cycle branch pred
val BSRC_C = 3.U(BSRC_SZ.W) // core branch resolution
//************************************
// Control Signals
// CFI types
val CFI_SZ = 3
val CFI_X = 0.U(CFI_SZ.W) // Not a CFI instruction
val CFI_BR = 1.U(CFI_SZ.W) // Branch
val CFI_JAL = 2.U(CFI_SZ.W) // JAL
val CFI_JALR = 3.U(CFI_SZ.W) // JALR
// PC Select Signal
val PC_PLUS4 = 0.U(2.W) // PC + 4
val PC_BRJMP = 1.U(2.W) // brjmp_target
val PC_JALR = 2.U(2.W) // jump_reg_target
// Branch Type
val BR_N = 0.U(4.W) // Next
val BR_NE = 1.U(4.W) // Branch on NotEqual
val BR_EQ = 2.U(4.W) // Branch on Equal
val BR_GE = 3.U(4.W) // Branch on Greater/Equal
val BR_GEU = 4.U(4.W) // Branch on Greater/Equal Unsigned
val BR_LT = 5.U(4.W) // Branch on Less Than
val BR_LTU = 6.U(4.W) // Branch on Less Than Unsigned
val BR_J = 7.U(4.W) // Jump
val BR_JR = 8.U(4.W) // Jump Register
// RS1 Operand Select Signal
val OP1_RS1 = 0.U(2.W) // Register Source #1
val OP1_ZERO= 1.U(2.W)
val OP1_PC = 2.U(2.W)
val OP1_X = BitPat("b??")
// RS2 Operand Select Signal
val OP2_RS2 = 0.U(3.W) // Register Source #2
val OP2_IMM = 1.U(3.W) // immediate
val OP2_ZERO= 2.U(3.W) // constant 0
val OP2_NEXT= 3.U(3.W) // constant 2/4 (for PC+2/4)
val OP2_IMMC= 4.U(3.W) // for CSR imm found in RS1
val OP2_X = BitPat("b???")
// Register File Write Enable Signal
val REN_0 = false.B
val REN_1 = true.B
// Is 32b Word or 64b Doubldword?
val SZ_DW = 1
val DW_X = true.B // Bool(xLen==64)
val DW_32 = false.B
val DW_64 = true.B
val DW_XPR = true.B // Bool(xLen==64)
// Memory Enable Signal
val MEN_0 = false.B
val MEN_1 = true.B
val MEN_X = false.B
// Immediate Extend Select
val IS_I = 0.U(3.W) // I-Type (LD,ALU)
val IS_S = 1.U(3.W) // S-Type (ST)
val IS_B = 2.U(3.W) // SB-Type (BR)
val IS_U = 3.U(3.W) // U-Type (LUI/AUIPC)
val IS_J = 4.U(3.W) // UJ-Type (J/JAL)
val IS_X = BitPat("b???")
// Decode Stage Control Signals
val RT_FIX = 0.U(2.W)
val RT_FLT = 1.U(2.W)
val RT_PAS = 3.U(2.W) // pass-through (prs1 := lrs1, etc)
val RT_X = 2.U(2.W) // not-a-register (but shouldn't get a busy-bit, etc.)
// TODO rename RT_NAR
// Micro-op opcodes
// TODO change micro-op opcodes into using enum
val UOPC_SZ = 7
val uopX = BitPat.dontCare(UOPC_SZ)
val uopNOP = 0.U(UOPC_SZ.W)
val uopLD = 1.U(UOPC_SZ.W)
val uopSTA = 2.U(UOPC_SZ.W) // store address generation
val uopSTD = 3.U(UOPC_SZ.W) // store data generation
val uopLUI = 4.U(UOPC_SZ.W)
val uopADDI = 5.U(UOPC_SZ.W)
val uopANDI = 6.U(UOPC_SZ.W)
val uopORI = 7.U(UOPC_SZ.W)
val uopXORI = 8.U(UOPC_SZ.W)
val uopSLTI = 9.U(UOPC_SZ.W)
val uopSLTIU= 10.U(UOPC_SZ.W)
val uopSLLI = 11.U(UOPC_SZ.W)
val uopSRAI = 12.U(UOPC_SZ.W)
val uopSRLI = 13.U(UOPC_SZ.W)
val uopSLL = 14.U(UOPC_SZ.W)
val uopADD = 15.U(UOPC_SZ.W)
val uopSUB = 16.U(UOPC_SZ.W)
val uopSLT = 17.U(UOPC_SZ.W)
val uopSLTU = 18.U(UOPC_SZ.W)
val uopAND = 19.U(UOPC_SZ.W)
val uopOR = 20.U(UOPC_SZ.W)
val uopXOR = 21.U(UOPC_SZ.W)
val uopSRA = 22.U(UOPC_SZ.W)
val uopSRL = 23.U(UOPC_SZ.W)
val uopBEQ = 24.U(UOPC_SZ.W)
val uopBNE = 25.U(UOPC_SZ.W)
val uopBGE = 26.U(UOPC_SZ.W)
val uopBGEU = 27.U(UOPC_SZ.W)
val uopBLT = 28.U(UOPC_SZ.W)
val uopBLTU = 29.U(UOPC_SZ.W)
val uopCSRRW= 30.U(UOPC_SZ.W)
val uopCSRRS= 31.U(UOPC_SZ.W)
val uopCSRRC= 32.U(UOPC_SZ.W)
val uopCSRRWI=33.U(UOPC_SZ.W)
val uopCSRRSI=34.U(UOPC_SZ.W)
val uopCSRRCI=35.U(UOPC_SZ.W)
val uopJ = 36.U(UOPC_SZ.W)
val uopJAL = 37.U(UOPC_SZ.W)
val uopJALR = 38.U(UOPC_SZ.W)
val uopAUIPC= 39.U(UOPC_SZ.W)
//val uopSRET = 40.U(UOPC_SZ.W)
val uopCFLSH= 41.U(UOPC_SZ.W)
val uopFENCE= 42.U(UOPC_SZ.W)
val uopADDIW= 43.U(UOPC_SZ.W)
val uopADDW = 44.U(UOPC_SZ.W)
val uopSUBW = 45.U(UOPC_SZ.W)
val uopSLLIW= 46.U(UOPC_SZ.W)
val uopSLLW = 47.U(UOPC_SZ.W)
val uopSRAIW= 48.U(UOPC_SZ.W)
val uopSRAW = 49.U(UOPC_SZ.W)
val uopSRLIW= 50.U(UOPC_SZ.W)
val uopSRLW = 51.U(UOPC_SZ.W)
val uopMUL = 52.U(UOPC_SZ.W)
val uopMULH = 53.U(UOPC_SZ.W)
val uopMULHU= 54.U(UOPC_SZ.W)
val uopMULHSU=55.U(UOPC_SZ.W)
val uopMULW = 56.U(UOPC_SZ.W)
val uopDIV = 57.U(UOPC_SZ.W)
val uopDIVU = 58.U(UOPC_SZ.W)
val uopREM = 59.U(UOPC_SZ.W)
val uopREMU = 60.U(UOPC_SZ.W)
val uopDIVW = 61.U(UOPC_SZ.W)
val uopDIVUW= 62.U(UOPC_SZ.W)
val uopREMW = 63.U(UOPC_SZ.W)
val uopREMUW= 64.U(UOPC_SZ.W)
val uopFENCEI = 65.U(UOPC_SZ.W)
// = 66.U(UOPC_SZ.W)
val uopAMO_AG = 67.U(UOPC_SZ.W) // AMO-address gen (use normal STD for datagen)
val uopFMV_W_X = 68.U(UOPC_SZ.W)
val uopFMV_D_X = 69.U(UOPC_SZ.W)
val uopFMV_X_W = 70.U(UOPC_SZ.W)
val uopFMV_X_D = 71.U(UOPC_SZ.W)
val uopFSGNJ_S = 72.U(UOPC_SZ.W)
val uopFSGNJ_D = 73.U(UOPC_SZ.W)
val uopFCVT_S_D = 74.U(UOPC_SZ.W)
val uopFCVT_D_S = 75.U(UOPC_SZ.W)
val uopFCVT_S_X = 76.U(UOPC_SZ.W)
val uopFCVT_D_X = 77.U(UOPC_SZ.W)
val uopFCVT_X_S = 78.U(UOPC_SZ.W)
val uopFCVT_X_D = 79.U(UOPC_SZ.W)
val uopCMPR_S = 80.U(UOPC_SZ.W)
val uopCMPR_D = 81.U(UOPC_SZ.W)
val uopFCLASS_S = 82.U(UOPC_SZ.W)
val uopFCLASS_D = 83.U(UOPC_SZ.W)
val uopFMINMAX_S = 84.U(UOPC_SZ.W)
val uopFMINMAX_D = 85.U(UOPC_SZ.W)
// = 86.U(UOPC_SZ.W)
val uopFADD_S = 87.U(UOPC_SZ.W)
val uopFSUB_S = 88.U(UOPC_SZ.W)
val uopFMUL_S = 89.U(UOPC_SZ.W)
val uopFADD_D = 90.U(UOPC_SZ.W)
val uopFSUB_D = 91.U(UOPC_SZ.W)
val uopFMUL_D = 92.U(UOPC_SZ.W)
val uopFMADD_S = 93.U(UOPC_SZ.W)
val uopFMSUB_S = 94.U(UOPC_SZ.W)
val uopFNMADD_S = 95.U(UOPC_SZ.W)
val uopFNMSUB_S = 96.U(UOPC_SZ.W)
val uopFMADD_D = 97.U(UOPC_SZ.W)
val uopFMSUB_D = 98.U(UOPC_SZ.W)
val uopFNMADD_D = 99.U(UOPC_SZ.W)
val uopFNMSUB_D = 100.U(UOPC_SZ.W)
val uopFDIV_S = 101.U(UOPC_SZ.W)
val uopFDIV_D = 102.U(UOPC_SZ.W)
val uopFSQRT_S = 103.U(UOPC_SZ.W)
val uopFSQRT_D = 104.U(UOPC_SZ.W)
val uopWFI = 105.U(UOPC_SZ.W) // pass uop down the CSR pipeline
val uopERET = 106.U(UOPC_SZ.W) // pass uop down the CSR pipeline, also is ERET
val uopSFENCE = 107.U(UOPC_SZ.W)
val uopROCC = 108.U(UOPC_SZ.W)
val uopMOV = 109.U(UOPC_SZ.W) // conditional mov decoded from "add rd, x0, rs2"
// The Bubble Instruction (Machine generated NOP)
// Insert (XOR x0,x0,x0) which is different from software compiler
// generated NOPs which are (ADDI x0, x0, 0).
// Reasoning for this is to let visualizers and stat-trackers differentiate
// between software NOPs and machine-generated Bubbles in the pipeline.
val BUBBLE = (0x4033).U(32.W)
def NullMicroOp()(implicit p: Parameters): boom.v3.common.MicroOp = {
val uop = Wire(new boom.v3.common.MicroOp)
uop := DontCare // Overridden in the following lines
uop.uopc := uopNOP // maybe not required, but helps on asserts that try to catch spurious behavior
uop.bypassable := false.B
uop.fp_val := false.B
uop.uses_stq := false.B
uop.uses_ldq := false.B
uop.pdst := 0.U
uop.dst_rtype := RT_X
val cs = Wire(new boom.v3.common.CtrlSignals())
cs := DontCare // Overridden in the following lines
cs.br_type := BR_N
cs.csr_cmd := freechips.rocketchip.rocket.CSR.N
cs.is_load := false.B
cs.is_sta := false.B
cs.is_std := false.B
uop.ctrl := cs
uop
}
}
/**
* Mixin for RISCV constants
*/
trait RISCVConstants
{
// abstract out instruction decode magic numbers
val RD_MSB = 11
val RD_LSB = 7
val RS1_MSB = 19
val RS1_LSB = 15
val RS2_MSB = 24
val RS2_LSB = 20
val RS3_MSB = 31
val RS3_LSB = 27
val CSR_ADDR_MSB = 31
val CSR_ADDR_LSB = 20
val CSR_ADDR_SZ = 12
// location of the fifth bit in the shamt (for checking for illegal ops for SRAIW,etc.)
val SHAMT_5_BIT = 25
val LONGEST_IMM_SZ = 20
val X0 = 0.U
val RA = 1.U // return address register
// memory consistency model
// The C/C++ atomics MCM requires that two loads to the same address maintain program order.
// The Cortex A9 does NOT enforce load/load ordering (which leads to buggy behavior).
val MCM_ORDER_DEPENDENT_LOADS = true
val jal_opc = (0x6f).U
val jalr_opc = (0x67).U
def GetUop(inst: UInt): UInt = inst(6,0)
def GetRd (inst: UInt): UInt = inst(RD_MSB,RD_LSB)
def GetRs1(inst: UInt): UInt = inst(RS1_MSB,RS1_LSB)
def ExpandRVC(inst: UInt)(implicit p: Parameters): UInt = {
val rvc_exp = Module(new RVCExpander)
rvc_exp.io.in := inst
Mux(rvc_exp.io.rvc, rvc_exp.io.out.bits, inst)
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeBranchTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val b_imm32 = Cat(Fill(20,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
((pc.asSInt + b_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def ComputeJALTarget(pc: UInt, inst: UInt, xlen: Int)(implicit p: Parameters): UInt = {
val j_imm32 = Cat(Fill(12,inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
((pc.asSInt + j_imm32.asSInt).asSInt & (-2).S).asUInt
}
// Note: Accepts only EXPANDED rvc instructions
def GetCfiType(inst: UInt)(implicit p: Parameters): UInt = {
val bdecode = Module(new boom.v3.exu.BranchDecode)
bdecode.io.inst := inst
bdecode.io.pc := 0.U
bdecode.io.out.cfi_type
}
}
/**
* Mixin for exception cause constants
*/
trait ExcCauseConstants
{
// a memory disambigious misspeculation occurred
val MINI_EXCEPTION_MEM_ORDERING = 16.U
val MINI_EXCEPTION_CSR_REPLAY = 17.U
require (!freechips.rocketchip.rocket.Causes.all.contains(16))
require (!freechips.rocketchip.rocket.Causes.all.contains(17))
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v3.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.common._
import boom.v3.util._
import FUConstants._
/**
* IO bundle to interact with Issue slot
*
* @param numWakeupPorts number of wakeup ports for the slot
*/
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val request_hp = Output(Bool())
val grant = Input(Bool())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val ldspec_miss = Input(Bool()) // Previous cycle's speculative load wakeup was mispredicted.
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new IqWakeup(maxPregSz))))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val spec_ld_wakeup = Flipped(Vec(memWidth, Valid(UInt(width=maxPregSz.W))))
val in_uop = Flipped(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp()) // the updated slot uop; will be shifted upwards in a collasping queue.
val uop = Output(new MicroOp()) // the current Slot's uop. Sent down the pipeline when issued.
val debug = {
val result = new Bundle {
val p1 = Bool()
val p2 = Bool()
val p3 = Bool()
val ppred = Bool()
val state = UInt(width=2.W)
}
Output(result)
}
}
/**
* Single issue slot. Holds a uop within the issue queue
*
* @param numWakeupPorts number of wakeup ports
*/
class IssueSlot(val numWakeupPorts: Int)(implicit p: Parameters)
extends BoomModule
with IssueUnitConstants
{
val io = IO(new IssueSlotIO(numWakeupPorts))
// slot invalid?
// slot is valid, holding 1 uop
// slot is valid, holds 2 uops (like a store)
def is_invalid = state === s_invalid
def is_valid = state =/= s_invalid
val next_state = Wire(UInt()) // the next state of this slot (which might then get moved to a new slot)
val next_uopc = Wire(UInt()) // the next uopc of this slot (which might then get moved to a new slot)
val next_lrs1_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val next_lrs2_rtype = Wire(UInt()) // the next reg type of this slot (which might then get moved to a new slot)
val state = RegInit(s_invalid)
val p1 = RegInit(false.B)
val p2 = RegInit(false.B)
val p3 = RegInit(false.B)
val ppred = RegInit(false.B)
// Poison if woken up by speculative load.
// Poison lasts 1 cycle (as ldMiss will come on the next cycle).
// SO if poisoned is true, set it to false!
val p1_poisoned = RegInit(false.B)
val p2_poisoned = RegInit(false.B)
p1_poisoned := false.B
p2_poisoned := false.B
val next_p1_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
val next_p2_poisoned = Mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
val slot_uop = RegInit(NullMicroOp)
val next_uop = Mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
//-----------------------------------------------------------------------------
// next slot state computation
// compute the next state for THIS entry slot (in a collasping queue, the
// current uop may get moved elsewhere, and a new uop can enter
when (io.kill) {
state := s_invalid
} .elsewhen (io.in_uop.valid) {
state := io.in_uop.bits.iw_state
} .elsewhen (io.clear) {
state := s_invalid
} .otherwise {
state := next_state
}
//-----------------------------------------------------------------------------
// "update" state
// compute the next state for the micro-op in this slot. This micro-op may
// be moved elsewhere, so the "next_state" travels with it.
// defaults
next_state := state
next_uopc := slot_uop.uopc
next_lrs1_rtype := slot_uop.lrs1_rtype
next_lrs2_rtype := slot_uop.lrs2_rtype
when (io.kill) {
next_state := s_invalid
} .elsewhen ((io.grant && (state === s_valid_1)) ||
(io.grant && (state === s_valid_2) && p1 && p2 && ppred)) {
// try to issue this uop.
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_invalid
}
} .elsewhen (io.grant && (state === s_valid_2)) {
when (!(io.ldspec_miss && (p1_poisoned || p2_poisoned))) {
next_state := s_valid_1
when (p1) {
slot_uop.uopc := uopSTD
next_uopc := uopSTD
slot_uop.lrs1_rtype := RT_X
next_lrs1_rtype := RT_X
} .otherwise {
slot_uop.lrs2_rtype := RT_X
next_lrs2_rtype := RT_X
}
}
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (is_invalid || io.clear || io.kill, "trying to overwrite a valid issue slot.")
}
// Wakeup Compare Logic
// these signals are the "next_p*" for the current slot's micro-op.
// they are important for shifting the current slot_uop up to an other entry.
val next_p1 = WireInit(p1)
val next_p2 = WireInit(p2)
val next_p3 = WireInit(p3)
val next_ppred = WireInit(ppred)
when (io.in_uop.valid) {
p1 := !(io.in_uop.bits.prs1_busy)
p2 := !(io.in_uop.bits.prs2_busy)
p3 := !(io.in_uop.bits.prs3_busy)
ppred := !(io.in_uop.bits.ppred_busy)
}
when (io.ldspec_miss && next_p1_poisoned) {
assert(next_uop.prs1 =/= 0.U, "Poison bit can't be set for prs1=x0!")
p1 := false.B
}
when (io.ldspec_miss && next_p2_poisoned) {
assert(next_uop.prs2 =/= 0.U, "Poison bit can't be set for prs2=x0!")
p2 := false.B
}
for (i <- 0 until numWakeupPorts) {
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs1)) {
p1 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs2)) {
p2 := true.B
}
when (io.wakeup_ports(i).valid &&
(io.wakeup_ports(i).bits.pdst === next_uop.prs3)) {
p3 := true.B
}
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === next_uop.ppred) {
ppred := true.B
}
for (w <- 0 until memWidth) {
assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),
"Loads to x0 should never speculatively wakeup other instructions")
}
// TODO disable if FP IQ.
for (w <- 0 until memWidth) {
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs1 &&
next_uop.lrs1_rtype === RT_FIX) {
p1 := true.B
p1_poisoned := true.B
assert (!next_p1_poisoned)
}
when (io.spec_ld_wakeup(w).valid &&
io.spec_ld_wakeup(w).bits === next_uop.prs2 &&
next_uop.lrs2_rtype === RT_FIX) {
p2 := true.B
p2_poisoned := true.B
assert (!next_p2_poisoned)
}
}
// Handle branch misspeculations
val next_br_mask = GetNewBrMask(io.brupdate, slot_uop)
// was this micro-op killed by a branch? if yes, we can't let it be valid if
// we compact it into an other entry
when (IsKilledByBranch(io.brupdate, slot_uop)) {
next_state := s_invalid
}
when (!io.in_uop.valid) {
slot_uop.br_mask := next_br_mask
}
//-------------------------------------------------------------
// Request Logic
io.request := is_valid && p1 && p2 && p3 && ppred && !io.kill
val high_priority = slot_uop.is_br || slot_uop.is_jal || slot_uop.is_jalr
io.request_hp := io.request && high_priority
when (state === s_valid_1) {
io.request := p1 && p2 && p3 && ppred && !io.kill
} .elsewhen (state === s_valid_2) {
io.request := (p1 || p2) && ppred && !io.kill
} .otherwise {
io.request := false.B
}
//assign outputs
io.valid := is_valid
io.uop := slot_uop
io.uop.iw_p1_poisoned := p1_poisoned
io.uop.iw_p2_poisoned := p2_poisoned
// micro-op will vacate due to grant.
val may_vacate = io.grant && ((state === s_valid_1) || (state === s_valid_2) && p1 && p2 && ppred)
val squash_grant = io.ldspec_miss && (p1_poisoned || p2_poisoned)
io.will_be_valid := is_valid && !(may_vacate && !squash_grant)
io.out_uop := slot_uop
io.out_uop.iw_state := next_state
io.out_uop.uopc := next_uopc
io.out_uop.lrs1_rtype := next_lrs1_rtype
io.out_uop.lrs2_rtype := next_lrs2_rtype
io.out_uop.br_mask := next_br_mask
io.out_uop.prs1_busy := !p1
io.out_uop.prs2_busy := !p2
io.out_uop.prs3_busy := !p3
io.out_uop.ppred_busy := !ppred
io.out_uop.iw_p1_poisoned := p1_poisoned
io.out_uop.iw_p2_poisoned := p2_poisoned
when (state === s_valid_2) {
when (p1 && p2 && ppred) {
; // send out the entire instruction as one uop
} .elsewhen (p1 && ppred) {
io.uop.uopc := slot_uop.uopc
io.uop.lrs2_rtype := RT_X
} .elsewhen (p2 && ppred) {
io.uop.uopc := uopSTD
io.uop.lrs1_rtype := RT_X
}
}
// debug outputs
io.debug.p1 := p1
io.debug.p2 := p2
io.debug.p3 := p3
io.debug.ppred := ppred
io.debug.state := state
}
| module IssueSlot_119( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_66( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [8:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [10:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [8:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [3:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [10:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [8:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [3:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [10:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [3:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [8:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [10:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [8:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [10:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [8:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [8:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [8:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [10:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [8:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [3:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [10:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [8:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [10:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [8:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [8:0] invalid_tag = 9'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [8:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [10:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [8:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [8:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [10:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [8:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [3:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [8:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [10:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [8:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [10:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [8:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [3:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [3:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [8:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 6'h28; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 9'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [8:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [3:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [8:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [10:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 6'h28; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File Decode.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.BitPat
import chisel3.util.experimental.decode._
object DecodeLogic
{
// TODO This should be a method on BitPat
private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width
// Pads BitPats that are safe to pad (no don't cares), errors otherwise
private def padBP(bp: BitPat, width: Int): BitPat = {
if (bp.width == width) bp
else {
require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares")
val diff = width - bp.width
require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!")
BitPat(0.U(diff.W)) ## bp
}
}
def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt =
chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default))
def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = {
val nElts = default.size
require(mappingIn.forall(_._2.size == nElts),
s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}"
)
val elementsGrouped = mappingIn.map(_._2).transpose
val elementWidths = elementsGrouped.zip(default).map { case (elts, default) =>
(default :: elts.toList).map(_.getWidth).max
}
val resultWidth = elementWidths.sum
val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r }
// All BitPats that correspond to a given element in the result must have the same width in the
// chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have
// any don't cares. If there are don't cares, it is an error and the user needs to pad the
// BitPat themselves
val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
val mappingInPadded = mappingIn.map { case (in, elts) =>
in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) }
}
val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) })
elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList
}
def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] =
apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]])
def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool =
apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File CustomCSRs.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import org.chipsalliance.cde.config.Parameters
case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt])
object CustomCSR {
def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value))
}
class CustomCSRIO(implicit p: Parameters) extends CoreBundle {
val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR
val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR
val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR
val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile
val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded)
val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR
val sdata = Input(UInt(xLen.W))
}
class CustomCSRs(implicit p: Parameters) extends CoreBundle {
// Not all cores have these CSRs, but those that do should follow the same
// numbering conventions. So we list them here but default them to None.
protected def bpmCSRId = 0x7c0
protected def bpmCSR: Option[CustomCSR] = None
protected def chickenCSRId = 0x7c1
protected def chickenCSR: Option[CustomCSR] = None
// If you override this, you'll want to concatenate super.decls
def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR
val csrs = Vec(decls.size, new CustomCSRIO)
def flushBTB = getOrElse(bpmCSR, _.wen, false.B)
def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B)
def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B)
def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B)
def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B)
def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B)
def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B)
protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = {
val idx = decls.indexWhere(_.id == id)
if (idx < 0) alt else f(csrs(idx))
}
protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T =
csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt)
}
File Consts.scala:
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket.constants
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
trait ScalarOpConstants {
val SZ_BR = 3
def BR_X = BitPat("b???")
def BR_EQ = 0.U(3.W)
def BR_NE = 1.U(3.W)
def BR_J = 2.U(3.W)
def BR_N = 3.U(3.W)
def BR_LT = 4.U(3.W)
def BR_GE = 5.U(3.W)
def BR_LTU = 6.U(3.W)
def BR_GEU = 7.U(3.W)
def A1_X = BitPat("b??")
def A1_ZERO = 0.U(2.W)
def A1_RS1 = 1.U(2.W)
def A1_PC = 2.U(2.W)
def A1_RS1SHL = 3.U(2.W)
def IMM_X = BitPat("b???")
def IMM_S = 0.U(3.W)
def IMM_SB = 1.U(3.W)
def IMM_U = 2.U(3.W)
def IMM_UJ = 3.U(3.W)
def IMM_I = 4.U(3.W)
def IMM_Z = 5.U(3.W)
def A2_X = BitPat("b???")
def A2_ZERO = 0.U(3.W)
def A2_SIZE = 1.U(3.W)
def A2_RS2 = 2.U(3.W)
def A2_IMM = 3.U(3.W)
def A2_RS2OH = 4.U(3.W)
def A2_IMMOH = 5.U(3.W)
def X = BitPat("b?")
def N = BitPat("b0")
def Y = BitPat("b1")
val SZ_DW = 1
def DW_X = X
def DW_32 = false.B
def DW_64 = true.B
def DW_XPR = DW_64
}
trait MemoryOpConstants {
val NUM_XA_OPS = 9
val M_SZ = 5
def M_X = BitPat("b?????");
def M_XRD = "b00000".U; // int load
def M_XWR = "b00001".U; // int store
def M_PFR = "b00010".U; // prefetch with intent to read
def M_PFW = "b00011".U; // prefetch with intent to write
def M_XA_SWAP = "b00100".U
def M_FLUSH_ALL = "b00101".U // flush all lines
def M_XLR = "b00110".U
def M_XSC = "b00111".U
def M_XA_ADD = "b01000".U
def M_XA_XOR = "b01001".U
def M_XA_OR = "b01010".U
def M_XA_AND = "b01011".U
def M_XA_MIN = "b01100".U
def M_XA_MAX = "b01101".U
def M_XA_MINU = "b01110".U
def M_XA_MAXU = "b01111".U
def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions
def M_PWR = "b10001".U // partial (masked) store
def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions
def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions
def M_SFENCE = "b10100".U // SFENCE.VMA
def M_HFENCEV = "b10101".U // HFENCE.VVMA
def M_HFENCEG = "b10110".U // HFENCE.GVMA
def M_WOK = "b10111".U // check write permissions but don't perform a write
def M_HLVX = "b10000".U // HLVX instruction
def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND)
def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU)
def isAMO(cmd: UInt) = isAMOLogical(cmd) || isAMOArithmetic(cmd)
def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) || isAMO(cmd)
def isWrite(cmd: UInt) = cmd === M_XWR || cmd === M_PWR || cmd === M_XSC || isAMO(cmd)
def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
}
File Events.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.log2Ceil
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) {
def size = events.size
val hits = WireDefault(VecInit(Seq.fill(size)(false.B)))
def check(mask: UInt) = {
hits := events.map(_._2())
gate(mask, hits.asUInt)
}
def dump(): Unit = {
for (((name, _), i) <- events.zipWithIndex)
when (check(1.U << i)) { printf(s"Event $name\n") }
}
def withCovers: Unit = {
events.zipWithIndex.foreach {
case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name)
}
}
}
class EventSets(val eventSets: Seq[EventSet]) {
def maskEventSelector(eventSel: UInt): UInt = {
// allow full associativity between counters and event sets (for now?)
val setMask = (BigInt(1) << eventSetIdBits) - 1
val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits
eventSel & (setMask | maskMask).U
}
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
def evaluate(eventSel: UInt): Bool = {
val (set, mask) = decode(eventSel)
val sets = for (e <- eventSets) yield {
require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}")
e check mask
}
sets(set)
}
def cover() = eventSets.foreach { _.withCovers }
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSetIdBits <= maxEventSetIdBits)
}
class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) {
def evaluate(eventSel: UInt): UInt = {
val (set, mask) = decode(eventSel)
val sets = for ((sets, reducer) <- eventSets) yield {
sets.map { set =>
require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}")
set.check(mask)
}.reduce(reducer)
}
val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U)
zeroPadded(set)
}
def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head))
def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) }
private def decode(counter: UInt): (UInt, UInt) = {
require(eventSets.size <= (1 << maxEventSetIdBits))
require(eventSetIdBits > 0)
(counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits)
}
private def eventSetIdBits = log2Ceil(eventSets.size)
private def maxEventSetIdBits = 8
require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size)))
require(eventSetIdBits <= maxEventSetIdBits)
}
File RocketCore.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.withClock
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ArrayBuffer
case class RocketCoreParams(
xLen: Int = 64,
pgLevels: Int = 3, // sv39 default
bootFreqHz: BigInt = 0,
useVM: Boolean = true,
useUser: Boolean = false,
useSupervisor: Boolean = false,
useHypervisor: Boolean = false,
useDebug: Boolean = true,
useAtomics: Boolean = true,
useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true,
useRVE: Boolean = false,
useConditionalZero: Boolean = false,
useZba: Boolean = false,
useZbb: Boolean = false,
useZbs: Boolean = false,
nLocalInterrupts: Int = 0,
useNMI: Boolean = false,
nBreakpoints: Int = 1,
useBPWatch: Boolean = false,
mcontextWidth: Int = 0,
scontextWidth: Int = 0,
nPMPs: Int = 8,
nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true,
haveCFlush: Boolean = false,
misaWritable: Boolean = true,
nL2TLBEntries: Int = 0,
nL2TLBWays: Int = 1,
nPTECacheEntries: Int = 8,
mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
branchPredictionModeCSR: Boolean = false,
clockGate: Boolean = false,
mvendorid: Int = 0, // 0 means non-commercial implementation
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
vector: Option[RocketCoreVectorParams] = None
) extends CoreParams {
val lgPauseCycles = 5
val haveFSDirty = false
val pmpGranularity: Int = if (useHypervisor) 4096 else 4
val fetchWidth: Int = if (useCompressed) 2 else 1
// fetchWidth doubled, but coreInstBytes halved, for RVC:
val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1)
val retireWidth: Int = 1
val instBits: Int = if (useCompressed) 16 else 32
val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace
override val useVector = vector.isDefined
override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)
override def vLen = vector.map(_.vLen).getOrElse(0)
override def eLen = vector.map(_.eLen).getOrElse(0)
override def vfLen = vector.map(_.vfLen).getOrElse(0)
override def vfh = vector.map(_.vfh).getOrElse(false)
override def vExts = vector.map(_.vExts).getOrElse(Nil)
override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs
}
trait HasRocketCoreParameters extends HasCoreParameters {
lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams]
val fastLoadWord = rocketParams.fastLoadWord
val fastLoadByte = rocketParams.fastLoadByte
val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this
require(!fastLoadByte || fastLoadWord)
require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty")
}
class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters {
override def bpmCSR = {
rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0))))
}
private def haveDCache = tileParams.dcache.get.scratch.isEmpty
override def chickenCSR = {
val mask = BigInt(
tileParams.dcache.get.clockGate.toInt << 0 |
rocketParams.clockGate.toInt << 1 |
rocketParams.clockGate.toInt << 2 |
1 << 3 | // disableSpeculativeICacheRefill
haveDCache.toInt << 9 | // suppressCorruptOnGrantData
tileParams.icache.get.prefetch.toInt << 17
)
Some(CustomCSR(chickenCSRId, mask, Some(mask)))
}
def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B)
def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1))
def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
// mimpid encodes a release version in the form of a BCD-encoded datestamp.
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
}
class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) {
val buserror = Option.when(hasBeu)(Bool())
}
trait HasRocketCoreIO extends HasRocketCoreParameters {
implicit val p: Parameters
def nTotalRoCCCSRs: Int
val io = IO(new CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined))
val imem = new FrontendIO
val dmem = new HellaCacheIO
val ptw = Flipped(new DatapathPTWIO())
val fpu = Flipped(new FPUCoreIO())
val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
val trace = Output(new TraceBundle)
val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None
})
}
class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
with HasRocketCoreParameters
with HasRocketCoreIO {
def nTotalRoCCCSRs = tile.roccCSRs.flatten.size
import ALU._
val clock_en_reg = RegInit(true.B)
val long_latency_stall = Reg(Bool())
val id_reg_pause = Reg(Bool())
val imem_might_request_reg = Reg(Bool())
val clock_en = WireDefault(true.B)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "rocket_clock_gate")
class RocketImpl { // entering gated-clock domain
// performance counters
def pipelineIDToWB[T <: Data](x: T): T =
RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid)
val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
("exception", () => false.B),
("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
("system", () => id_ctrl.csr =/= CSR.N),
("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
("branch", () => id_ctrl.branch),
("jal", () => id_ctrl.jal),
("jalr", () => id_ctrl.jalr))
++ (if (!usingMulDiv) Seq() else Seq(
("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV),
("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV)))
++ (if (!usingFPU) Seq() else Seq(
("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
("long-latency interlock", () => id_sboard_hazard),
("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
("I$ blocked", () => icache_blocked),
("D$ blocked", () => id_ctrl.mem && dcache_blocked),
("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
("flush", () => wb_reg_flush_pipe),
("replay", () => replay_wb))
++ (if (!usingMulDiv) Seq() else Seq(
("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
++ (if (!usingFPU) Seq() else Seq(
("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.imem.perf.acquire),
("D$ miss", () => io.dmem.perf.acquire),
("D$ release", () => io.dmem.perf.release),
("ITLB miss", () => io.imem.perf.tlbMiss),
("DTLB miss", () => io.dmem.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
val decode_table = {
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++:
(if (xLen == 32) new I32Decode else new I64Decode) +:
(usingVM.option(new SVMDecode)) ++:
(usingSupervisor.option(new SDecode)) ++:
(usingHypervisor.option(new HypervisorDecode)) ++:
((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++:
(usingDebug.option(new DebugDecode)) ++:
(usingNMI.option(new NMIDecode)) ++:
(usingConditionalZero.option(new ConditionalZeroDecode)) ++:
Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++:
coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++:
rocketParams.haveCease.option(new CeaseDecode) ++:
usingVector.option(new VCFGDecode) ++:
(if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++:
(if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++:
coreParams.useZbs.option(new ZbsDecode) ++:
Seq(new IDecode)
} flatMap(_.table)
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)
val wb_ctrl = Reg(new IntCtrlSigs)
val ex_reg_xcpt_interrupt = Reg(Bool())
val ex_reg_valid = Reg(Bool())
val ex_reg_rvc = Reg(Bool())
val ex_reg_btb_resp = Reg(new BTBResp)
val ex_reg_xcpt = Reg(Bool())
val ex_reg_flush_pipe = Reg(Bool())
val ex_reg_load_use = Reg(Bool())
val ex_reg_cause = Reg(UInt())
val ex_reg_replay = Reg(Bool())
val ex_reg_pc = Reg(UInt())
val ex_reg_mem_size = Reg(UInt())
val ex_reg_hls = Reg(Bool())
val ex_reg_inst = Reg(Bits())
val ex_reg_raw_inst = Reg(UInt())
val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val ex_reg_set_vconfig = Reg(Bool())
val mem_reg_xcpt_interrupt = Reg(Bool())
val mem_reg_valid = Reg(Bool())
val mem_reg_rvc = Reg(Bool())
val mem_reg_btb_resp = Reg(new BTBResp)
val mem_reg_xcpt = Reg(Bool())
val mem_reg_replay = Reg(Bool())
val mem_reg_flush_pipe = Reg(Bool())
val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool())
val mem_reg_load = Reg(Bool())
val mem_reg_store = Reg(Bool())
val mem_reg_set_vconfig = Reg(Bool())
val mem_reg_sfence = Reg(Bool())
val mem_reg_pc = Reg(UInt())
val mem_reg_inst = Reg(Bits())
val mem_reg_mem_size = Reg(UInt())
val mem_reg_hls_or_dv = Reg(Bool())
val mem_reg_raw_inst = Reg(UInt())
val mem_reg_wdata = Reg(Bits())
val mem_reg_rs2 = Reg(Bits())
val mem_br_taken = Reg(Bool())
val take_pc_mem = Wire(Bool())
val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val wb_reg_valid = Reg(Bool())
val wb_reg_xcpt = Reg(Bool())
val wb_reg_replay = Reg(Bool())
val wb_reg_flush_pipe = Reg(Bool())
val wb_reg_cause = Reg(UInt())
val wb_reg_set_vconfig = Reg(Bool())
val wb_reg_sfence = Reg(Bool())
val wb_reg_pc = Reg(UInt())
val wb_reg_mem_size = Reg(UInt())
val wb_reg_hls_or_dv = Reg(Bool())
val wb_reg_hfence_v = Reg(Bool())
val wb_reg_hfence_g = Reg(Bool())
val wb_reg_inst = Reg(Bits())
val wb_reg_raw_inst = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_rs2 = Reg(Bits())
val take_pc_wb = Wire(Bool())
val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val take_pc_mem_wb = take_pc_wb || take_pc_mem
val take_pc = take_pc_mem_wb
// decode stage
val ibuf = Module(new IBuf)
val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
val id_inst = id_expanded_inst.map(_.bits)
ibuf.io.imem <> io.imem.resp
ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)
require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point")
require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor")
val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table)
val lgNXRegs = if (coreParams.useRVE) 4 else 5
val regAddrMask = (1 << lgNXRegs) - 1
def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0))
val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3)
val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2)
val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1)
val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd)
val id_load_use = Wire(Bool())
val id_reg_fence = RegInit(false.B)
val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
val rf = new RegFile(regAddrMask, xLen)
val id_rs = id_raddr.map(rf.read _)
val ctrl_killd = Wire(Bool())
val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt
val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined))
val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)
val id_system_insn = id_ctrl.csr === CSR.I
val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U
val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr))
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B
id_ctrl.vec := false.B
if (usingVector) {
val v_decode = rocketParams.vector.get.decoder(p)
v_decode.io.inst := id_inst(0)
v_decode.io.vconfig := csr.io.vector.get.vconfig
when (v_decode.io.legal) {
id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
id_ctrl.fp := v_decode.io.fp
id_ctrl.rocc := false.B
id_ctrl.branch := false.B
id_ctrl.jal := false.B
id_ctrl.jalr := false.B
id_ctrl.rxs2 := v_decode.io.read_rs2
id_ctrl.rxs1 := v_decode.io.read_rs1
id_ctrl.mem := false.B
id_ctrl.rfs1 := v_decode.io.read_frs1
id_ctrl.rfs2 := false.B
id_ctrl.rfs3 := false.B
id_ctrl.wfd := v_decode.io.write_frd
id_ctrl.mul := false.B
id_ctrl.div := false.B
id_ctrl.wxd := v_decode.io.write_rd
id_ctrl.csr := CSR.N
id_ctrl.fence_i := false.B
id_ctrl.fence := false.B
id_ctrl.amo := false.B
id_ctrl.dp := false.B
id_ctrl.vec := true.B
}
}
val id_illegal_insn = !id_ctrl.legal ||
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
(id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
id_raddr2_illegal && id_ctrl.rxs2 ||
id_raddr1_illegal && id_ctrl.rxs1 ||
id_waddr_illegal && id_ctrl.wxd ||
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
!ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal)
val id_virtual_insn = id_ctrl.legal &&
((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) ||
(!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal))
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
val id_amo_aq = id_inst(0)(26)
val id_amo_rl = id_inst(0)(25)
val id_fence_pred = id_inst(0)(27,24)
val id_fence_succ = id_inst(0)(23,20)
val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq
val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
when (!id_mem_busy) { id_reg_fence := false.B }
val id_rocc_busy = usingRoCC.B &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren
val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B)
val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||
id_vec_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status
bpu.io.bp := csr.io.bp
bpu.io.pc := ibuf.io.pc
bpu.io.ea := mem_reg_wdata
bpu.io.mcontext := csr.io.mcontext
bpu.io.scontext := csr.io.scontext
val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
val (id_xcpt, id_cause) = checkExceptions(List(
(csr.io.interrupt, csr.io.interrupt_cause),
(bpu.io.debug_if, CSR.debugTriggerCause.U),
(bpu.io.xcpt_if, Causes.breakpoint.U),
(id_xcpt0.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt0.ae.inst, Causes.fetch_access.U),
(id_xcpt1.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt1.ae.inst, Causes.fetch_access.U),
(id_virtual_insn, Causes.virtual_instruction.U),
(id_illegal_insn, Causes.illegal_instruction.U)))
val idCoverCauses = List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.fetch_access, "FETCH_ACCESS"),
(Causes.illegal_instruction, "ILLEGAL_INSTRUCTION")
) ++ (if (usingVM) List(
(Causes.fetch_page_fault, "FETCH_PAGE_FAULT")
) else Nil)
coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
val dcache_bypass_data =
if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
else wb_reg_wdata
// detect bypass opportunities
val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U
val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U
val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U
val bypass_sources = IndexedSeq(
(true.B, 0.U, 0.U), // treat reading x0 as a bypass
(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W)))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13)
val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq(
A1_RS1 -> ex_rs(0).asSInt,
A1_PC -> ex_reg_pc.asSInt,
A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S)
))
val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt
val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq(
A2_RS2 -> ex_rs(1).asSInt,
A2_IMM -> ex_imm,
A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S),
) ++ (if (coreParams.useZbs) Seq(
A2_RS2OH -> ex_op2_oh,
A2_IMMOH -> ex_op2_oh,
) else Nil))
val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(
ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),
!ex_reg_inst(31) -> ex_reg_inst(30,20))))
val ex_avl = Mux(ex_ctrl.rxs1,
Mux(ex_reg_inst(19,15) === 0.U,
Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
ex_rs(0)
),
ex_reg_inst(19,15))
val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B)
val ex_new_vconfig = Wire(new VConfig)
ex_new_vconfig.vtype := ex_new_vtype
ex_new_vconfig.vl := ex_new_vl
(Some(ex_new_vl), Some(ex_new_vconfig))
} else { (None, None) }
val alu = Module(new ALU)
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.asUInt
alu.io.in1 := ex_op1.asUInt
// multiplier and divider
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
div.io.req.valid := ex_reg_valid && ex_ctrl.div
div.io.req.bits.dw := ex_ctrl.alu_dw
div.io.req.bits.fn := ex_ctrl.alu_fn
div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := ex_waddr
val mul = pipelinedMul.option {
val m = Module(new PipelinedMultiplier(xLen, 2))
m.io.req.valid := ex_reg_valid && ex_ctrl.mul
m.io.req.bits := div.io.req.bits
m
}
ex_reg_valid := !ctrl_killd
ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
ex_reg_xcpt := !ctrl_killd && id_xcpt
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
when (!ctrl_killd) {
ex_ctrl := id_ctrl
ex_reg_rvc := ibuf.io.inst(0).bits.rvc
ex_ctrl.csr := id_csr
when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B }
when (id_fence_next) { id_reg_fence := true.B }
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := FN_ADD
ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
ex_ctrl.sel_alu2 := A2_ZERO
when (id_xcpt1.asUInt.orR) { // badaddr := PC+2
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_SIZE
ex_reg_rvc := true.B
}
when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_ZERO
}
}
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_load_use := id_load_use
ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX)
ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))
when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) {
ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U)
}
when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) {
ex_ctrl.mem_cmd := M_HFENCEV
}
if (tile.dcache.flushOnFenceI) {
when (id_ctrl.fence_i) {
ex_reg_mem_size := 0.U
}
}
for (i <- 0 until id_raddr.size) {
val do_bypass = id_bypass_src(i).reduce(_||_)
val bypass_src = PriorityEncoder(id_bypass_src(i))
ex_reg_rs_bypass(i) := do_bypass
ex_reg_rs_lsb(i) := bypass_src
when (id_ren(i) && !do_bypass) {
ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)
}
}
when (id_illegal_insn || id_virtual_insn) {
val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))
ex_reg_rs_bypass(0) := false.B
ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
}
}
when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
ex_reg_cause := id_cause
ex_reg_inst := id_inst(0)
ex_reg_raw_inst := id_raw_inst(0)
ex_reg_pc := ibuf.io.pc
ex_reg_btb_resp := ibuf.io.btb_resp
ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) }
ex_reg_set_vconfig := id_set_vconfig && !id_xcpt
}
// replay inst in ex stage?
val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt
val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid
val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||
ex_ctrl.div && !div.io.req.ready ||
ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B)
val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use
val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use))
val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid
// detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U
val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG)
val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause)))
val exCoverCauses = idCoverCauses
coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses)
// memory stage
val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
val mem_br_target = mem_reg_pc.asSInt +
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
Mux(mem_reg_rvc, 2.S, 4.S)))
val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt
val mem_wrong_npc =
Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,
Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B))
val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken)
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence)
mem_reg_valid := !ctrl_killx
mem_reg_replay := !take_pc_mem_wb && replay_ex
mem_reg_xcpt := !ctrl_killx && ex_xcpt
mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt
// on pipeline flushes, cause mem_npc to hold the sequential npc, which
// will drive the W-stage npc mux
when (mem_reg_valid && mem_reg_flush_pipe) {
mem_reg_sfence := false.B
}.elsewhen (ex_pc_valid) {
mem_ctrl := ex_ctrl
mem_reg_rvc := ex_reg_rvc
mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
mem_reg_sfence := ex_sfence
mem_reg_btb_resp := ex_reg_btb_resp
mem_reg_flush_pipe := ex_reg_flush_pipe
mem_reg_slow_bypass := ex_slow_bypass
mem_reg_wphit := ex_reg_wphit
mem_reg_set_vconfig := ex_reg_set_vconfig
mem_reg_cause := ex_cause
mem_reg_inst := ex_reg_inst
mem_reg_raw_inst := ex_reg_raw_inst
mem_reg_mem_size := ex_reg_mem_size
mem_reg_hls_or_dv := io.dmem.req.bits.dv
mem_reg_pc := ex_reg_pc
// IDecode ensured they are 1H
mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out)
mem_br_taken := alu.io.cmp_out
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size)
mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data
}
if (usingVector) { when (ex_reg_set_vconfig) {
mem_reg_rs2 := ex_new_vconfig.get.asUInt
} }
when (ex_ctrl.jalr && csr.io.status.debug) {
// flush I$ on D-mode JALR to effect uncached fetch without D$ flush
mem_ctrl.fence_i := true.B
mem_reg_flush_pipe := true.B
}
}
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
(mem_debug_breakpoint, CSR.debugTriggerCause.U),
(mem_breakpoint, Causes.breakpoint.U)))
val (mem_xcpt, mem_cause) = checkExceptions(List(
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
(mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U),
(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
val memCoverCauses = (exCoverCauses ++ List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.misaligned_fetch, "MISALIGNED_FETCH")
)).distinct
coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses)
val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B)
val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B)
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
div.io.kill := killm_common && RegNext(div.io.req.fire)
val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem
// writeback stage
wb_reg_valid := !ctrl_killm
wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B)
wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe
when (mem_pc_valid) {
wb_ctrl := mem_ctrl
wb_reg_sfence := mem_reg_sfence
wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) {
wb_reg_rs2 := mem_reg_rs2
}
wb_reg_cause := mem_cause
wb_reg_inst := mem_reg_inst
wb_reg_raw_inst := mem_reg_raw_inst
wb_reg_mem_size := mem_reg_mem_size
wb_reg_hls_or_dv := mem_reg_hls_or_dv
wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV
wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG
wb_reg_pc := mem_reg_pc
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }
wb_reg_set_vconfig := mem_reg_set_vconfig
}
val (wb_xcpt, wb_cause) = checkExceptions(List(
(wb_reg_xcpt, wb_reg_cause),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U)
))
val wbCoverCauses = List(
(Causes.misaligned_store, "MISALIGNED_STORE"),
(Causes.misaligned_load, "MISALIGNED_LOAD"),
(Causes.store_access, "STORE_ACCESS"),
(Causes.load_access, "LOAD_ACCESS")
) ++ (if(usingVM) List(
(Causes.store_page_fault, "STORE_PAGE_FAULT"),
(Causes.load_page_fault, "LOAD_PAGE_FAULT")
) else Nil) ++ (if (usingHypervisor) List(
(Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"),
(Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"),
) else Nil)
coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses)
val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt
val wb_wxd = wb_reg_valid && wb_ctrl.wxd
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec
val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall
val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B)
val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec
take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool
val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
class LLWB extends Bundle {
val data = UInt(xLen.W)
val tag = UInt(5.W)
}
val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec
ll_arb.io.in.foreach(_.valid := false.B)
ll_arb.io.in.foreach(_.bits := DontCare)
val ll_wdata = WireInit(ll_arb.io.out.bits.data)
val ll_waddr = WireInit(ll_arb.io.out.bits.tag)
val ll_wen = WireInit(ll_arb.io.out.fire)
ll_arb.io.out.ready := !wb_wxd
div.io.resp.ready := ll_arb.io.in(0).ready
ll_arb.io.in(0).valid := div.io.resp.valid
ll_arb.io.in(0).bits.data := div.io.resp.bits.data
ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag
if (usingRoCC) {
io.rocc.resp.ready := ll_arb.io.in(1).ready
ll_arb.io.in(1).valid := io.rocc.resp.valid
ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data
ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd
} else {
// tie off RoCC
io.rocc.resp.ready := false.B
io.rocc.mem.req.ready := false.B
}
io.vector.map { v =>
v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready)
ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp
ll_arb.io.in(2).bits.data := v.resp.bits.data
ll_arb.io.in(2).bits.tag := v.resp.bits.rd
}
// Dont care mem since not all RoCC need accessing memory
io.rocc.mem := DontCare
when (dmem_resp_replay && dmem_resp_xpu) {
ll_arb.io.out.ready := false.B
ll_waddr := dmem_resp_waddr
ll_wen := true.B
}
val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt
val wb_wen = wb_valid && wb_ctrl.wxd
val rf_wen = wb_wen || ll_wen
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
Mux(ll_wen, ll_wdata,
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata),
wb_reg_wdata))))
when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
// hook up control/status regfile
csr.io.ungated_clock := clock
csr.io.decode(0).inst := id_inst(0)
csr.io.exception := wb_xcpt
csr.io.cause := wb_cause
csr.io.retire := wb_valid
csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst)
csr.io.interrupts := io.interrupts
csr.io.hartid := io.hartid
io.fpu.fcsr_rm := csr.io.fcsr_rm
val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W))
val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B)
csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid
csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid))
io.fpu.time := csr.io.time(31,0)
io.fpu.hartid := io.hartid
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
val tval_dmem_addr = !wb_reg_xcpt
val tval_any_addr = tval_dmem_addr ||
wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U)
val tval_inst = wb_reg_cause === Causes.illegal_instruction.U
val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)
csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
val (htval, mhtinst_read_pseudo) = {
val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U
val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)
assert(!htval_valid_imem || io.imem.gpa.valid)
val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR
val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)
val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
// read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation
val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)
(htval, mhtinst_read_pseudo)
}
csr.io.vector.foreach { v =>
v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid
v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig)
v.set_vs_dirty := wb_valid && wb_ctrl.vec
v.set_vstart.valid := wb_valid && wb_reg_set_vconfig
v.set_vstart.bits := 0.U
}
io.vector.foreach { v =>
when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) {
csr.io.pc := v.wb.pc
csr.io.retire := v.wb.retire
csr.io.inst(0) := v.wb.inst
when (v.wb.xcpt && !wb_reg_xcpt) {
wb_xcpt := true.B
wb_cause := v.wb.cause
csr.io.tval := v.wb.tval
}
}
v.wb.store_pending := io.dmem.store_pending
v.wb.vxrm := csr.io.vector.get.vxrm
v.wb.frm := csr.io.fcsr_rm
csr.io.vector.get.set_vxsat := v.set_vxsat
when (v.set_vconfig.valid) {
csr.io.vector.get.set_vconfig.valid := true.B
csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits
}
when (v.set_vstart.valid) {
csr.io.vector.get.set_vstart.valid := true.B
csr.io.vector.get.set_vstart.bits := v.set_vstart.bits
}
}
csr.io.htval := htval
csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo
io.ptw.ptbr := csr.io.ptbr
io.ptw.hgatp := csr.io.hgatp
io.ptw.vsatp := csr.io.vsatp
(io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
io.ptw.status := csr.io.status
io.ptw.hstatus := csr.io.hstatus
io.ptw.gstatus := csr.io.gstatus
io.ptw.pmp := csr.io.pmp
csr.io.rw.addr := wb_reg_inst(31,20)
csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)
csr.io.rw.wdata := wb_reg_wdata
io.rocc.csrs <> csr.io.roccCSRs
io.trace.time := csr.io.time
io.trace.insns := csr.io.trace
if (rocketParams.debugROB.isDefined) {
val sz = rocketParams.debugROB.get.size
if (sz < 1) { // use unsynthesizable ROB
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception)
val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)
val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
io.vector.foreach { v => when (v.wb.retire) {
should_wb := v.wb.rob_should_wb
has_wb := false.B
wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))
}}
DebugROB.pushTrace(clock, reset,
io.hartid, csr_trace_with_wdata,
should_wb, has_wb, wb_addr)
io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
} else { // synthesizable ROB (no FPRs)
require(!usingVector, "Synthesizable ROB does not support vector implementations")
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val debug_rob = Module(new HardDebugROB(sz, 32))
debug_rob.io.i_insn := csr_trace_with_wdata
debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
!csr.io.trace(0).exception
debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
debug_rob.io.wb_val := ll_wen
debug_rob.io.wb_tag := rf_waddr
debug_rob.io.wb_data := rf_wdata
io.trace.insns(0) := debug_rob.io.o_insn
}
} else {
io.trace.insns := csr.io.trace
}
for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {
iobpw.valid(0) := wphit
iobpw.action := bp.control.action
// tie off bpwatch valids
iobpw.rvalid.foreach(_ := false.B)
iobpw.wvalid.foreach(_ := false.B)
iobpw.ivalid.foreach(_ := false.B)
}
val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1),
(id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2),
(id_ctrl.wxd && id_waddr =/= 0.U, id_waddr))
val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),
(io.fpu.dec.ren2, id_raddr2),
(io.fpu.dec.ren3, id_raddr3),
(io.fpu.dec.wen, id_waddr))
val sboard = new Scoreboard(32, true)
sboard.clear(ll_wen, ll_waddr)
def id_sboard_clear_bypass(r: UInt) = {
// ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check
if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r
else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r
}
val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
val mem_mem_cmd_bh =
if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass
else true.B
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem
val id_vconfig_hazard = id_ctrl.vec && (
(ex_reg_valid && ex_reg_set_vconfig) ||
(mem_reg_valid && mem_reg_set_vconfig) ||
(wb_reg_valid && wb_reg_set_vconfig))
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)
val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
val id_stall_fpu = if (usingFPU) {
val fp_sboard = new Scoreboard(32)
fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B)
fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
checkHazards(fp_hazard_targets, fp_sboard.read _)
} else false.B
val dcache_blocked = {
// speculate that a blocked D$ will unblock the cycle after a Grant
val blocked = Reg(Bool())
blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack)
blocked && !io.dmem.perf.grant
}
val rocc_blocked = Reg(Bool())
rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked)
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_vconfig_hazard ||
csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) ||
id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy ||
id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay
!clock_en ||
id_do_fence ||
csr.io.csr_stall ||
id_reg_pause ||
io.traceStall
ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
io.imem.req.valid := take_pc
io.imem.req.bits.speculative := !take_pc_wb
io.imem.req.bits.pc :=
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)) // flush or branch misprediction
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
io.imem.might_request := {
imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B)
imem_might_request_reg
}
io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common)
io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
io.imem.sfence.bits.rs1 := wb_reg_mem_size(0)
io.imem.sfence.bits.rs2 := wb_reg_mem_size(1)
io.imem.sfence.bits.addr := wb_reg_wdata
io.imem.sfence.bits.asid := wb_reg_rs2
io.imem.sfence.bits.hv := wb_reg_hfence_v
io.imem.sfence.bits.hg := wb_reg_hfence_g
io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)
io.imem.btb_update.bits.isValid := mem_cfi
io.imem.btb_update.bits.cfiType :=
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret,
Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump,
CFIType.branch)))
io.imem.btb_update.bits.target := io.imem.req.bits.pc
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc)
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U)
io.imem.btb_update.bits.prediction := mem_reg_btb_resp
io.imem.btb_update.bits.taken := DontCare
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
io.imem.bht_update.bits.taken := mem_br_taken
io.imem.bht_update.bits.mispredict := mem_wrong_npc
io.imem.bht_update.bits.branch := mem_ctrl.branch
io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht
// Connect RAS in Frontend
io.imem.ras_update := DontCare
io.fpu.valid := !ctrl_killd && id_ctrl.fp
io.fpu.killx := ctrl_killx
io.fpu.killm := killm_common
io.fpu.inst := id_inst(0)
io.fpu.fromint_data := ex_rs(0)
io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data)
io.fpu.ll_resp_type := io.dmem.resp.bits.size
io.fpu.ll_resp_tag := dmem_resp_waddr
io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate
io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U)
io.vector.map { v =>
when (!(dmem_resp_valid && dmem_resp_fpu)) {
io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp
io.fpu.ll_resp_data := v.resp.bits.data
io.fpu.ll_resp_type := v.resp.bits.size
io.fpu.ll_resp_tag := v.resp.bits.rd
}
}
io.vector.foreach { v =>
v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx
v.ex.inst := ex_reg_inst
v.ex.vconfig := csr.io.vector.get.vconfig
v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart)
v.ex.rs1 := ex_rs(0)
v.ex.rs2 := ex_rs(1)
v.ex.pc := ex_reg_pc
v.mem.frs1 := io.fpu.store_data
v.killm := killm_common
v.status := csr.io.status
}
io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem
val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)
require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth)
io.dmem.req.bits.tag := ex_dcache_tag
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.size := ex_reg_mem_size
io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))
io.dmem.req.bits.phys := false.B
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)
io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv
io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)
io.dmem.req.bits.no_alloc := DontCare
io.dmem.req.bits.no_xcpt := DontCare
io.dmem.req.bits.data := DontCare
io.dmem.req.bits.mask := DontCare
io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2))
io.dmem.s1_data.mask := DontCare
io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem
io.dmem.s2_kill := false.B
// don't let D$ go to sleep if we're probably going to use it soon
io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
io.rocc.cmd.bits.status := csr.io.status
io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction())
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false.B }
io.cease := csr.io.status.cease && !clock_en_reg
io.wfi := csr.io.status.wfi
if (rocketParams.clockGate) {
long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause
clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid)
clock_en_reg :=
ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight
io.ptw.customCSRs.disableCoreClockGate || // chicken bit
!div.io.req.ready || // mul/div in flight
usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight
io.dmem.replay_next || // long-latency load replaying
(!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending
assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en)
}
// evaluate performance counters
val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
coreMonitorBundle.hartid := io.hartid
coreMonitorBundle.timer := csr.io.time(31,0)
coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen)
coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard
coreMonitorBundle.wrenf := false.B
coreMonitorBundle.wrdst := wb_waddr
coreMonitorBundle.wrdata := rf_wdata
coreMonitorBundle.rd0src := wb_reg_inst(19,15)
coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0)))
coreMonitorBundle.rd1src := wb_reg_inst(24,20)
coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1)))
coreMonitorBundle.inst := csr.io.trace(0).insn
coreMonitorBundle.excpt := csr.io.trace(0).exception
coreMonitorBundle.priv_mode := csr.io.trace(0).priv
if (enableCommitLog) {
val t = csr.io.trace(0)
val rd = wb_waddr
val wfd = wb_ctrl.wfd
val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard
when (t.valid && !t.exception) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U)
}
.elsewhen (wxd && rd =/= 0.U && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= 0.U && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
when (ll_wen && rf_waddr =/= 0.U) {
printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
}
}
else {
when (csr.io.trace(0).valid) {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
coreMonitorBundle.pc,
Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),
Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),
coreMonitorBundle.wrenx,
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),
coreMonitorBundle.inst, coreMonitorBundle.inst)
}
}
// CoreMonitorBundle for late latency writes
val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen))
xrfWriteBundle.clock := clock
xrfWriteBundle.reset := reset
xrfWriteBundle.hartid := io.hartid
xrfWriteBundle.timer := csr.io.time(31,0)
xrfWriteBundle.valid := false.B
xrfWriteBundle.pc := 0.U
xrfWriteBundle.wrdst := rf_waddr
xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr))
xrfWriteBundle.wrenf := false.B
xrfWriteBundle.wrdata := rf_wdata
xrfWriteBundle.rd0src := 0.U
xrfWriteBundle.rd0val := 0.U
xrfWriteBundle.rd1src := 0.U
xrfWriteBundle.rd1val := 0.U
xrfWriteBundle.inst := 0.U
xrfWriteBundle.excpt := false.B
xrfWriteBundle.priv_mode := csr.io.trace(0).priv
if (rocketParams.haveSimTimeout) PlusArg.timeout(
name = "max_core_cycles",
docstring = "Kill the emulation after INT rdtime cycles. Off if 0."
)(csr.io.time)
} // leaving gated-clock domain
val rocketImpl = withClock (gated_clock) { new RocketImpl }
def checkExceptions(x: Seq[(Bool, UInt)]) =
(WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x)))
def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = {
for ((coverCause, label) <- coverCausesLabels) {
property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}")
}
}
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val b = vaddrBitsExtended-1
val a = (a0 >> b).asSInt
val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))
Cat(msb, ea(b-1, 0))
}
class Scoreboard(n: Int, zero: Boolean = false)
{
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
def read(addr: UInt): Bool = r(addr)
def readBypassed(addr: UInt): Bool = _next(addr)
private val _r = RegInit(0.U(n.W))
private val r = if (zero) (_r >> 1 << 1) else _r
private var _next = r
private var ens = false.B
private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U)
private def update(en: Bool, update: UInt) = {
_next = update
ens = ens || en
when (ens) { _r := _next }
}
}
}
class RegFile(n: Int, w: Int, zero: Boolean = false) {
val rf = Mem(n, UInt(w.W))
private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
private val reads = ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> Wire(UInt())
reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr))
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr =/= 0.U) {
access(addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
object ImmGen {
def apply(sel: UInt, inst: UInt) = {
val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)
val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)
val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt)
val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,
Mux(sel === IMM_UJ, inst(20).asSInt,
Mux(sel === IMM_SB, inst(7).asSInt, sign)))
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))
val b4_1 = Mux(sel === IMM_U, 0.U,
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), 0.U)))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt
}
}
File AMOALU.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) {
val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W))
size := typ
val dat_padded = dat.pad(maxSize*8)
def misaligned: Bool =
(addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR
def mask = {
var res = 1.U
for (i <- 0 until log2Up(maxSize)) {
val upper = Mux(addr(i), res, 0.U) | Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U)
val lower = Mux(addr(i), 0.U, res)
res = Cat(upper, lower)
}
res
}
protected def genData(i: Int): UInt =
if (i >= log2Up(maxSize)) dat_padded
else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1))
def data = genData(0)
def wordData = genData(2)
}
class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) {
private val size = new StoreGen(typ, addr, dat, maxSize).size
private def genData(logMinSize: Int): UInt = {
var res = dat
for (i <- log2Up(maxSize)-1 to logMinSize by -1) {
val pos = 8 << i
val shifted = Mux(addr(i), res(2*pos-1,pos), res(pos-1,0))
val doZero = (i == 0).B && zero
val zeroed = Mux(doZero, 0.U, shifted)
res = Cat(Mux(size === i.U || doZero, Fill(8*maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed)
}
res
}
def wordData = genData(2)
def data = genData(0)
}
class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module {
val minXLen = 32
val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _)
val io = IO(new Bundle {
val mask = Input(UInt((operandBits / 8).W))
val cmd = Input(UInt(M_SZ.W))
val lhs = Input(UInt(operandBits.W))
val rhs = Input(UInt(operandBits.W))
val out = Output(UInt(operandBits.W))
val out_unmasked = Output(UInt(operandBits.W))
})
val max = io.cmd === M_XA_MAX || io.cmd === M_XA_MAXU
val min = io.cmd === M_XA_MIN || io.cmd === M_XA_MINU
val add = io.cmd === M_XA_ADD
val logic_and = io.cmd === M_XA_OR || io.cmd === M_XA_AND
val logic_xor = io.cmd === M_XA_XOR || io.cmd === M_XA_OR
val adder_out = {
// partition the carry chain to support sub-xLen addition
val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
(io.lhs & mask) + (io.rhs & mask)
}
val less = {
// break up the comparator so the lower parts will be CSE'd
def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = {
if (n == minXLen) x(n-1, 0) < y(n-1, 0)
else x(n-1, n/2) < y(n-1, n/2) || x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2)
}
def isLess(x: UInt, y: UInt, n: Int): Bool = {
val signed = {
val mask = M_XA_MIN ^ M_XA_MINU
(io.cmd & mask) === (M_XA_MIN & mask)
}
Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1)))
}
PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w))))
}
val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs)
val logic =
Mux(logic_and, io.lhs & io.rhs, 0.U) |
Mux(logic_xor, io.lhs ^ io.rhs, 0.U)
val out =
Mux(add, adder_out,
Mux(logic_and || logic_xor, logic,
minmax))
val wmask = FillInterleaved(8, io.mask)
io.out := wmask & out | ~wmask & io.lhs
io.out_unmasked := out
}
File CSR.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.LinkedHashMap
import Instructions._
import CustomInstructions._
class MStatus extends Bundle {
// not truly part of mstatus, but convenient
val debug = Bool()
val cease = Bool()
val wfi = Bool()
val isa = UInt(32.W)
val dprv = UInt(PRV.SZ.W) // effective prv for data accesses
val dv = Bool() // effective v for data accesses
val prv = UInt(PRV.SZ.W)
val v = Bool()
val sd = Bool()
val zero2 = UInt(23.W)
val mpv = Bool()
val gva = Bool()
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val sd_rv32 = Bool()
val zero1 = UInt(8.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = UInt(1.W)
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val upie = Bool()
val mie = Bool()
val hie = Bool()
val sie = Bool()
val uie = Bool()
}
class MNStatus extends Bundle {
val mpp = UInt(2.W)
val zero3 = UInt(3.W)
val mpv = Bool()
val zero2 = UInt(3.W)
val mie = Bool()
val zero1 = UInt(3.W)
}
class HStatus extends Bundle {
val zero6 = UInt(30.W)
val vsxl = UInt(2.W)
val zero5 = UInt(9.W)
val vtsr = Bool()
val vtw = Bool()
val vtvm = Bool()
val zero3 = UInt(2.W)
val vgein = UInt(6.W)
val zero2 = UInt(2.W)
val hu = Bool()
val spvp = Bool()
val spv = Bool()
val gva = Bool()
val vsbe = Bool()
val zero1 = UInt(5.W)
}
class DCSR extends Bundle {
val xdebugver = UInt(2.W)
val zero4 = UInt(2.W)
val zero3 = UInt(12.W)
val ebreakm = Bool()
val ebreakh = Bool()
val ebreaks = Bool()
val ebreaku = Bool()
val zero2 = Bool()
val stopcycle = Bool()
val stoptime = Bool()
val cause = UInt(3.W)
val v = Bool()
val zero1 = UInt(2.W)
val step = Bool()
val prv = UInt(PRV.SZ.W)
}
class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero1 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
val rocc = Bool()
val sgeip = Bool()
val meip = Bool()
val vseip = Bool()
val seip = Bool()
val ueip = Bool()
val mtip = Bool()
val vstip = Bool()
val stip = Bool()
val utip = Bool()
val msip = Bool()
val vssip = Bool()
val ssip = Bool()
val usip = Bool()
}
class Envcfg extends Bundle {
val stce = Bool() // only for menvcfg/henvcfg
val pbmte = Bool() // only for menvcfg/henvcfg
val zero54 = UInt(54.W)
val cbze = Bool()
val cbcfe = Bool()
val cbie = UInt(2.W)
val zero3 = UInt(3.W)
val fiom = Bool()
def write(wdata: UInt) {
val new_envcfg = wdata.asTypeOf(new Envcfg)
fiom := new_envcfg.fiom // only FIOM is writable currently
}
}
class PTBR(implicit p: Parameters) extends CoreBundle()(p) {
def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0)
def pgLevelsToMode(i: Int) = (xLen, i) match {
case (32, 2) => 1
case (64, x) if x >= 3 && x <= 6 => x + 5
}
val (modeBits, maxASIdBits) = xLen match {
case 32 => (1, 9)
case 64 => (4, 16)
}
require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen)
val mode = UInt(modeBits.W)
val asid = UInt(maxASIdBits.W)
val ppn = UInt((maxPAddrBits - pgIdxBits).W)
}
object PRV
{
val SZ = 2
val U = 0
val S = 1
val H = 2
val M = 3
}
object CSR
{
// commands
val SZ = 3
def X = BitPat.dontCare(SZ)
def N = 0.U(SZ.W)
def R = 2.U(SZ.W)
def I = 4.U(SZ.W)
def W = 5.U(SZ.W)
def S = 6.U(SZ.W)
def C = 7.U(SZ.W)
// mask a CSR cmd with a valid bit
def maskCmd(valid: Bool, cmd: UInt): UInt = {
// all commands less than CSR.I are treated by CSRFile as NOPs
cmd & ~Mux(valid, 0.U, CSR.I)
}
val ADDRSZ = 12
def modeLSB: Int = 8
def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ)
def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB)
def busErrorIntCause = 128
def debugIntCause = 14 // keep in sync with MIP.debug
def debugTriggerCause = {
val res = debugIntCause
require(!(Causes.all contains res))
res
}
def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause
def rnmiBEUCause = 12
val firstCtr = CSRs.cycle
val firstCtrH = CSRs.cycleh
val firstHPC = CSRs.hpmcounter3
val firstHPCH = CSRs.hpmcounter3h
val firstHPE = CSRs.mhpmevent3
val firstMHPC = CSRs.mhpmcounter3
val firstMHPCH = CSRs.mhpmcounter3h
val firstHPM = 3
val nCtr = 32
val nHPM = nCtr - firstHPM
val hpmWidth = 40
val maxPMPs = 16
}
class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val eventSel = Output(UInt(xLen.W))
val inc = Input(UInt(log2Ceil(1+retireWidth).W))
}
class TracedInstruction(implicit p: Parameters) extends CoreBundle {
val valid = Bool()
val iaddr = UInt(coreMaxAddrBits.W)
val insn = UInt(iLen.W)
val priv = UInt(3.W)
val exception = Bool()
val interrupt = Bool()
val cause = UInt(xLen.W)
val tval = UInt((coreMaxAddrBits max iLen).W)
val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W))
}
class TraceAux extends Bundle {
val enable = Bool()
val stall = Bool()
}
class CSRDecodeIO(implicit p: Parameters) extends CoreBundle {
val inst = Input(UInt(iLen.W))
def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0)
val fp_illegal = Output(Bool())
val vector_illegal = Output(Bool())
val fp_csr = Output(Bool())
val vector_csr = Output(Bool())
val rocc_illegal = Output(Bool())
val read_illegal = Output(Bool())
val write_illegal = Output(Bool())
val write_flush = Output(Bool())
val system_illegal = Output(Bool())
val virtual_access_illegal = Output(Bool())
val virtual_system_illegal = Output(Bool())
}
class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle
with HasCoreParameters {
val ungated_clock = Input(Clock())
val interrupts = Input(new CoreInterrupts(hasBeu))
val hartid = Input(UInt(hartIdLen.W))
val rw = new Bundle {
val addr = Input(UInt(CSR.ADDRSZ.W))
val cmd = Input(Bits(CSR.SZ.W))
val rdata = Output(Bits(xLen.W))
val wdata = Input(Bits(xLen.W))
}
val decode = Vec(decodeWidth, new CSRDecodeIO)
val csr_stall = Output(Bool()) // stall retire for wfi
val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall
val eret = Output(Bool())
val singleStep = Output(Bool())
val status = Output(new MStatus())
val hstatus = Output(new HStatus())
val gstatus = Output(new MStatus())
val ptbr = Output(new PTBR())
val hgatp = Output(new PTBR())
val vsatp = Output(new PTBR())
val evec = Output(UInt(vaddrBitsExtended.W))
val exception = Input(Bool())
val retire = Input(UInt(log2Up(1+retireWidth).W))
val cause = Input(UInt(xLen.W))
val pc = Input(UInt(vaddrBitsExtended.W))
val tval = Input(UInt(vaddrBitsExtended.W))
val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W))
val mhtinst_read_pseudo = Input(Bool())
val gva = Input(Bool())
val time = Output(UInt(xLen.W))
val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W)))
val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool()))
val rocc_interrupt = Input(Bool())
val interrupt = Output(Bool())
val interrupt_cause = Output(UInt(xLen.W))
val bp = Output(Vec(nBreakpoints, new BP))
val pmp = Output(Vec(nPMPs, new PMP))
val counters = Vec(nPerfCounters, new PerfCounterIO)
val csrw_counter = Output(UInt(CSR.nCtr.W))
val inhibit_cycle = Output(Bool())
val inst = Input(Vec(retireWidth, UInt(iLen.W)))
val trace = Output(Vec(retireWidth, new TracedInstruction))
val mcontext = Output(UInt(coreParams.mcontextWidth.W))
val scontext = Output(UInt(coreParams.scontextWidth.W))
val fiom = Output(Bool())
val vector = usingVector.option(new Bundle {
val vconfig = Output(new VConfig())
val vstart = Output(UInt(maxVLMax.log2.W))
val vxrm = Output(UInt(2.W))
val set_vs_dirty = Input(Bool())
val set_vconfig = Flipped(Valid(new VConfig))
val set_vstart = Flipped(Valid(vstart))
val set_vxsat = Input(Bool())
})
}
class VConfig(implicit p: Parameters) extends CoreBundle {
val vl = UInt((maxVLMax.log2 + 1).W)
val vtype = new VType
}
object VType {
def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
val res = 0.U.asTypeOf(new VType)
val in = that.asTypeOf(res)
val vill = (in.max_vsew.U < in.vsew) || !in.lmul_ok || in.reserved =/= 0.U || in.vill
when (!vill || ignore_vill.B) {
res := in
res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)
}
res.reserved := 0.U
res.vill := vill
res
}
def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}
class VType(implicit p: Parameters) extends CoreBundle {
val vill = Bool()
val reserved = UInt((xLen - 9).W)
val vma = Bool()
val vta = Bool()
val vsew = UInt(3.W)
val vlmul_sign = Bool()
val vlmul_mag = UInt(2.W)
def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt
@deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9")
def vlmul: UInt = vlmul_mag
def max_vsew = log2Ceil(eLen/8)
def max_vlmul = (1 << vlmul_mag.getWidth) - 1
def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B)
def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1
def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U)
def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)
val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR
val isZero = vill || useZero
Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)
}
}
class CSRFile(
perfEventSets: EventSets = new EventSets(Seq()),
customCSRs: Seq[CustomCSR] = Nil,
roccCSRs: Seq[CustomCSR] = Nil,
hasBeu: Boolean = false)(implicit p: Parameters)
extends CoreModule()(p)
with HasCoreParameters {
val io = IO(new CSRFileIO(hasBeu) {
val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO)
val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO)
})
io.rw_stall := false.B
val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus()))
reset_mstatus.mpp := PRV.M.U
reset_mstatus.prv := PRV.M.U
reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U)
val reg_mstatus = RegInit(reset_mstatus)
val new_prv = WireDefault(reg_mstatus.prv)
reg_mstatus.prv := legalizePrivilege(new_prv)
val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR()))
reset_dcsr.xdebugver := 1.U
reset_dcsr.prv := PRV.M.U
val reg_dcsr = RegInit(reset_dcsr)
val (supported_interrupts, delegable_interrupts) = {
val sup = Wire(new MIP)
sup.usip := false.B
sup.ssip := usingSupervisor.B
sup.vssip := usingHypervisor.B
sup.msip := true.B
sup.utip := false.B
sup.stip := usingSupervisor.B
sup.vstip := usingHypervisor.B
sup.mtip := true.B
sup.ueip := false.B
sup.seip := usingSupervisor.B
sup.vseip := usingHypervisor.B
sup.meip := true.B
sup.sgeip := false.B
sup.rocc := usingRoCC.B
sup.debug := false.B
sup.zero1 := false.B
sup.lip foreach { _ := true.B }
val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U
val del = WireDefault(sup)
del.msip := false.B
del.mtip := false.B
del.meip := false.B
(sup.asUInt | supported_high_interrupts, del.asUInt)
}
val delegable_base_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_page_fault,
Causes.breakpoint,
Causes.load_page_fault,
Causes.store_page_fault,
Causes.misaligned_load,
Causes.misaligned_store,
Causes.illegal_instruction,
Causes.user_ecall,
)
val delegable_hypervisor_exceptions = Seq(
Causes.virtual_supervisor_ecall,
Causes.fetch_guest_page_fault,
Causes.load_guest_page_fault,
Causes.virtual_instruction,
Causes.store_guest_page_fault,
)
val delegable_exceptions = (
delegable_base_exceptions
++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq())
).map(1 << _).sum.U
val hs_delegable_exceptions = Seq(
Causes.misaligned_fetch,
Causes.fetch_access,
Causes.illegal_instruction,
Causes.breakpoint,
Causes.misaligned_load,
Causes.load_access,
Causes.misaligned_store,
Causes.store_access,
Causes.user_ecall,
Causes.fetch_page_fault,
Causes.load_page_fault,
Causes.store_page_fault).map(1 << _).sum.U
val (hs_delegable_interrupts, mideleg_always_hs) = {
val always = WireDefault(0.U.asTypeOf(new MIP()))
always.vssip := usingHypervisor.B
always.vstip := usingHypervisor.B
always.vseip := usingHypervisor.B
val deleg = WireDefault(always)
deleg.lip.foreach { _ := usingHypervisor.B }
(deleg.asUInt, always.asUInt)
}
val reg_debug = RegInit(false.B)
val reg_dpc = Reg(UInt(vaddrBitsExtended.W))
val reg_dscratch0 = Reg(UInt(xLen.W))
val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W)))
val reg_singleStepped = Reg(Bool())
val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W)))
val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W)))
val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W))
val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP))
val reg_pmp = Reg(Vec(nPMPs, new PMPReg))
val reg_mie = Reg(UInt(xLen.W))
val (reg_mideleg, read_mideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_interrupts | mideleg_always_hs, 0.U))
}
val (reg_medeleg, read_medeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U))
}
val reg_mip = Reg(new MIP)
val reg_mepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mcause = RegInit(0.U(xLen.W))
val reg_mtval = Reg(UInt(vaddrBitsExtended.W))
val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W))
val reg_mscratch = Reg(Bits(xLen.W))
val mtvecWidth = paddrBits min xLen
val reg_mtvec = mtvecInit match {
case Some(addr) => RegInit(addr.U(mtvecWidth.W))
case None => Reg(UInt(mtvecWidth.W))
}
val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus()))
reset_mnstatus.mpp := PRV.M.U
val reg_mnscratch = Reg(Bits(xLen.W))
val reg_mnepc = Reg(UInt(vaddrBitsExtended.W))
val reg_mncause = RegInit(0.U(xLen.W))
val reg_mnstatus = RegInit(reset_mnstatus)
val reg_rnmie = RegInit(true.B)
val nmie = reg_rnmie
val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg))
val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U
val (reg_mcounteren, read_mcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingUser.B, reg & delegable_counters, 0.U))
}
val (reg_scounteren, read_scounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U))
}
val (reg_hideleg, read_hideleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U))
}
val (reg_hedeleg, read_hedeleg) = {
val reg = Reg(UInt(xLen.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U))
}
val hs_delegable_counters = delegable_counters
val (reg_hcounteren, read_hcounteren) = {
val reg = Reg(UInt(32.W))
(reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U))
}
val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus))
val reg_hgatp = Reg(new PTBR)
val reg_htval = Reg(reg_mtval2.cloneType)
val read_hvip = reg_mip.asUInt & hs_delegable_interrupts
val read_hie = reg_mie & hs_delegable_interrupts
val (reg_vstvec, read_vstvec) = {
val reg = Reg(UInt(vaddrBitsExtended.W))
(reg, formTVec(reg).sextTo(xLen))
}
val reg_vsstatus = Reg(new MStatus)
val reg_vsscratch = Reg(Bits(xLen.W))
val reg_vsepc = Reg(UInt(vaddrBitsExtended.W))
val reg_vscause = Reg(Bits(xLen.W))
val reg_vstval = Reg(UInt(vaddrBitsExtended.W))
val reg_vsatp = Reg(new PTBR)
val reg_sepc = Reg(UInt(vaddrBitsExtended.W))
val reg_scause = Reg(Bits(xLen.W))
val reg_stval = Reg(UInt(vaddrBitsExtended.W))
val reg_sscratch = Reg(Bits(xLen.W))
val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W))
val reg_satp = Reg(new PTBR)
val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) }
val reg_fflags = Reg(UInt(5.W))
val reg_frm = Reg(UInt(3.W))
val reg_vconfig = usingVector.option(Reg(new VConfig))
val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W)))
val reg_vxsat = usingVector.option(Reg(Bool()))
val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W)))
val reg_mtinst_read_pseudo = Reg(Bool())
val reg_htinst_read_pseudo = Reg(Bool())
// XLEN=32: 0x00002000
// XLEN=64: 0x00003000
val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W)))
val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W))
io.inhibit_cycle := reg_mcountinhibit(0)
val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2))
val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0))
else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) }
val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W)))
(io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e }
val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) =>
WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) }
val mip = WireDefault(reg_mip)
mip.lip := (io.interrupts.lip: Seq[Bool])
mip.mtip := io.interrupts.mtip
mip.msip := io.interrupts.msip
mip.meip := io.interrupts.meip
// seip is the OR of reg_mip.seip and the actual line from the PLIC
io.interrupts.seip.foreach { mip.seip := reg_mip.seip || _ }
// Simimlar sort of thing would apply if the PLIC had a VSEIP line:
//io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip || _ }
mip.rocc := io.rocc_interrupt
val read_mip = mip.asUInt & supported_interrupts
val read_hip = read_mip & hs_delegable_interrupts
val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U))
val pending_interrupts = high_interrupts | (read_mip & reg_mie)
val d_interrupts = io.interrupts.debug << CSR.debugIntCause
val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi =>
(((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) |
io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U),
!io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B)
val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U || reg_mstatus.mie), ~(~pending_interrupts | read_mideleg), 0.U)
val s_interrupts = Mux(nmie && (reg_mstatus.v || reg_mstatus.prv < PRV.S.U || (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U)
val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U || reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U)
val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts))
val interruptMSB = BigInt(1) << (xLen-1)
val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt
io.interrupt := (anyInterrupt && !io.singleStep || reg_singleStepped) && !(reg_debug || io.status.cease)
io.interrupt_cause := interruptCause
io.bp := reg_bp take nBreakpoints
io.mcontext := reg_mcontext.getOrElse(0.U)
io.scontext := reg_scontext.getOrElse(0.U)
io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) || (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) || (reg_mstatus.v && reg_henvcfg.fiom)
io.pmp := reg_pmp.map(PMP(_))
val isaMaskString =
(if (usingMulDiv) "M" else "") +
(if (usingAtomics) "A" else "") +
(if (fLen >= 32) "F" else "") +
(if (fLen >= 64) "D" else "") +
(if (coreParams.hasV) "V" else "") +
(if (usingCompressed) "C" else "")
val isaString = (if (coreParams.useRVE) "E" else "I") +
isaMaskString +
(if (customIsaExt.isDefined || usingRoCC) "X" else "") +
(if (usingSupervisor) "S" else "") +
(if (usingHypervisor) "H" else "") +
(if (usingUser) "U" else "")
val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) | isaStringToMask(isaString)
val reg_misa = RegInit(isaMax.U)
val read_mstatus = io.status.asUInt.extract(xLen-1,0)
val read_mtvec = formTVec(reg_mtvec).padTo(xLen)
val read_stvec = formTVec(reg_stvec).sextTo(xLen)
val read_mapping = LinkedHashMap[Int,Bits](
CSRs.tselect -> reg_tselect,
CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt,
CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen),
CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt,
CSRs.misa -> reg_misa,
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> read_mtvec,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,
CSRs.mscratch -> reg_mscratch,
CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen),
CSRs.mtval -> reg_mtval.sextTo(xLen),
CSRs.mcause -> reg_mcause,
CSRs.mhartid -> io.hartid)
val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.dcsr -> reg_dcsr.asUInt,
CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen),
CSRs.dscratch0 -> reg_dscratch0.asUInt) ++
reg_dscratch1.map(r => CSRs.dscratch1 -> r)
val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus()))
read_mnstatus.mpp := reg_mnstatus.mpp
read_mnstatus.mpv := reg_mnstatus.mpv
read_mnstatus.mie := reg_rnmie
val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](
CustomCSRs.mnscratch -> reg_mnscratch,
CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
CustomCSRs.mncause -> reg_mncause,
CustomCSRs.mnstatus -> read_mnstatus.asUInt)
val context_csrs = LinkedHashMap[Int,Bits]() ++
reg_mcontext.map(r => CSRs.mcontext -> r) ++
reg_scontext.map(r => CSRs.scontext -> r)
val read_fcsr = Cat(reg_frm, reg_fflags)
val fp_csrs = LinkedHashMap[Int,Bits]() ++
usingFPU.option(CSRs.fflags -> reg_fflags) ++
usingFPU.option(CSRs.frm -> reg_frm) ++
(usingFPU || usingVector).option(CSRs.fcsr -> read_fcsr)
val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U))
val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits](
CSRs.vxsat -> reg_vxsat.get,
CSRs.vxrm -> reg_vxrm.get,
CSRs.vcsr -> read_vcsr,
CSRs.vstart -> reg_vstart.get,
CSRs.vtype -> reg_vconfig.get.vtype.asUInt,
CSRs.vl -> reg_vconfig.get.vl,
CSRs.vlenb -> (vLen / 8).U)
read_mapping ++= debug_csrs
read_mapping ++= nmi_csrs
read_mapping ++= context_csrs
read_mapping ++= fp_csrs
read_mapping ++= vector_csrs
if (coreParams.haveBasicCounters) {
read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit
read_mapping += CSRs.mcycle -> reg_cycle
read_mapping += CSRs.minstret -> reg_instret
for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U)
zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) {
read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN
read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN
read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN
if (xLen == 32) {
read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh
read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh
}
}
if (usingUser) {
read_mapping += CSRs.mcounteren -> read_mcounteren
}
read_mapping += CSRs.cycle -> reg_cycle
read_mapping += CSRs.instret -> reg_instret
if (xLen == 32) {
read_mapping += CSRs.mcycleh -> (reg_cycle >> 32)
read_mapping += CSRs.minstreth -> (reg_instret >> 32)
read_mapping += CSRs.cycleh -> (reg_cycle >> 32)
read_mapping += CSRs.instreth -> (reg_instret >> 32)
}
}
if (usingUser) {
read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32)
}
val sie_mask = {
val sgeip_mask = WireInit(0.U.asTypeOf(new MIP))
sgeip_mask.sgeip := true.B
read_mideleg & ~(hs_delegable_interrupts | sgeip_mask.asUInt)
}
if (usingSupervisor) {
val read_sie = reg_mie & sie_mask
val read_sip = read_mip & sie_mask
val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus))
read_sstatus.sd := io.status.sd
read_sstatus.uxl := io.status.uxl
read_sstatus.sd_rv32 := io.status.sd_rv32
read_sstatus.mxr := io.status.mxr
read_sstatus.sum := io.status.sum
read_sstatus.xs := io.status.xs
read_sstatus.fs := io.status.fs
read_sstatus.vs := io.status.vs
read_sstatus.spp := io.status.spp
read_sstatus.spie := io.status.spie
read_sstatus.sie := io.status.sie
read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0)
read_mapping += CSRs.sip -> read_sip.asUInt
read_mapping += CSRs.sie -> read_sie.asUInt
read_mapping += CSRs.sscratch -> reg_sscratch
read_mapping += CSRs.scause -> reg_scause
read_mapping += CSRs.stval -> reg_stval.sextTo(xLen)
read_mapping += CSRs.satp -> reg_satp.asUInt
read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen)
read_mapping += CSRs.stvec -> read_stvec
read_mapping += CSRs.scounteren -> read_scounteren
read_mapping += CSRs.mideleg -> read_mideleg
read_mapping += CSRs.medeleg -> read_medeleg
read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt
}
val pmpCfgPerCSR = xLen / new PMPConfig().getWidth
def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR)
if (reg_pmp.nonEmpty) {
require(reg_pmp.size <= CSR.maxPMPs)
val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP))
for (i <- 0 until read_pmp.size by pmpCfgPerCSR)
read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt
for ((pmp, i) <- read_pmp.zipWithIndex)
read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr
}
// implementation-defined CSRs
def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = {
require(csr.mask >= 0 && csr.mask.bitLength <= xLen)
require(!read_mapping.contains(csr.id))
val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W)))
val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U
csr_io.ren := read
when (read && csr_io.stall) { io.rw_stall := true.B }
read_mapping += csr.id -> reg
reg
}
val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2))
val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2))
if (usingHypervisor) {
read_mapping += CSRs.mtinst -> read_mtinst
read_mapping += CSRs.mtval2 -> reg_mtval2
val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.hstatus -> read_hstatus
read_mapping += CSRs.hedeleg -> read_hedeleg
read_mapping += CSRs.hideleg -> read_hideleg
read_mapping += CSRs.hcounteren-> read_hcounteren
read_mapping += CSRs.hgatp -> reg_hgatp.asUInt
read_mapping += CSRs.hip -> read_hip
read_mapping += CSRs.hie -> read_hie
read_mapping += CSRs.hvip -> read_hvip
read_mapping += CSRs.hgeie -> 0.U
read_mapping += CSRs.hgeip -> 0.U
read_mapping += CSRs.htval -> reg_htval
read_mapping += CSRs.htinst -> read_htinst
read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt
if (xLen == 32)
read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32)
val read_vsie = (read_hie & read_hideleg) >> 1
val read_vsip = (read_hip & read_hideleg) >> 1
val read_vsepc = readEPC(reg_vsepc).sextTo(xLen)
val read_vstval = reg_vstval.sextTo(xLen)
val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0)
read_mapping += CSRs.vsstatus -> read_vsstatus
read_mapping += CSRs.vsip -> read_vsip
read_mapping += CSRs.vsie -> read_vsie
read_mapping += CSRs.vsscratch -> reg_vsscratch
read_mapping += CSRs.vscause -> reg_vscause
read_mapping += CSRs.vstval -> read_vstval
read_mapping += CSRs.vsatp -> reg_vsatp.asUInt
read_mapping += CSRs.vsepc -> read_vsepc
read_mapping += CSRs.vstvec -> read_vstvec
}
// mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs
Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U))
val decoded_addr = {
val addr = Cat(io.status.v, io.rw.addr)
val pats = for (((k, _), i) <- read_mapping.zipWithIndex)
yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B)))
val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats)
val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap
for ((k, v) <- unvirtualized_mapping) yield k -> {
val alt: Option[Bool] = CSR.mode(k) match {
// hcontext was assigned an unfortunate address; it lives where a
// hypothetical vscontext will live. Exclude them from the S/VS remapping.
// (on separate lines so scala-lint doesnt do something stupid)
case _ if k == CSRs.scontext => None
case _ if k == CSRs.hcontext => None
// When V=1, if a corresponding VS CSR exists, access it instead...
case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB))
// ...and don't access the original S-mode version.
case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B)
case _ => None
}
alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v)
}
}
val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata)
val system_insn = io.rw.cmd === CSR.I
val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU)
val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N),
EBREAK-> List(N,Y,N,N,N,N,N,N,N),
MRET-> List(N,N,Y,N,N,N,N,N,N),
CEASE-> List(N,N,N,Y,N,N,N,N,N),
WFI-> List(N,N,N,N,Y,N,N,N,N)) ++
usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++
coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++
usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++
usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++
usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++
usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++
(if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq())
val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = {
val insn = ECALL.value.U | (io.rw.addr << 20)
DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool)
}
for (io_dec <- io.decode) {
val addr = io_dec.inst(31, 20)
def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_||_)
def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U))
val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil =
DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool)
val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) || addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U))
val allow_wfi = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !reg_mstatus.tw && (!reg_mstatus.v || !reg_hstatus.vtw)
val allow_sfence_vma = (!usingVM).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
val allow_hfence_vvma = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U)
val allow_hlsv = (!usingHypervisor).B || !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U || reg_hstatus.hu)
val allow_sret = (!usingSupervisor).B || reg_mstatus.prv > PRV.S.U || !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0)
val allow_counter = (reg_mstatus.prv > PRV.S.U || read_mcounteren(counter_addr)) &&
(!usingSupervisor.B || reg_mstatus.prv >= PRV.S.U || read_scounteren(counter_addr)) &&
(!usingHypervisor.B || !reg_mstatus.v || read_hcounteren(counter_addr))
io_dec.fp_illegal := io.status.fs === 0.U || reg_mstatus.v && reg_vsstatus.fs === 0.U || !reg_misa('f'-'a')
io_dec.vector_illegal := io.status.vs === 0.U || reg_mstatus.v && reg_vsstatus.vs === 0.U || !reg_misa('v'-'a')
io_dec.fp_csr := decodeFast(fp_csrs.keys.toList)
io_dec.vector_csr := decodeFast(vector_csrs.keys.toList)
io_dec.rocc_illegal := io.status.xs === 0.U || reg_mstatus.v && reg_vsstatus.xs === 0.U || !reg_misa('x'-'a')
val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) ||
usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U
val csr_exists = decodeAny(read_mapping)
io_dec.read_illegal := !csr_addr_legal ||
!csr_exists ||
((addr === CSRs.satp.U || addr === CSRs.hgatp.U) && !allow_sfence_vma) ||
is_counter && !allow_counter ||
decodeFast(debug_csrs.keys.toList) && !reg_debug ||
decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal ||
io_dec.fp_csr && io_dec.fp_illegal
io_dec.write_illegal := addr(11,10).andR
io_dec.write_flush := {
val addr_m = addr | (PRV.M.U << CSR.modeLSB)
!(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U)
}
io_dec.system_illegal := !csr_addr_legal && !is_hlsv ||
is_wfi && !allow_wfi ||
is_ret && !allow_sret ||
is_ret && addr(10) && addr(7) && !reg_debug ||
(is_sfence || is_hfence_gvma) && !allow_sfence_vma ||
is_hfence_vvma && !allow_hfence_vvma ||
is_hlsv && !allow_hlsv
io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && (
CSR.mode(addr) === PRV.H.U ||
is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) || !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) ||
CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) ||
addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm)
io_dec.virtual_system_illegal := reg_mstatus.v && (
is_hfence_vvma ||
is_hfence_gvma ||
is_hlsv ||
is_wfi && (!reg_mstatus.prv(0) || !reg_mstatus.tw && reg_hstatus.vtw) ||
is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) || reg_hstatus.vtsr) ||
is_sfence && (!reg_mstatus.prv(0) || reg_hstatus.vtvm))
}
val cause =
Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv),
Mux[UInt](insn_break, Causes.breakpoint.U, io.cause))
val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0)
val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0)
val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U
val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U
val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv)
val trapToDebug = usingDebug.B && (reg_singleStepped || causeIsDebugInt || causeIsDebugTrigger || causeIsDebugBreak || reg_debug)
val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800))
val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808))
val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U)
val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs))
val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs))
def mtvecBaseAlign = 2
def mtvecInterruptAlign = {
require(reg_mip.getWidth <= xLen)
log2Ceil(xLen)
}
val notDebugTVec = {
val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec)
val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign
val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset)
val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U
Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign)
}
val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U || cause_lsbs === CSR.rnmiBEUCause.U)
val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U
val causeIsNmi = causeIsRnmiInt
val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U)
val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U)
val trapToNmiInt = usingNMI.B && causeIsNmi
val trapToNmiXcpt = usingNMI.B && !nmie
val trapToNmi = trapToNmiInt || trapToNmiXcpt
val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1
val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec))
io.evec := tvec
io.ptbr := reg_satp
io.hgatp := reg_hgatp
io.vsatp := reg_vsatp
io.eret := insn_call || insn_break || insn_ret
io.singleStep := reg_dcsr.step && !reg_debug
io.status := reg_mstatus
io.status.sd := io.status.fs.andR || io.status.xs.andR || io.status.vs.andR
io.status.debug := reg_debug
io.status.isa := reg_misa
io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv)
io.status.dv := reg_mstatus.v || Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B)
io.status.sd_rv32 := (xLen == 32).B && io.status.sd
io.status.mpv := reg_mstatus.mpv
io.status.gva := reg_mstatus.gva
io.hstatus := reg_hstatus
io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U
io.gstatus := reg_vsstatus
io.gstatus.sd := io.gstatus.fs.andR || io.gstatus.xs.andR || io.gstatus.vs.andR
io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U
io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd
val exception = insn_call || insn_break || io.exception
assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive")
when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B }
when (pending_interrupts.orR || io.interrupts.debug || exception) { reg_wfi := false.B }
io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } )
when (io.retire(0) || exception) { reg_singleStepped := true.B }
when (!io.singleStep) { reg_singleStepped := false.B }
assert(!io.singleStep || io.retire <= 1.U)
assert(!reg_singleStepped || io.retire === 0.U)
val epc = formEPC(io.pc)
val tval = Mux(insn_break, epc, io.tval)
when (exception) {
when (trapToDebug) {
when (!reg_debug) {
reg_mstatus.v := false.B
reg_debug := true.B
reg_dpc := epc
reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U)))
reg_dcsr.prv := trimPrivilege(reg_mstatus.prv)
reg_dcsr.v := reg_mstatus.v
new_prv := PRV.M.U
}
}.elsewhen (trapToNmiInt) {
when (reg_rnmie) {
reg_mstatus.v := false.B
reg_mnstatus.mpv := reg_mstatus.v
reg_rnmie := false.B
reg_mnepc := epc
reg_mncause := (BigInt(1) << (xLen-1)).U | Mux(causeIsRnmiBEU, 3.U, 2.U)
reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv)
new_prv := PRV.M.U
}
}.elsewhen (delegateVS && nmie) {
reg_mstatus.v := true.B
reg_vsstatus.spp := reg_mstatus.prv
reg_vsepc := epc
reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause)
reg_vstval := tval
reg_vsstatus.spie := reg_vsstatus.sie
reg_vsstatus.sie := false.B
new_prv := PRV.S.U
}.elsewhen (delegate && nmie) {
reg_mstatus.v := false.B
reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp)
reg_hstatus.gva := io.gva
reg_hstatus.spv := reg_mstatus.v
reg_sepc := epc
reg_scause := cause
reg_stval := tval
reg_htval := io.htval
reg_htinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.spie := reg_mstatus.sie
reg_mstatus.spp := reg_mstatus.prv
reg_mstatus.sie := false.B
new_prv := PRV.S.U
}.otherwise {
reg_mstatus.v := false.B
reg_mstatus.mpv := reg_mstatus.v
reg_mstatus.gva := io.gva
reg_mepc := epc
reg_mcause := cause
reg_mtval := tval
reg_mtval2 := io.htval
reg_mtinst_read_pseudo := io.mhtinst_read_pseudo
reg_mstatus.mpie := reg_mstatus.mie
reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv)
reg_mstatus.mie := false.B
new_prv := PRV.M.U
}
}
for (i <- 0 until supported_interrupts.getWidth) {
val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U
val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"INTERRUPT_M_$i")
property.cover(en && delegable && delegate, s"INTERRUPT_S_$i")
}
for (i <- 0 until xLen) {
val supported_exceptions: BigInt = 0x8fe |
(if (usingCompressed && !coreParams.misaWritable) 0 else 1) |
(if (usingUser) 0x100 else 0) |
(if (usingSupervisor) 0x200 else 0) |
(if (usingVM) 0xb000 else 0)
if (((supported_exceptions >> i) & 1) != 0) {
val en = exception && cause === i.U
val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U
property.cover(en && !delegate, s"EXCEPTION_M_$i")
property.cover(en && delegable && delegate, s"EXCEPTION_S_$i")
}
}
when (insn_ret) {
val ret_prv = WireInit(UInt(), DontCare)
when (usingSupervisor.B && !io.rw.addr(9)) {
when (!reg_mstatus.v) {
reg_mstatus.sie := reg_mstatus.spie
reg_mstatus.spie := true.B
reg_mstatus.spp := PRV.U.U
ret_prv := reg_mstatus.spp
reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv
io.evec := readEPC(reg_sepc)
reg_hstatus.spv := false.B
}.otherwise {
reg_vsstatus.sie := reg_vsstatus.spie
reg_vsstatus.spie := true.B
reg_vsstatus.spp := PRV.U.U
ret_prv := reg_vsstatus.spp
reg_mstatus.v := usingHypervisor.B
io.evec := readEPC(reg_vsepc)
}
}.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) {
ret_prv := reg_dcsr.prv
reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U
reg_debug := false.B
io.evec := readEPC(reg_dpc)
}.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) {
ret_prv := reg_mnstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U
reg_rnmie := true.B
io.evec := readEPC(reg_mnepc)
}.otherwise {
reg_mstatus.mie := reg_mstatus.mpie
reg_mstatus.mpie := true.B
reg_mstatus.mpp := legalizePrivilege(PRV.U.U)
reg_mstatus.mpv := false.B
ret_prv := reg_mstatus.mpp
reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U
io.evec := readEPC(reg_mepc)
}
new_prv := ret_prv
when (usingUser.B && ret_prv <= PRV.S.U) {
reg_mstatus.mprv := false.B
}
}
io.time := reg_cycle
io.csr_stall := reg_wfi || io.status.cease
io.status.cease := RegEnable(true.B, false.B, insn_cease)
io.status.wfi := reg_wfi
for ((io, reg) <- io.customCSRs zip reg_custom) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
for ((io, reg) <- io.roccCSRs zip reg_rocc) {
io.wen := false.B
io.wdata := wdata
io.value := reg
}
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
// cover access to register
val coverable_counters = read_mapping.filterNot { case (k, _) =>
k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM
}
coverable_counters.foreach( {case (k, v) => {
when (!k.U(11,10).andR) { // Cover points for RW CSR registers
property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
} .otherwise { // Cover points for RO CSR registers
property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field")
}
}})
val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B))
io.vector.foreach { vio =>
when (set_vs_dirty) {
assert(reg_mstatus.vs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.vs := 3.U }
reg_mstatus.vs := 3.U
}
}
val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B))
if (coreParams.haveFSDirty) {
when (set_fs_dirty) {
assert(reg_mstatus.fs > 0.U)
when (reg_mstatus.v) { reg_vsstatus.fs := 3.U }
reg_mstatus.fs := 3.U
}
}
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
set_fs_dirty := true.B
}
io.vector.foreach { vio =>
when (vio.set_vxsat) {
reg_vxsat.get := true.B
set_vs_dirty := true.B
}
}
val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall
io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) || io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U)
when (csr_wen) {
val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB */
val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_))
when (decoded_addr(CSRs.mstatus)) {
val new_mstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.mie := new_mstatus.mie
reg_mstatus.mpie := new_mstatus.mpie
if (usingUser) {
reg_mstatus.mprv := new_mstatus.mprv
reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp)
if (usingSupervisor) {
reg_mstatus.spp := new_mstatus.spp
reg_mstatus.spie := new_mstatus.spie
reg_mstatus.sie := new_mstatus.sie
reg_mstatus.tw := new_mstatus.tw
reg_mstatus.tsr := new_mstatus.tsr
}
if (usingVM) {
reg_mstatus.mxr := new_mstatus.mxr
reg_mstatus.sum := new_mstatus.sum
reg_mstatus.tvm := new_mstatus.tvm
}
if (usingHypervisor) {
reg_mstatus.mpv := new_mstatus.mpv
reg_mstatus.gva := new_mstatus.gva
}
}
if (usingSupervisor || usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs)
reg_mstatus.vs := formVS(new_mstatus.vs)
}
when (decoded_addr(CSRs.misa)) {
val mask = isaStringToMask(isaMaskString).U(xLen.W)
val f = wdata('f' - 'a')
// suppress write if it would cause the next fetch to be misaligned
when (!usingCompressed.B || !io.pc(1) || wdata('c' - 'a')) {
if (coreParams.misaWritable)
reg_misa := ~(~wdata | (!f << ('d' - 'a'))) & mask | reg_misa & ~mask
}
}
when (decoded_addr(CSRs.mip)) {
// MIP should be modified based on the value in reg_mip, not the value
// in read_mip, since read_mip.seip is the OR of reg_mip.seip and
// io.interrupts.seip. We don't want the value on the PLIC line to
// inadvertently be OR'd into read_mip.seip.
val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP)
if (usingSupervisor) {
reg_mip.ssip := new_mip.ssip
reg_mip.stip := new_mip.stip
reg_mip.seip := new_mip.seip
}
if (usingHypervisor) {
reg_mip.vssip := new_mip.vssip
}
}
when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts }
when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) }
when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata }
if (mtvecWritable)
when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata }
when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U }
when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata }
if (usingNMI) {
val new_mnstatus = wdata.asTypeOf(new MNStatus())
when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }
when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) }
when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U }
when (decoded_addr(CustomCSRs.mnstatus)) {
reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)
reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv
reg_rnmie := reg_rnmie | new_mnstatus.mie // mnie bit settable but not clearable from software
}
}
for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) {
writeCounter(i + CSR.firstMHPC, c, wdata)
when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) }
}
if (coreParams.haveBasicCounters) {
when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero
writeCounter(CSRs.mcycle, reg_cycle, wdata)
writeCounter(CSRs.minstret, reg_instret, wdata)
}
if (usingFPU) {
when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) {
set_fs_dirty := true.B
reg_fflags := wdata
reg_frm := wdata >> reg_fflags.getWidth
}
}
if (usingDebug) {
when (decoded_addr(CSRs.dcsr)) {
val new_dcsr = wdata.asTypeOf(new DCSR())
reg_dcsr.step := new_dcsr.step
reg_dcsr.ebreakm := new_dcsr.ebreakm
if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks
if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku
if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv)
if (usingHypervisor) reg_dcsr.v := new_dcsr.v
}
when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) }
when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata }
reg_dscratch1.foreach { r =>
when (decoded_addr(CSRs.dscratch1)) { r := wdata }
}
}
if (usingSupervisor) {
when (decoded_addr(CSRs.sstatus)) {
val new_sstatus = wdata.asTypeOf(new MStatus())
reg_mstatus.sie := new_sstatus.sie
reg_mstatus.spie := new_sstatus.spie
reg_mstatus.spp := new_sstatus.spp
reg_mstatus.fs := formFS(new_sstatus.fs)
reg_mstatus.vs := formVS(new_sstatus.vs)
if (usingVM) {
reg_mstatus.mxr := new_sstatus.mxr
reg_mstatus.sum := new_sstatus.sum
}
}
when (decoded_addr(CSRs.sip)) {
val new_sip = ((read_mip & ~read_mideleg) | (wdata & read_mideleg)).asTypeOf(new MIP())
reg_mip.ssip := new_sip.ssip
}
when (decoded_addr(CSRs.satp)) {
if (usingVM) {
val new_satp = wdata.asTypeOf(new PTBR())
when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) {
reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_|_).U
reg_satp.ppn := new_satp.ppn(ppnBits-1,0)
if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0)
}
}
}
when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) | (wdata & sie_mask) }
when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata }
when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) }
when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata }
when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask }
when (decoded_addr(CSRs.stval)) { reg_stval := wdata }
when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata }
when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata }
when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata }
when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) }
}
if (usingHypervisor) {
when (decoded_addr(CSRs.hstatus)) {
val new_hstatus = wdata.asTypeOf(new HStatus())
reg_hstatus.gva := new_hstatus.gva
reg_hstatus.spv := new_hstatus.spv
reg_hstatus.spvp := new_hstatus.spvp
reg_hstatus.hu := new_hstatus.hu
reg_hstatus.vtvm := new_hstatus.vtvm
reg_hstatus.vtw := new_hstatus.vtw
reg_hstatus.vtsr := new_hstatus.vtsr
reg_hstatus.vsxl := new_hstatus.vsxl
}
when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata }
when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata }
when (decoded_addr(CSRs.hgatp)) {
val new_hgatp = wdata.asTypeOf(new PTBR())
val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_))
when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) {
reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_|_).U
}
reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W))
if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0)
}
when (decoded_addr(CSRs.hip)) {
val new_hip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_hip.vssip
}
when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts) }
when (decoded_addr(CSRs.hvip)) {
val new_sip = ((read_mip & ~hs_delegable_interrupts) | (wdata & hs_delegable_interrupts)).asTypeOf(new MIP())
reg_mip.vssip := new_sip.vssip
reg_mip.vstip := new_sip.vstip
reg_mip.vseip := new_sip.vseip
}
when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata }
when (decoded_addr(CSRs.htval)) { reg_htval := wdata }
when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata }
val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12))
when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo }
when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo }
when (decoded_addr(CSRs.vsstatus)) {
val new_vsstatus = wdata.asTypeOf(new MStatus())
reg_vsstatus.sie := new_vsstatus.sie
reg_vsstatus.spie := new_vsstatus.spie
reg_vsstatus.spp := new_vsstatus.spp
reg_vsstatus.mxr := new_vsstatus.mxr
reg_vsstatus.sum := new_vsstatus.sum
reg_vsstatus.fs := formFS(new_vsstatus.fs)
reg_vsstatus.vs := formVS(new_vsstatus.vs)
}
when (decoded_addr(CSRs.vsip)) {
val new_vsip = ((read_hip & ~read_hideleg) | ((wdata << 1) & read_hideleg)).asTypeOf(new MIP())
reg_mip.vssip := new_vsip.vssip
}
when (decoded_addr(CSRs.vsatp)) {
val new_vsatp = wdata.asTypeOf(new PTBR())
val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U))
when (mode_ok) {
reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_|_).U
}
when (mode_ok || !reg_mstatus.v) {
reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0)
if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0)
}
}
when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) | ((wdata << 1) & read_hideleg) }
when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata }
when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) }
when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata }
when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask }
when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata }
when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) }
}
if (usingUser) {
when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata }
when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) }
}
if (nBreakpoints > 0) {
when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata }
for ((bp, i) <- reg_bp.zipWithIndex) {
when (i.U === reg_tselect && (!bp.control.dmode || reg_debug)) {
when (decoded_addr(CSRs.tdata2)) { bp.address := wdata }
when (decoded_addr(CSRs.tdata3)) {
if (coreParams.mcontextWidth > 0) {
bp.textra.mselect := wdata(bp.textra.mselectPos)
bp.textra.mvalue := wdata >> bp.textra.mvaluePos
}
if (coreParams.scontextWidth > 0) {
bp.textra.sselect := wdata(bp.textra.sselectPos)
bp.textra.svalue := wdata >> bp.textra.svaluePos
}
}
when (decoded_addr(CSRs.tdata1)) {
bp.control := wdata.asTypeOf(bp.control)
val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain
val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode
val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain
val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode
val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control)
val dMode = newBPC.dmode && reg_debug && (prevDMode || !prevChain)
bp.control.dmode := dMode
when (dMode || (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U }
bp.control.chain := newBPC.chain && !(prevChain || nextChain) && (dMode || !nextDMode)
}
}
}
}
reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }}
reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }}
if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) {
require(xLen % pmp.cfg.getWidth == 0)
when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) {
val newCfg = (wdata >> ((i * pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig())
pmp.cfg := newCfg
// disallow unreadable but writable PMPs
pmp.cfg.w := newCfg.w && newCfg.r
// can't select a=NA4 with coarse-grained PMPs
if (pmpGranularity.log2 > PMP.lgAlign)
pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR)
}
when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) {
pmp.addr := wdata
}
}
def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (decoded_addr(csr.id)) {
reg := (wdata & mask) | (reg & ~mask)
io.wen := true.B
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
writeCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
writeCustomCSR(io, csr, reg)
}
if (usingVector) {
when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata }
when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata }
when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata }
when (decoded_addr(CSRs.vcsr)) {
set_vs_dirty := true.B
reg_vxsat.get := wdata
reg_vxrm.get := wdata >> 1
}
}
}
def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = {
val mask = csr.mask.U(xLen.W)
when (io.set) {
reg := (io.sdata & mask) | (reg & ~mask)
}
}
for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) {
setCustomCSR(io, csr, reg)
}
for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) {
setCustomCSR(io, csr, reg)
}
io.vector.map { vio =>
when (vio.set_vconfig.valid) {
// user of CSRFile is responsible for set_vs_dirty in this case
assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax)
reg_vconfig.get := vio.set_vconfig.bits
}
when (vio.set_vstart.valid) {
set_vs_dirty := true.B
reg_vstart.get := vio.set_vstart.bits
}
vio.vstart := reg_vstart.get
vio.vconfig := reg_vconfig.get
vio.vxrm := reg_vxrm.get
when (reset.asBool) {
reg_vconfig.get.vl := 0.U
reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
reg_vconfig.get.vtype.vill := true.B
}
}
when(reset.asBool) {
reg_satp.mode := 0.U
reg_vsatp.mode := 0.U
reg_hgatp.mode := 0.U
}
if (!usingVM) {
reg_satp.mode := 0.U
reg_satp.ppn := 0.U
reg_satp.asid := 0.U
}
if (!usingHypervisor) {
reg_vsatp.mode := 0.U
reg_vsatp.ppn := 0.U
reg_vsatp.asid := 0.U
reg_hgatp.mode := 0.U
reg_hgatp.ppn := 0.U
reg_hgatp.asid := 0.U
}
if (!(asIdBits > 0)) {
reg_satp.asid := 0.U
reg_vsatp.asid := 0.U
}
if (!(vmIdBits > 0)) {
reg_hgatp.asid := 0.U
}
reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U)
if (nBreakpoints <= 1) reg_tselect := 0.U
for (bpc <- reg_bp map {_.control}) {
bpc.ttype := bpc.tType.U
bpc.maskmax := bpc.maskMax.U
bpc.reserved := 0.U
bpc.zero := 0.U
bpc.h := false.B
if (!usingSupervisor) bpc.s := false.B
if (!usingUser) bpc.u := false.B
if (!usingSupervisor && !usingUser) bpc.m := true.B
when (reset.asBool) {
bpc.action := 0.U
bpc.dmode := false.B
bpc.chain := false.B
bpc.r := false.B
bpc.w := false.B
bpc.x := false.B
}
}
for (bpx <- reg_bp map {_.textra}) {
if (coreParams.mcontextWidth == 0) bpx.mselect := false.B
if (coreParams.scontextWidth == 0) bpx.sselect := false.B
}
for (bp <- reg_bp drop nBreakpoints)
bp := 0.U.asTypeOf(new BP())
for (pmp <- reg_pmp) {
pmp.cfg.res := 0.U
when (reset.asBool) { pmp.reset() }
}
for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {
t.exception := io.retire >= i.U && exception
t.valid := io.retire > i.U || t.exception
t.insn := insn
t.iaddr := io.pc
t.priv := Cat(reg_debug, reg_mstatus.prv)
t.cause := cause
t.interrupt := cause(xLen-1)
t.tval := io.tval
t.wdata.foreach(_ := DontCare)
}
def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = {
val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
// MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI
val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4)
val priority = nonstandard ++ standard
val masks = masksIn.reverse
val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_||_)
val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U))))
(any, which)
}
def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = {
(Mux(cmd(1), rdata, 0.U) | wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U)
}
def legalizePrivilege(priv: UInt): UInt =
if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv)
else if (usingUser) Fill(2, priv(0))
else PRV.M.U
def trimPrivilege(priv: UInt): UInt =
if (usingSupervisor) priv
else legalizePrivilege(priv)
def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = {
if (xLen == 32) {
val hi = lo + CSRs.mcycleh - CSRs.mcycle
when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) }
when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) }
} else {
when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) }
}
}
def formEPC(x: UInt) = ~(~x | (if (usingCompressed) 1.U else 3.U))
def readEPC(x: UInt) = ~(~x | Mux(reg_misa('c' - 'a'), 1.U, 3.U))
def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) | 2).U, 2.U)
def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_|_)
def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR)
def formVS(vs: UInt) = if (usingVector) vs else 0.U
}
| module Rocket_1( // @[RocketCore.scala:153:7]
input clock, // @[RocketCore.scala:153:7]
input reset, // @[RocketCore.scala:153:7]
input [2:0] io_hartid, // @[RocketCore.scala:134:14]
input io_interrupts_debug, // @[RocketCore.scala:134:14]
input io_interrupts_mtip, // @[RocketCore.scala:134:14]
input io_interrupts_msip, // @[RocketCore.scala:134:14]
input io_interrupts_meip, // @[RocketCore.scala:134:14]
input io_interrupts_seip, // @[RocketCore.scala:134:14]
output io_imem_might_request, // @[RocketCore.scala:134:14]
output io_imem_req_valid, // @[RocketCore.scala:134:14]
output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14]
output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14]
output io_imem_sfence_valid, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14]
output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14]
output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14]
output io_imem_resp_ready, // @[RocketCore.scala:134:14]
input io_imem_resp_valid, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14]
input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14]
input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14]
input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14]
input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14]
input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14]
input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14]
input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14]
input io_imem_gpa_valid, // @[RocketCore.scala:134:14]
input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14]
input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14]
output io_imem_btb_update_valid, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14]
output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14]
output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14]
output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14]
output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14]
output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14]
output io_imem_bht_update_valid, // @[RocketCore.scala:134:14]
output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14]
output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14]
output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14]
output io_imem_flush_icache, // @[RocketCore.scala:134:14]
input [39:0] io_imem_npc, // @[RocketCore.scala:134:14]
input io_imem_perf_acquire, // @[RocketCore.scala:134:14]
input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14]
output io_imem_progress, // @[RocketCore.scala:134:14]
input io_dmem_req_ready, // @[RocketCore.scala:134:14]
output io_dmem_req_valid, // @[RocketCore.scala:134:14]
output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14]
output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14]
output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14]
output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14]
output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14]
output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14]
output io_dmem_s1_kill, // @[RocketCore.scala:134:14]
output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14]
input io_dmem_s2_nack, // @[RocketCore.scala:134:14]
input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14]
input io_dmem_s2_uncached, // @[RocketCore.scala:134:14]
input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14]
input io_dmem_resp_valid, // @[RocketCore.scala:134:14]
input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14]
input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14]
input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14]
input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14]
input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14]
input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14]
input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14]
input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14]
input io_dmem_replay_next, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14]
input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14]
input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14]
input io_dmem_ordered, // @[RocketCore.scala:134:14]
input io_dmem_store_pending, // @[RocketCore.scala:134:14]
input io_dmem_perf_acquire, // @[RocketCore.scala:134:14]
input io_dmem_perf_release, // @[RocketCore.scala:134:14]
input io_dmem_perf_grant, // @[RocketCore.scala:134:14]
input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14]
input io_dmem_perf_blocked, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14]
input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14]
input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14]
output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14]
output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14]
output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14]
output io_ptw_sfence_valid, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14]
output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14]
output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14]
output io_ptw_status_debug, // @[RocketCore.scala:134:14]
output io_ptw_status_cease, // @[RocketCore.scala:134:14]
output io_ptw_status_wfi, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14]
output io_ptw_status_dv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14]
output io_ptw_status_v, // @[RocketCore.scala:134:14]
output io_ptw_status_sd, // @[RocketCore.scala:134:14]
output io_ptw_status_mpv, // @[RocketCore.scala:134:14]
output io_ptw_status_gva, // @[RocketCore.scala:134:14]
output io_ptw_status_tsr, // @[RocketCore.scala:134:14]
output io_ptw_status_tw, // @[RocketCore.scala:134:14]
output io_ptw_status_tvm, // @[RocketCore.scala:134:14]
output io_ptw_status_mxr, // @[RocketCore.scala:134:14]
output io_ptw_status_sum, // @[RocketCore.scala:134:14]
output io_ptw_status_mprv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14]
output io_ptw_status_spp, // @[RocketCore.scala:134:14]
output io_ptw_status_mpie, // @[RocketCore.scala:134:14]
output io_ptw_status_spie, // @[RocketCore.scala:134:14]
output io_ptw_status_mie, // @[RocketCore.scala:134:14]
output io_ptw_status_sie, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14]
output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_v, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14]
output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14]
output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14]
output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14]
output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14]
output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14]
output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14]
output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14]
input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14]
input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14]
output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14]
output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14]
input io_ptw_clock_enabled, // @[RocketCore.scala:134:14]
output [2:0] io_fpu_hartid, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_time, // @[RocketCore.scala:134:14]
output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14]
output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14]
input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14]
input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14]
input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14]
input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14]
output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14]
output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14]
output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14]
output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14]
output io_fpu_valid, // @[RocketCore.scala:134:14]
input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14]
input io_fpu_nack_mem, // @[RocketCore.scala:134:14]
input io_fpu_illegal_rm, // @[RocketCore.scala:134:14]
output io_fpu_killx, // @[RocketCore.scala:134:14]
output io_fpu_killm, // @[RocketCore.scala:134:14]
input io_fpu_dec_ldst, // @[RocketCore.scala:134:14]
input io_fpu_dec_wen, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren1, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren2, // @[RocketCore.scala:134:14]
input io_fpu_dec_ren3, // @[RocketCore.scala:134:14]
input io_fpu_dec_swap12, // @[RocketCore.scala:134:14]
input io_fpu_dec_swap23, // @[RocketCore.scala:134:14]
input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14]
input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14]
input io_fpu_dec_fromint, // @[RocketCore.scala:134:14]
input io_fpu_dec_toint, // @[RocketCore.scala:134:14]
input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14]
input io_fpu_dec_fma, // @[RocketCore.scala:134:14]
input io_fpu_dec_div, // @[RocketCore.scala:134:14]
input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14]
input io_fpu_dec_wflags, // @[RocketCore.scala:134:14]
input io_fpu_dec_vec, // @[RocketCore.scala:134:14]
input io_fpu_sboard_set, // @[RocketCore.scala:134:14]
input io_fpu_sboard_clr, // @[RocketCore.scala:134:14]
input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14]
output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14]
output io_trace_insns_0_valid, // @[RocketCore.scala:134:14]
output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14]
output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14]
output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14]
output io_trace_insns_0_exception, // @[RocketCore.scala:134:14]
output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14]
output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14]
output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14]
output [63:0] io_trace_time, // @[RocketCore.scala:134:14]
output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14]
output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14]
output io_wfi // @[RocketCore.scala:134:14]
);
wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25]
wire id_ctrl_fence; // @[RocketCore.scala:321:21]
wire id_ctrl_rocc; // @[RocketCore.scala:321:21]
wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7]
wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7]
wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22]
wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22]
wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22]
wire _div_io_req_ready; // @[RocketCore.scala:511:19]
wire _div_io_resp_valid; // @[RocketCore.scala:511:19]
wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19]
wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19]
wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19]
wire _alu_io_cmp_out; // @[RocketCore.scala:504:19]
wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19]
wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19]
wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_if; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19]
wire _bpu_io_debug_st; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19]
wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19]
wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19]
wire _csr_io_csr_stall; // @[RocketCore.scala:341:19]
wire _csr_io_eret; // @[RocketCore.scala:341:19]
wire _csr_io_singleStep; // @[RocketCore.scala:341:19]
wire _csr_io_status_debug; // @[RocketCore.scala:341:19]
wire _csr_io_status_cease; // @[RocketCore.scala:341:19]
wire _csr_io_status_wfi; // @[RocketCore.scala:341:19]
wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19]
wire _csr_io_status_dv; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19]
wire _csr_io_status_v; // @[RocketCore.scala:341:19]
wire _csr_io_status_sd; // @[RocketCore.scala:341:19]
wire _csr_io_status_mpv; // @[RocketCore.scala:341:19]
wire _csr_io_status_gva; // @[RocketCore.scala:341:19]
wire _csr_io_status_tsr; // @[RocketCore.scala:341:19]
wire _csr_io_status_tw; // @[RocketCore.scala:341:19]
wire _csr_io_status_tvm; // @[RocketCore.scala:341:19]
wire _csr_io_status_mxr; // @[RocketCore.scala:341:19]
wire _csr_io_status_sum; // @[RocketCore.scala:341:19]
wire _csr_io_status_mprv; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19]
wire _csr_io_status_spp; // @[RocketCore.scala:341:19]
wire _csr_io_status_mpie; // @[RocketCore.scala:341:19]
wire _csr_io_status_spie; // @[RocketCore.scala:341:19]
wire _csr_io_status_mie; // @[RocketCore.scala:341:19]
wire _csr_io_status_sie; // @[RocketCore.scala:341:19]
wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19]
wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19]
wire _csr_io_interrupt; // @[RocketCore.scala:341:19]
wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19]
wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19]
wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19]
wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19]
wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19]
wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19]
wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19]
wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19]
wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19]
wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19]
wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19]
wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20]
wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20]
wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20]
wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20]
wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20]
wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20]
wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20]
wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20]
wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20]
wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20]
wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20]
wire [2:0] io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7]
wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7]
wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7]
wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7]
wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7]
wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7]
wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7]
wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7]
wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7]
wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7]
wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7]
wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7]
wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7]
wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7]
wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7]
wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7]
wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7]
wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7]
wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7]
wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7]
wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7]
wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7]
wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7]
wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7]
wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7]
wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7]
wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7]
wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7]
wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7]
wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7]
wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7]
wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7]
wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7]
wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7]
wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7]
wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7]
wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7]
wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7]
wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7]
wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7]
wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7]
wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7]
wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7]
wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7]
wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7]
wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7]
wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7]
wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7]
wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7]
wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7]
wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31]
wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28]
wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7]
wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7]
wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29]
wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23]
wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73]
wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55]
wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43]
wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36]
wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23]
wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41]
wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34]
wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26]
wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23]
wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45]
wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56]
wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31]
wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7]
wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7]
wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7]
wire io_cease = 1'h0; // @[RocketCore.scala:153:7]
wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7]
wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33]
wire hits_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2 = 1'h0; // @[Events.scala:13:25]
wire hits_3 = 1'h0; // @[Events.scala:13:25]
wire hits_4 = 1'h0; // @[Events.scala:13:25]
wire hits_5 = 1'h0; // @[Events.scala:13:25]
wire hits_6 = 1'h0; // @[Events.scala:13:25]
wire hits_7 = 1'h0; // @[Events.scala:13:25]
wire hits_8 = 1'h0; // @[Events.scala:13:25]
wire hits_9 = 1'h0; // @[Events.scala:13:25]
wire hits_10 = 1'h0; // @[Events.scala:13:25]
wire hits_11 = 1'h0; // @[Events.scala:13:25]
wire hits_12 = 1'h0; // @[Events.scala:13:25]
wire hits_13 = 1'h0; // @[Events.scala:13:25]
wire hits_14 = 1'h0; // @[Events.scala:13:25]
wire hits_15 = 1'h0; // @[Events.scala:13:25]
wire hits_16 = 1'h0; // @[Events.scala:13:25]
wire hits_17 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33]
wire hits_1_0 = 1'h0; // @[Events.scala:13:25]
wire hits_1_1 = 1'h0; // @[Events.scala:13:25]
wire hits_1_2 = 1'h0; // @[Events.scala:13:25]
wire hits_1_3 = 1'h0; // @[Events.scala:13:25]
wire hits_1_4 = 1'h0; // @[Events.scala:13:25]
wire hits_1_5 = 1'h0; // @[Events.scala:13:25]
wire hits_1_6 = 1'h0; // @[Events.scala:13:25]
wire hits_1_7 = 1'h0; // @[Events.scala:13:25]
wire hits_1_8 = 1'h0; // @[Events.scala:13:25]
wire hits_1_9 = 1'h0; // @[Events.scala:13:25]
wire hits_1_10 = 1'h0; // @[Events.scala:13:25]
wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33]
wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33]
wire hits_2_0 = 1'h0; // @[Events.scala:13:25]
wire hits_2_1 = 1'h0; // @[Events.scala:13:25]
wire hits_2_2 = 1'h0; // @[Events.scala:13:25]
wire hits_2_3 = 1'h0; // @[Events.scala:13:25]
wire hits_2_4 = 1'h0; // @[Events.scala:13:25]
wire hits_2_5 = 1'h0; // @[Events.scala:13:25]
wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21]
wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33]
wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33]
wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43]
wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36]
wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23]
wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41]
wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34]
wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120]
wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19]
wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23]
wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23]
wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22]
wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34]
wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87]
wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100]
wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46]
wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17]
wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86]
wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37]
wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55]
wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46]
wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42]
wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45]
wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42]
wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23]
wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24]
wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26]
wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43]
wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36]
wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23]
wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40]
wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33]
wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23]
wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25]
wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42]
wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35]
wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24]
wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24]
wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41]
wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34]
wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24]
wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22]
wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22]
wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22]
wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17]
wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17]
wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17]
wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52]
wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36]
wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42]
wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36]
wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83]
wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54]
wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87]
wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98]
wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19]
wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39]
wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15]
wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46]
wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5]
wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52]
wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32]
wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38]
wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35]
wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31]
wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28]
wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7]
wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7]
wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7]
wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116]
wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110]
wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28]
wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28]
wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7]
wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25]
wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7]
wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7]
wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28]
wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7]
wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28]
wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28]
wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7]
wire take_pc_mem_wb; // @[RocketCore.scala:307:35]
wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8]
wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35]
wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40]
wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7]
wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45]
wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7]
wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45]
wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7]
wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7]
wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7]
wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77]
wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33]
wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7]
wire mem_cfi; // @[RocketCore.scala:625:50]
wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8]
wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45]
wire mem_wrong_npc; // @[RocketCore.scala:621:8]
wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59]
wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41]
wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8]
wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30]
wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31]
wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37]
wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56]
wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68]
wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63]
wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7]
wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78]
wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62]
wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70]
wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14]
wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54]
wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41]
wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46]
wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31]
wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70]
wire ctrl_killx; // @[RocketCore.scala:602:48]
wire killm_common; // @[RocketCore.scala:700:68]
wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59]
wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53]
wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48]
wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48]
wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48]
wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7]
wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7]
wire io_imem_req_valid_0; // @[RocketCore.scala:153:7]
wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7]
wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7]
wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7]
wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7]
wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7]
wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7]
wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7]
wire io_imem_might_request_0; // @[RocketCore.scala:153:7]
wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7]
wire io_imem_progress_0; // @[RocketCore.scala:153:7]
wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7]
wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7]
wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7]
wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7]
wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7]
wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7]
wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7]
wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7]
wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7]
wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_v_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7]
wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7]
wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7]
wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7]
wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7]
wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7]
wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7]
wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7]
wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7]
wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7]
wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7]
wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7]
wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7]
wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7]
wire io_fpu_valid_0; // @[RocketCore.scala:153:7]
wire io_fpu_killx_0; // @[RocketCore.scala:153:7]
wire io_fpu_killm_0; // @[RocketCore.scala:153:7]
wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7]
wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7]
wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7]
wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7]
wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7]
wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7]
wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7]
wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7]
wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7]
wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7]
wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7]
wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7]
wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7]
wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7]
wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7]
wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7]
wire io_wfi_0; // @[RocketCore.scala:153:7]
reg id_reg_pause; // @[RocketCore.scala:161:25]
reg imem_might_request_reg; // @[RocketCore.scala:162:35]
assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35]
reg ex_ctrl_legal; // @[RocketCore.scala:243:20]
reg ex_ctrl_fp; // @[RocketCore.scala:243:20]
reg ex_ctrl_rocc; // @[RocketCore.scala:243:20]
reg ex_ctrl_branch; // @[RocketCore.scala:243:20]
reg ex_ctrl_jal; // @[RocketCore.scala:243:20]
reg ex_ctrl_jalr; // @[RocketCore.scala:243:20]
reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20]
reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20]
reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20]
reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20]
reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20]
reg ex_ctrl_mem; // @[RocketCore.scala:243:20]
wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29]
reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20]
assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20]
reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20]
reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20]
reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20]
reg ex_ctrl_wfd; // @[RocketCore.scala:243:20]
reg ex_ctrl_mul; // @[RocketCore.scala:243:20]
reg ex_ctrl_div; // @[RocketCore.scala:243:20]
reg ex_ctrl_wxd; // @[RocketCore.scala:243:20]
reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20]
reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20]
reg ex_ctrl_fence; // @[RocketCore.scala:243:20]
reg ex_ctrl_amo; // @[RocketCore.scala:243:20]
reg ex_ctrl_dp; // @[RocketCore.scala:243:20]
reg mem_ctrl_legal; // @[RocketCore.scala:244:21]
reg mem_ctrl_fp; // @[RocketCore.scala:244:21]
reg mem_ctrl_rocc; // @[RocketCore.scala:244:21]
reg mem_ctrl_branch; // @[RocketCore.scala:244:21]
assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21]
reg mem_ctrl_jal; // @[RocketCore.scala:244:21]
reg mem_ctrl_jalr; // @[RocketCore.scala:244:21]
reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21]
reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21]
reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21]
reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21]
reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21]
reg mem_ctrl_mem; // @[RocketCore.scala:244:21]
reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21]
reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21]
reg mem_ctrl_wfd; // @[RocketCore.scala:244:21]
reg mem_ctrl_mul; // @[RocketCore.scala:244:21]
reg mem_ctrl_div; // @[RocketCore.scala:244:21]
reg mem_ctrl_wxd; // @[RocketCore.scala:244:21]
reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21]
reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21]
reg mem_ctrl_fence; // @[RocketCore.scala:244:21]
reg mem_ctrl_amo; // @[RocketCore.scala:244:21]
reg mem_ctrl_dp; // @[RocketCore.scala:244:21]
reg mem_ctrl_vec; // @[RocketCore.scala:244:21]
reg wb_ctrl_legal; // @[RocketCore.scala:245:20]
reg wb_ctrl_fp; // @[RocketCore.scala:245:20]
reg wb_ctrl_rocc; // @[RocketCore.scala:245:20]
reg wb_ctrl_branch; // @[RocketCore.scala:245:20]
reg wb_ctrl_jal; // @[RocketCore.scala:245:20]
reg wb_ctrl_jalr; // @[RocketCore.scala:245:20]
reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20]
reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20]
reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20]
reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20]
reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20]
reg wb_ctrl_mem; // @[RocketCore.scala:245:20]
reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20]
reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20]
reg wb_ctrl_wfd; // @[RocketCore.scala:245:20]
reg wb_ctrl_mul; // @[RocketCore.scala:245:20]
reg wb_ctrl_div; // @[RocketCore.scala:245:20]
reg wb_ctrl_wxd; // @[RocketCore.scala:245:20]
reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20]
reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20]
reg wb_ctrl_fence; // @[RocketCore.scala:245:20]
reg wb_ctrl_amo; // @[RocketCore.scala:245:20]
reg wb_ctrl_dp; // @[RocketCore.scala:245:20]
reg wb_ctrl_vec; // @[RocketCore.scala:245:20]
reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35]
reg ex_reg_valid; // @[RocketCore.scala:248:35]
reg ex_reg_rvc; // @[RocketCore.scala:249:35]
reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35]
reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35]
reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35]
reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35]
reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35]
reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35]
reg ex_reg_xcpt; // @[RocketCore.scala:251:35]
reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35]
reg ex_reg_load_use; // @[RocketCore.scala:253:35]
reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35]
wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50]
reg ex_reg_replay; // @[RocketCore.scala:255:26]
reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22]
wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24]
reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28]
assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28]
reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24]
reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28]
reg ex_reg_wphit_0; // @[RocketCore.scala:261:36]
reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36]
reg mem_reg_valid; // @[RocketCore.scala:265:36]
reg mem_reg_rvc; // @[RocketCore.scala:266:36]
reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36]
wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85]
reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36]
reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36]
reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36]
reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36]
assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36]
assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36]
assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36]
reg mem_reg_xcpt; // @[RocketCore.scala:268:36]
reg mem_reg_replay; // @[RocketCore.scala:269:36]
reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36]
reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36]
reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36]
wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41]
reg mem_reg_load; // @[RocketCore.scala:273:36]
reg mem_reg_store; // @[RocketCore.scala:274:36]
reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36]
reg mem_reg_sfence; // @[RocketCore.scala:276:27]
reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23]
wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34]
reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25]
reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29]
reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30]
reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29]
reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26]
wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111]
reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24]
reg mem_br_taken; // @[RocketCore.scala:284:25]
assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25]
wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49]
wire take_pc_mem; // @[RocketCore.scala:285:25]
reg mem_reg_wphit_0; // @[RocketCore.scala:286:35]
reg wb_reg_valid; // @[RocketCore.scala:288:35]
reg wb_reg_xcpt; // @[RocketCore.scala:289:35]
reg wb_reg_replay; // @[RocketCore.scala:290:35]
reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35]
reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35]
reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35]
reg wb_reg_sfence; // @[RocketCore.scala:294:26]
reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22]
reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28]
reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29]
reg wb_reg_hfence_v; // @[RocketCore.scala:298:28]
assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28]
reg wb_reg_hfence_g; // @[RocketCore.scala:299:28]
assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28]
reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24]
wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48]
reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28]
reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25]
assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25]
wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21]
reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23]
assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23]
wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53]
wire take_pc_wb; // @[RocketCore.scala:304:24]
reg wb_reg_wphit_0; // @[RocketCore.scala:305:35]
assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35]
assign take_pc_mem_wb = take_pc_wb | take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35]
assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35]
wire id_ctrl_decoder_0; // @[Decode.scala:50:77]
wire id_ctrl_decoder_1; // @[Decode.scala:50:77]
wire id_ctrl_decoder_2; // @[Decode.scala:50:77]
wire id_ctrl_decoder_3; // @[Decode.scala:50:77]
wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18]
wire id_ctrl_decoder_4; // @[Decode.scala:50:77]
wire id_ctrl_decoder_5; // @[Decode.scala:50:77]
wire id_ctrl_decoder_6; // @[Decode.scala:50:77]
wire id_ctrl_decoder_7; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77]
wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77]
wire id_ctrl_decoder_11; // @[Decode.scala:50:77]
wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77]
wire id_ctrl_decoder_13; // @[Decode.scala:50:77]
wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77]
wire id_ctrl_decoder_15; // @[Decode.scala:50:77]
wire id_ctrl_decoder_16; // @[Decode.scala:50:77]
wire id_ctrl_decoder_17; // @[Decode.scala:50:77]
wire id_ctrl_decoder_18; // @[Decode.scala:50:77]
wire id_ctrl_decoder_19; // @[Decode.scala:50:77]
wire id_ctrl_decoder_20; // @[Decode.scala:50:77]
wire id_ctrl_decoder_21; // @[Decode.scala:50:77]
wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77]
wire id_ctrl_decoder_23; // @[Decode.scala:50:77]
wire id_ctrl_decoder_24; // @[Decode.scala:50:77]
wire id_ctrl_decoder_25; // @[Decode.scala:50:77]
wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64]
wire id_ctrl_decoder_26; // @[Decode.scala:50:77]
wire id_ctrl_legal; // @[RocketCore.scala:321:21]
wire id_ctrl_fp; // @[RocketCore.scala:321:21]
wire id_ctrl_branch; // @[RocketCore.scala:321:21]
wire id_ctrl_jal; // @[RocketCore.scala:321:21]
wire id_ctrl_jalr; // @[RocketCore.scala:321:21]
wire id_ctrl_rxs2; // @[RocketCore.scala:321:21]
wire id_ctrl_rxs1; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21]
wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21]
wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21]
wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21]
wire id_ctrl_mem; // @[RocketCore.scala:321:21]
wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs1; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs2; // @[RocketCore.scala:321:21]
wire id_ctrl_rfs3; // @[RocketCore.scala:321:21]
wire id_ctrl_wfd; // @[RocketCore.scala:321:21]
wire id_ctrl_mul; // @[RocketCore.scala:321:21]
wire id_ctrl_div; // @[RocketCore.scala:321:21]
wire id_ctrl_wxd; // @[RocketCore.scala:321:21]
wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21]
wire id_ctrl_fence_i; // @[RocketCore.scala:321:21]
wire id_ctrl_amo; // @[RocketCore.scala:321:21]
wire id_ctrl_dp; // @[RocketCore.scala:321:21]
wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22]
wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53]
wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53]
wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53]
wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53]
wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53]
wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53]
wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53]
wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53]
wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53]
wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53]
wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53]
wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53]
wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53]
wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53]
wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53]
wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53]
wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53]
wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53]
wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53]
wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53]
wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53]
wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53]
wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53]
wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53]
wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53]
wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53]
wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19]
wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19]
wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19]
wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19]
wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19]
wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19]
wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19]
wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19]
wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19]
wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19]
wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19]
wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19]
wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19]
wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19]
wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19]
wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19]
wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19]
wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}]
wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19]
wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19]
wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19]
wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19]
wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19]
wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19]
wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19]
wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19]
wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19]
wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19]
wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19]
wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19]
wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19]
wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19]
wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19]
wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}]
wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}]
wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19]
assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19]
wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19]
wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19]
wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19]
wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19]
wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19]
wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19]
wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19]
wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19]
wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19]
wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = |_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36]
wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36]
wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36]
wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36]
wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36]
wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36]
wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36]
wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36]
wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31]
wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31]
wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31]
wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31]
wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31]
wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31]
wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23]
assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23]
assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23]
assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23]
assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23]
assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23]
assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23]
assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23]
assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23]
assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23]
assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23]
assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23]
assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23]
assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23]
assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23]
assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23]
assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23]
assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23]
assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23]
assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23]
assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23]
assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23]
assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23]
assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23]
assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23]
assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23]
assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21]
assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23]
assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21]
wire [4:0] id_raddr3; // @[RocketCore.scala:326:72]
wire [4:0] id_raddr2; // @[RocketCore.scala:326:72]
wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44]
wire [4:0] id_raddr1; // @[RocketCore.scala:326:72]
wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44]
wire [4:0] id_waddr; // @[RocketCore.scala:326:72]
wire _id_load_use_T_1; // @[RocketCore.scala:1001:51]
wire id_load_use; // @[RocketCore.scala:332:25]
reg id_reg_fence; // @[RocketCore.scala:333:29]
wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26]
wire _id_rs_T = ~(|id_raddr1); // @[RocketCore.scala:326:72, :1326:41]
wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}]
wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26]
wire _id_rs_T_5 = ~(|id_raddr2); // @[RocketCore.scala:326:72, :1326:41]
wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}]
wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104]
wire ctrl_killd; // @[RocketCore.scala:338:24]
wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44]
wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18]
wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41]
wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65]
wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39]
wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37]
wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}]
wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39]
wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37]
wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62]
wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57]
wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39]
wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52]
wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37]
wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}]
wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28]
wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53]
wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35]
wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35]
wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}]
wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47]
wire _id_csr_en_T; // @[package.scala:16:47]
assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47]
wire _id_csr_ren_T; // @[package.scala:16:47]
assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47]
wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47]
wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47]
wire _id_csr_en_T_3 = _id_csr_en_T | _id_csr_en_T_1; // @[package.scala:16:47, :81:59]
wire id_csr_en = _id_csr_en_T_3 | _id_csr_en_T_2; // @[package.scala:16:47, :81:59]
wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36]
wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47]
wire _id_csr_ren_T_2 = _id_csr_ren_T | _id_csr_ren_T_1; // @[package.scala:16:47, :81:59]
wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81]
wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59]
wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35]
wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61]
wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}]
wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54]
wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59]
wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}]
wire id_csr_flush = id_system_insn | _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}]
wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100]
wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100]
wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100]
wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100]
wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 | _id_set_vconfig_T_3; // @[package.scala:81:59]
wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 | _id_set_vconfig_T_5; // @[package.scala:81:59]
wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25]
wire _id_illegal_insn_T_1 = id_ctrl_mul | id_ctrl_div; // @[RocketCore.scala:321:21, :382:18]
wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55]
wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}]
wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}]
wire _id_illegal_insn_T_5 = _id_illegal_insn_T | _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34]
wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38]
wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}]
wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}]
wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 | _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17]
wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal | _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}]
wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}]
wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 | _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16]
wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88]
wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37]
wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}]
wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}]
wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 | _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16]
wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51]
wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46]
wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}]
wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}]
wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 | _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30]
wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61]
wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39]
wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39]
wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 | _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18]
wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52]
wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}]
wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal | _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}]
wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59]
wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 | _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15]
wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5]
wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50]
wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}]
wire id_illegal_insn = _id_illegal_insn_T_38 | _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31]
wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22]
wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}]
wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}]
wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59]
wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}]
wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7]
wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}]
wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}]
wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 | _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51]
wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113]
wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29]
wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29]
wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33]
wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33]
wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52]
wire id_fence_next = id_ctrl_fence | _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}]
wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21]
wire id_mem_busy = _id_mem_busy_T | io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}]
wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35]
wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}]
wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20]
wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 | _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20]
wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53]
wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53]
assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53]
wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37]
assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37]
wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37]
assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37]
wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 | _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}]
wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103]
wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33]
wire _id_do_fence_T_5 = _id_do_fence_T_4 | id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}]
wire _id_do_fence_T_6 = id_ctrl_mem | id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97]
wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}]
wire _id_do_fence_T_8 = _id_do_fence_T_5 | _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}]
wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}]
wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17]
wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34]
wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16]
wire id_xcpt = _csr_io_interrupt | _bpu_io_debug_if | _bpu_io_xcpt_if | _ibuf_io_inst_0_bits_xcpt0_pf_inst | _ibuf_io_inst_0_bits_xcpt0_gf_inst | _ibuf_io_inst_0_bits_xcpt0_ae_inst | _ibuf_io_inst_0_bits_xcpt1_pf_inst | _ibuf_io_inst_0_bits_xcpt1_gf_inst | _ibuf_io_inst_0_bits_xcpt1_ae_inst | id_virtual_insn | id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}]
wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70]
wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29]
wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}]
wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31]
wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}]
wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29]
wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}]
wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31]
wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19]
wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20]
wire _bypass_sources_T; // @[RocketCore.scala:459:20]
assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20]
wire bypass_sources_3_1; // @[RocketCore.scala:460:20]
assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20]
wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39]
assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39]
wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39]
wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}]
wire _id_bypass_src_T = ~(|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41]
wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}]
wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82]
wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82]
wire _data_hazard_ex_T; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70]
wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90]
wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}]
wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82]
wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82]
wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82]
wire _data_hazard_mem_T; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72]
wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92]
wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}]
wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}]
wire _id_bypass_src_T_4 = ~(|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41]
wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}]
wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82]
wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82]
wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70]
wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90]
wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}]
wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82]
wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82]
wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82]
assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82]
wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72]
wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92]
wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}]
wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}]
reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29]
reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29]
reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26]
reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26]
reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26]
reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26]
wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}]
wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}]
wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}]
wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69]
assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76]
assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14]
wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24]
wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}]
wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}]
wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86]
wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}]
wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69]
wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76]
wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24]
wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14]
wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24]
wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24]
assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24]
wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40]
assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40]
wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42]
assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42]
wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24]
assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24]
wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22]
assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22]
wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44]
wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}]
wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26]
wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26]
assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26]
wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23]
assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23]
wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25]
assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25]
wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24]
assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24]
wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41]
wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}]
wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26]
wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43]
wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}]
wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65]
wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}]
wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _ex_imm_b11_T_2 = _ex_imm_b11_T | _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}]
wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23]
wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39]
wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37]
wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39]
wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23]
wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23]
assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23]
wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41]
assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41]
wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39]
wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37]
wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}]
wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18]
wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18]
wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T | _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}]
wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62]
wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}]
wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24]
wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24]
assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24]
wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22]
assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22]
wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 | _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}]
wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57]
wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39]
wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52]
wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}]
wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19]
wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19]
wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22]
wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37]
wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}]
wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17]
wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17]
wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8]
wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}]
wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34]
wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47]
wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}]
wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79]
wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}]
wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54]
wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48]
wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24]
wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48]
wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24]
wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48]
wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54]
wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24]
wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48]
wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66]
wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}]
wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}]
wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35]
wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35]
wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19]
wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24]
wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53]
wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19]
wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48]
wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48]
wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48]
wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24]
wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36]
wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19]
wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20]
wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}]
wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}]
wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18]
wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14]
wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28]
wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}]
wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}]
wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22]
wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40]
wire _ex_reg_flush_pipe_T = id_ctrl_fence_i | id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42]
wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47]
wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 | _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59]
wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 | _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59]
wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75]
wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95]
wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}]
wire _ex_reg_mem_size_T_4 = |id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41]
wire _ex_reg_mem_size_T_5 = |id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41]
wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}]
wire _do_bypass_T = id_bypass_src_0_0 | id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48]
wire _do_bypass_T_1 = _do_bypass_T | id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48]
wire do_bypass = _do_bypass_T_1 | id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48]
wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70]
wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70]
wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70]
wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26]
wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26]
wire _do_bypass_T_2 = id_bypass_src_1_0 | id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48]
wire _do_bypass_T_3 = _do_bypass_T_2 | id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48]
wire do_bypass_1 = _do_bypass_T_3 | id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48]
wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70]
wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70]
wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70]
wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26]
wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26]
wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62]
wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}]
wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31]
wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32]
wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14]
wire _ex_pc_valid_T = ex_reg_valid | ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34]
wire ex_pc_valid = _ex_pc_valid_T | ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}]
wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39]
wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}]
wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45]
wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}]
wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45]
wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}]
wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 | _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42]
wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63]
wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43]
wire _replay_ex_T = replay_ex_structural | replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75]
wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}]
wire replay_ex = ex_reg_replay | _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}]
wire _ctrl_killx_T = take_pc_mem_wb | replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35]
wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51]
assign ctrl_killx = _ctrl_killx_T | _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}]
assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48]
wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40]
wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40]
assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40]
wire _mem_reg_load_T_3; // @[package.scala:16:47]
assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47]
wire _mem_reg_store_T_3; // @[Consts.scala:90:66]
assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40]
wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47]
wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69]
wire ex_slow_bypass = _ex_slow_bypass_T | _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}]
wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64]
wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96]
wire _ex_sfence_T_3 = _ex_sfence_T_1 | _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}]
wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129]
wire _ex_sfence_T_5 = _ex_sfence_T_3 | _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}]
wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}]
wire ex_xcpt = ex_reg_xcpt_interrupt | ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14]
wire _mem_pc_valid_T = mem_reg_valid | mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36]
wire mem_pc_valid = _mem_pc_valid_T | mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}]
wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25]
wire _mem_br_target_T_1; // @[RocketCore.scala:616:25]
assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25]
wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40]
assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40]
wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44]
wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44]
wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41]
wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41]
wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65]
wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65]
wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39]
wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37]
wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39]
wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37]
wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39]
wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37]
wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39]
wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37]
wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}]
wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18]
wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62]
wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62]
wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57]
wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57]
wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39]
wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39]
wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52]
wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52]
wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37]
wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37]
wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}]
wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}]
wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}]
wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18]
wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8]
wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}]
wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}]
wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}]
wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18]
wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8]
wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}]
wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8]
wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53]
wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53]
wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8]
wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41]
wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41]
wire _mem_npc_T = mem_ctrl_jalr | mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36]
wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17]
wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _mem_npc_msb_T_2 = _mem_npc_msb_T | _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46]
wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54]
wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8]
wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}]
wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}]
wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129]
wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}]
wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30]
wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid | io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31]
wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62]
wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 | _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}]
assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8]
assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8]
wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}]
wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66]
wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}]
wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73]
wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}]
wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27]
wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59]
wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}]
wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}]
wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}]
wire _mem_cfi_T = mem_ctrl_branch | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33]
assign mem_cfi = _mem_cfi_T | mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}]
assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50]
wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}]
wire mem_cfi_taken = _mem_cfi_taken_T_1 | mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}]
wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}]
wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}]
wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35]
wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}]
wire _take_pc_mem_T_2 = mem_wrong_npc | mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71]
assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}]
assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49]
wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20]
wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21]
wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}]
wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19]
wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14]
wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29]
wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}]
wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _mem_reg_load_T; // @[package.scala:16:47]
assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47]
wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _mem_reg_load_T_1; // @[package.scala:16:47]
assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _mem_reg_load_T_2; // @[package.scala:16:47]
assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47]
wire _mem_reg_load_T_4 = _mem_reg_load_T | _mem_reg_load_T_1; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_5 = _mem_reg_load_T_4 | _mem_reg_load_T_2; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_6 = _mem_reg_load_T_5 | _mem_reg_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _mem_reg_load_T_7; // @[package.scala:16:47]
assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47]
wire _mem_reg_store_T_5; // @[package.scala:16:47]
assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47]
wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _mem_reg_load_T_8; // @[package.scala:16:47]
assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47]
wire _mem_reg_store_T_6; // @[package.scala:16:47]
assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47]
wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _mem_reg_load_T_9; // @[package.scala:16:47]
assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47]
wire _mem_reg_store_T_7; // @[package.scala:16:47]
assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47]
wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _mem_reg_load_T_10; // @[package.scala:16:47]
assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47]
wire _mem_reg_store_T_8; // @[package.scala:16:47]
assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47]
wire _mem_reg_load_T_11 = _mem_reg_load_T_7 | _mem_reg_load_T_8; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_12 = _mem_reg_load_T_11 | _mem_reg_load_T_9; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_13 = _mem_reg_load_T_12 | _mem_reg_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _mem_reg_load_T_14; // @[package.scala:16:47]
assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47]
wire _mem_reg_store_T_12; // @[package.scala:16:47]
assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47]
wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _mem_reg_load_T_15; // @[package.scala:16:47]
assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47]
wire _mem_reg_store_T_13; // @[package.scala:16:47]
assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47]
wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _mem_reg_load_T_16; // @[package.scala:16:47]
assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47]
wire _mem_reg_store_T_14; // @[package.scala:16:47]
assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47]
wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _mem_reg_load_T_17; // @[package.scala:16:47]
assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47]
wire _mem_reg_store_T_15; // @[package.scala:16:47]
assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47]
wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _mem_reg_load_T_18; // @[package.scala:16:47]
assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47]
wire _mem_reg_store_T_16; // @[package.scala:16:47]
assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47]
wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47]
assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47]
wire _mem_reg_load_T_19 = _mem_reg_load_T_14 | _mem_reg_load_T_15; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_20 = _mem_reg_load_T_19 | _mem_reg_load_T_16; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_21 = _mem_reg_load_T_20 | _mem_reg_load_T_17; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_22 = _mem_reg_load_T_21 | _mem_reg_load_T_18; // @[package.scala:16:47, :81:59]
wire _mem_reg_load_T_23 = _mem_reg_load_T_13 | _mem_reg_load_T_22; // @[package.scala:81:59]
wire _mem_reg_load_T_24 = _mem_reg_load_T_6 | _mem_reg_load_T_23; // @[package.scala:81:59]
wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33]
wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20]
wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20]
wire _mem_reg_store_T_2 = _mem_reg_store_T | _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}]
wire _mem_reg_store_T_4 = _mem_reg_store_T_2 | _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}]
wire _mem_reg_store_T_9 = _mem_reg_store_T_5 | _mem_reg_store_T_6; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_10 = _mem_reg_store_T_9 | _mem_reg_store_T_7; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_11 = _mem_reg_store_T_10 | _mem_reg_store_T_8; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_17 = _mem_reg_store_T_12 | _mem_reg_store_T_13; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_18 = _mem_reg_store_T_17 | _mem_reg_store_T_14; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_19 = _mem_reg_store_T_18 | _mem_reg_store_T_15; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_20 = _mem_reg_store_T_19 | _mem_reg_store_T_16; // @[package.scala:16:47, :81:59]
wire _mem_reg_store_T_21 = _mem_reg_store_T_11 | _mem_reg_store_T_20; // @[package.scala:81:59]
wire _mem_reg_store_T_22 = _mem_reg_store_T_4 | _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34]
wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21]
wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21]
wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19]
wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69]
wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}]
wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32]
wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32]
wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19]
wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69]
wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32]
wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19]
wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69]
wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}]
wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}]
wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}]
wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}]
wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38]
wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75]
wire mem_breakpoint = _mem_breakpoint_T | _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}]
wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44]
wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82]
wire mem_debug_breakpoint = _mem_debug_breakpoint_T | _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}]
wire mem_ldst_xcpt = mem_debug_breakpoint | mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}]
wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70]
wire _T_74 = mem_reg_xcpt_interrupt | mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29]
wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20]
wire mem_xcpt = _T_74 | _T_75 | mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}]
wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70]
wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}]
wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36]
wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}]
wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36]
wire _replay_mem_T = dcache_kill_mem | mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37]
wire _replay_mem_T_1 = _replay_mem_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}]
wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}]
wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}]
wire _killm_common_T = dcache_kill_mem | take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38]
wire _killm_common_T_1 = _killm_common_T | mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}]
wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71]
assign killm_common = _killm_common_T_1 | _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}]
assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68]
wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35]
reg div_io_kill_REG; // @[RocketCore.scala:701:41]
wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}]
wire _ctrl_killm_T = killm_common | mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14]
wire _ctrl_killm_T_1 = _ctrl_killm_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}]
wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}]
wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19]
wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34]
wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}]
wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30]
wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14]
wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}]
wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24]
wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}]
wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25]
wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}]
wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}]
wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}]
wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41]
wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41]
wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19]
wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}]
wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34]
wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34]
wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34]
wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34]
wire wb_xcpt = wb_reg_xcpt | _T_100 | _T_102 | _T_108 | _T_110 | _T_112 | _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}]
wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70]
wire _wb_pc_valid_T = wb_reg_valid | wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34]
wire wb_pc_valid = _wb_pc_valid_T | wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}]
wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29]
wire _wb_set_sboard_T = wb_ctrl_div | wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35]
wire _wb_set_sboard_T_1 = _wb_set_sboard_T | wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}]
wire wb_set_sboard = _wb_set_sboard_T_1 | wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}]
wire replay_wb_common = io_dmem_s2_nack_0 | wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42]
wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}]
wire _replay_wb_T = replay_wb_common | replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36]
wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}]
wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}]
wire _take_pc_wb_T = replay_wb | wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14]
wire _take_pc_wb_T_1 = _take_pc_wb_T | _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}]
assign _take_pc_wb_T_2 = _take_pc_wb_T_1 | wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}]
assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53]
wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45]
wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45]
wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}]
assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46]
assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46]
wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44]
wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42]
wire [63:0] ll_wdata; // @[RocketCore.scala:779:26]
wire [4:0] ll_waddr; // @[RocketCore.scala:780:26]
wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35]
wire ll_wen; // @[RocketCore.scala:781:24]
wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26]
wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26]
assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25]
assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14]
assign ll_wen = _T_143 | _ll_wen_T; // @[Decoupled.scala:51:35]
wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34]
wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}]
wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14]
wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}]
wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25]
wire rf_wen = wb_wen | ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23]
wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21]
wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28]
wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38]
wire _rf_wdata_T_2 = |wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34]
wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21]
wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21]
wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21]
wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31]
wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28]
wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25]
assign id_rs_0 = rf_wen & (|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}]
wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25]
assign id_rs_1 = rf_wen & (|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}]
wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66]
wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}]
wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91]
wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}]
wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119]
wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}]
wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59]
wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}]
wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}]
wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29]
wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41]
wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38]
assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}]
wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24]
wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47]
wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47]
wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47]
wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47]
wire _tval_any_addr_T_3; // @[package.scala:16:47]
assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47]
wire _htval_valid_imem_T; // @[RocketCore.scala:853:56]
assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47]
wire _tval_any_addr_T_4 = _tval_any_addr_T | _tval_any_addr_T_1; // @[package.scala:16:47, :81:59]
wire _tval_any_addr_T_5 = _tval_any_addr_T_4 | _tval_any_addr_T_2; // @[package.scala:16:47, :81:59]
wire _tval_any_addr_T_6 = _tval_any_addr_T_5 | _tval_any_addr_T_3; // @[package.scala:16:47, :81:59]
wire tval_any_addr = tval_dmem_addr | _tval_any_addr_T_6; // @[package.scala:81:59]
wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32]
wire _tval_valid_T = tval_any_addr | tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46]
wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14]
wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43]
wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80]
wire _csr_io_gva_T_2 = _csr_io_gva_T | _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}]
wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14]
wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17]
wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46]
wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54]
wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16]
wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16]
wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8]
wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}]
wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25]
wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29]
wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14]
wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110]
wire _htval_valid_dmem_T_5 = |_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}]
wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}]
wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}]
wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51]
wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}]
wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32]
wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35]
wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}]
wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20]
assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18]
wire _hazard_targets_T = |id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41]
wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}]
wire _hazard_targets_T_1 = |id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41]
wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}]
wire _hazard_targets_T_2 = |id_waddr; // @[RocketCore.scala:326:72, :971:55]
wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}]
reg [31:0] _r; // @[RocketCore.scala:1305:29]
wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35]
wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}]
wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27]
wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27]
wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58]
wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40]
wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35]
wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70]
wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}]
wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80]
wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35]
wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27]
wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 | _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}]
wire id_sboard_hazard = _id_sboard_hazard_T_21 | _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}]
wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58]
wire _ex_cannot_bypass_T = |ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38]
wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T | ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}]
wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 | ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}]
wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 | ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}]
wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 | ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}]
wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 | ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}]
wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 | ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}]
wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}]
wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27]
wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27]
wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70]
wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70]
assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70]
wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90]
assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90]
wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27]
wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 | _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 | _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50]
wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38]
wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90]
wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27]
wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 | _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 | _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 | _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50]
wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54]
wire _id_ex_hazard_T_1 = _id_ex_hazard_T | fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}]
wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}]
wire _mem_cannot_bypass_T = |mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40]
wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66]
wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T | _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}]
wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 | mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}]
wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 | mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}]
wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 | mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}]
wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 | mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}]
wire mem_cannot_bypass = _mem_cannot_bypass_T_6 | mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}]
wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27]
wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27]
wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72]
wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72]
assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72]
wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92]
assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92]
wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27]
wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 | _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 | _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50]
wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39]
wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92]
wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27]
wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 | _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 | _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 | _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50]
wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57]
wire _id_mem_hazard_T_1 = _id_mem_hazard_T | fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}]
wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}]
wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32]
assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}]
assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51]
wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20]
wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20]
wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19]
wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 | _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19]
wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27]
wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27]
wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70]
wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70]
assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70]
wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90]
assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90]
wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27]
wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 | _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}]
wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 | _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}]
wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50]
wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38]
wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90]
wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27]
wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 | _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 | _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}]
wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 | _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}]
wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50]
wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54]
wire _id_wb_hazard_T_1 = _id_wb_hazard_T | fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}]
wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}]
reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29]
wire _id_stall_fpu_T = wb_dcache_miss | wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36]
wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}]
wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 | io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}]
wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}]
wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17]
wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r | _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49]
wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39]
wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}]
wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58]
wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49]
wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}]
wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 | _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17]
wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58]
wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}]
wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49]
wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}]
wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 | io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17]
wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29]
wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29]
wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35]
wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35]
wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 | _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}]
wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 | _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}]
wire id_stall_fpu = _id_stall_fpu_T_33 | _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}]
reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22]
wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16]
wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}]
wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63]
wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}]
wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked | io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95]
wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 | io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}]
wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}]
wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16]
wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}]
reg rocc_blocked; // @[RocketCore.scala:1028:25]
wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14]
wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}]
wire _rocc_blocked_T_3 = io_rocc_cmd_valid | rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72]
wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}]
wire _ctrl_stalld_T = id_ex_hazard | id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18]
wire _ctrl_stalld_T_1 = _ctrl_stalld_T | id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}]
wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 | id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50]
wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}]
wire _ctrl_stalld_T_4 = ex_reg_valid | mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40]
wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 | wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}]
wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}]
wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 | _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23]
wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59]
wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45]
wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}]
wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 | _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42]
wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62]
wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50]
wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 | _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16]
wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17]
wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 | _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17]
wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18]
wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 | _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18]
wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65]
wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}]
wire _ctrl_stalld_T_23 = _div_io_req_ready | _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}]
wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}]
wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 | _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}]
wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}]
wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 | _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17]
wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96]
wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 | id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15]
wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 | _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17]
wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 | id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22]
wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18]
wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17]
wire _ctrl_killd_T_1 = _ctrl_killd_T | _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}]
wire _ctrl_killd_T_2 = _ctrl_killd_T_1 | take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}]
wire _ctrl_killd_T_3 = _ctrl_killd_T_2 | ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}]
assign _ctrl_killd_T_4 = _ctrl_killd_T_3 | _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}]
assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104]
assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35]
assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35]
wire _io_imem_req_bits_pc_T = wb_xcpt | _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14]
wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8]
assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8]
assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8]
wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40]
wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62]
assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}]
assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59]
wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid | mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43]
wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61]
wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T | _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61]
wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}]
wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47]
wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}]
reg io_imem_progress_REG; // @[RocketCore.scala:1059:30]
assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30]
assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40]
assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40]
assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45]
assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45]
assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45]
assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45]
assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28]
wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28]
wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48]
wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}]
wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}]
wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81]
wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 | mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}]
assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}]
assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77]
wire _GEN_70 = mem_ctrl_jal | mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23]
wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23]
assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23]
wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22]
assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22]
wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53]
wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}]
wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}]
wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64]
wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}]
wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}]
wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8]
assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8]
assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8]
assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34]
wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74]
wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}]
wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69]
assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}]
wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35]
wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}]
assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}]
assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33]
wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48]
assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}]
assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45]
wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19]
assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}]
assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31]
assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41]
assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41]
assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23]
assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59]
assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59]
assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41]
assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41]
wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26]
assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25]
wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75]
wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}]
assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}]
assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30]
wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17]
wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}]
wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21]
wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34]
wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T | _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}]
wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46]
wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54]
wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}]
wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}]
wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16]
assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}]
assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8]
assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31]
assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37]
wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T | _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 | _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 | _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 | _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 | _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 | _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 | _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 | _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 | _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 | _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59]
wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 | _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59]
wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 | _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59]
wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31]
wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60]
wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84]
wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}]
assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 | _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}]
assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56]
assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63]
assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63]
wire _io_dmem_s1_kill_T = killm_common | mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14]
wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T | fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}]
assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}]
assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68]
wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55]
wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73]
assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}]
assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70]
wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56]
assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}]
assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53]
wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48]
wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48]
wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48]
wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48]
assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48]
assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48]
assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48]
wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28]
wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}]
wire _unpause_T_2 = _unpause_T_1 | _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}]
wire _unpause_T_3 = _unpause_T_2 | io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}]
wire unpause = _unpause_T_3 | take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}]
reg icache_blocked_REG; // @[RocketCore.scala:1183:55]
wire _icache_blocked_T = io_imem_resp_valid_0 | icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}]
wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}]
wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52]
wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15]
wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37]
wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42]
wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42]
wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31]
wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31]
wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31]
wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31]
wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31]
wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31]
wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31]
wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31]
wire [63:0] _GEN_71 = {61'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28]
assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28]
wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28]
assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28]
assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41]
wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55]
assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}]
assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52]
wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48]
wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38]
wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}]
assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}]
assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15]
wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40]
assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}]
assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37]
assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42]
assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42]
reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46]
reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38]
assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38]
assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42]
assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42]
reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46]
reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38]
assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38] |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_25( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
| module TLBuffer_a29d64s10k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [9:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_8 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_in_a_bits_corrupt),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a29d64s10k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_user_amba_prot_bufferable (auto_in_a_bits_user_amba_prot_bufferable),
.io_enq_bits_user_amba_prot_modifiable (auto_in_a_bits_user_amba_prot_modifiable),
.io_enq_bits_user_amba_prot_readalloc (auto_in_a_bits_user_amba_prot_readalloc),
.io_enq_bits_user_amba_prot_writealloc (auto_in_a_bits_user_amba_prot_writealloc),
.io_enq_bits_user_amba_prot_privileged (auto_in_a_bits_user_amba_prot_privileged),
.io_enq_bits_user_amba_prot_secure (auto_in_a_bits_user_amba_prot_secure),
.io_enq_bits_user_amba_prot_fetch (auto_in_a_bits_user_amba_prot_fetch),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_enq_bits_corrupt (auto_in_a_bits_corrupt),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_user_amba_prot_bufferable (auto_out_a_bits_user_amba_prot_bufferable),
.io_deq_bits_user_amba_prot_modifiable (auto_out_a_bits_user_amba_prot_modifiable),
.io_deq_bits_user_amba_prot_readalloc (auto_out_a_bits_user_amba_prot_readalloc),
.io_deq_bits_user_amba_prot_writealloc (auto_out_a_bits_user_amba_prot_writealloc),
.io_deq_bits_user_amba_prot_privileged (auto_out_a_bits_user_amba_prot_privileged),
.io_deq_bits_user_amba_prot_secure (auto_out_a_bits_user_amba_prot_secure),
.io_deq_bits_user_amba_prot_fetch (auto_out_a_bits_user_amba_prot_fetch),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a29d64s10k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_382( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_126 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File FIFOFixer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.util.property
class TLFIFOFixer(policy: TLFIFOFixer.Policy = TLFIFOFixer.all)(implicit p: Parameters) extends LazyModule
{
private def fifoMap(seq: Seq[TLSlaveParameters]) = {
val (flatManagers, keepManagers) = seq.partition(policy)
// We need to be careful if one flatManager and one keepManager share an existing domain
// Erring on the side of caution, we will also flatten the keepManager in this case
val flatDomains = Set(flatManagers.flatMap(_.fifoId):_*) // => ID 0
val keepDomains = Set(keepManagers.flatMap(_.fifoId):_*) -- flatDomains // => IDs compacted
// Calculate what the FIFO domains look like after the fixer is applied
val flatMap = flatDomains.map { x => (x, 0) }.toMap
val keepMap = keepDomains.scanLeft((-1,0)) { case ((_,s),x) => (x, s+1) }.toMap
val map = flatMap ++ keepMap
val fixMap = seq.map { m => m.fifoId match {
case None => if (policy(m)) Some(0) else None
case Some(id) => Some(map(id)) // also flattens some who did not ask
} }
// Compress the FIFO domain space of those we are combining
val reMap = flatDomains.scanLeft((-1,-1)) { case ((_,s),x) => (x, s+1) }.toMap
val splatMap = seq.map { m => m.fifoId match {
case None => None
case Some(id) => reMap.lift(id)
} }
(fixMap, splatMap)
}
val node = new AdapterNode(TLImp)(
{ cp => cp },
{ mp =>
val (fixMap, _) = fifoMap(mp.managers)
mp.v1copy(managers = (fixMap zip mp.managers) map { case (id, m) => m.v1copy(fifoId = id) })
}) with TLFormatNode {
override def circuitIdentity = edges.in.map(_.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).size).sum == 0
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val (fixMap, splatMap) = fifoMap(edgeOut.manager.managers)
// Do we need to serialize the request to this manager?
val a_notFIFO = edgeIn.manager.fastProperty(in.a.bits.address, _.fifoId != Some(0), (b:Boolean) => b.B)
// Compact the IDs of the cases we serialize
val compacted = ((fixMap zip splatMap) zip edgeOut.manager.managers) flatMap {
case ((f, s), m) => if (f == Some(0)) Some(m.v1copy(fifoId = s)) else None
}
val sinks = if (compacted.exists(_.supportsAcquireB)) edgeOut.manager.endSinkId else 0
val a_id = if (compacted.isEmpty) 0.U else
edgeOut.manager.v1copy(managers = compacted, endSinkId = sinks).findFifoIdFast(in.a.bits.address)
val a_noDomain = a_id === 0.U
if (false) {
println(s"FIFOFixer for: ${edgeIn.client.clients.map(_.name).mkString(", ")}")
println(s"make FIFO: ${edgeIn.manager.managers.filter(_.fifoId==Some(0)).map(_.name).mkString(", ")}")
println(s"not FIFO: ${edgeIn.manager.managers.filter(_.fifoId!=Some(0)).map(_.name).mkString(", ")}")
println(s"domains: ${compacted.groupBy(_.name).mapValues(_.map(_.fifoId))}")
println("")
}
// Count beats
val a_first = edgeIn.first(in.a)
val d_first = edgeOut.first(out.d) && out.d.bits.opcode =/= TLMessages.ReleaseAck
// Keep one bit for each source recording if there is an outstanding request that must be made FIFO
// Sources unused in the stall signal calculation should be pruned by DCE
val flight = RegInit(VecInit(Seq.fill(edgeIn.client.endSourceId) { false.B }))
when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
val stalls = edgeIn.client.clients.filter(c => c.requestFifo && c.sourceId.size > 1).map { c =>
val a_sel = c.sourceId.contains(in.a.bits.source)
val id = RegEnable(a_id, in.a.fire && a_sel && !a_notFIFO)
val track = flight.slice(c.sourceId.start, c.sourceId.end)
a_sel && a_first && track.reduce(_ || _) && (a_noDomain || id =/= a_id)
}
val stall = stalls.foldLeft(false.B)(_||_)
out.a <> in.a
in.d <> out.d
out.a.valid := in.a.valid && (a_notFIFO || !stall)
in.a.ready := out.a.ready && (a_notFIFO || !stall)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> out.b
out.c <> in .c
out.e <> in .e
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
//Functional cover properties
property.cover(in.a.valid && stall, "COVER FIFOFIXER STALL", "Cover: Stall occured for a valid transaction")
val SourceIdFIFOed = RegInit(0.U(edgeIn.client.endSourceId.W))
val SourceIdSet = WireDefault(0.U(edgeIn.client.endSourceId.W))
val SourceIdClear = WireDefault(0.U(edgeIn.client.endSourceId.W))
when (a_first && in.a.fire && !a_notFIFO) {
SourceIdSet := UIntToOH(in.a.bits.source)
}
when (d_first && in.d.fire) {
SourceIdClear := UIntToOH(in.d.bits.source)
}
SourceIdFIFOed := SourceIdFIFOed | SourceIdSet
val allIDs_FIFOed = SourceIdFIFOed===Fill(SourceIdFIFOed.getWidth, 1.U)
property.cover(allIDs_FIFOed, "COVER all sources", "Cover: FIFOFIXER covers all Source IDs")
//property.cover(flight.reduce(_ && _), "COVER full", "Cover: FIFO is full with all Source IDs")
property.cover(!(flight.reduce(_ || _)), "COVER empty", "Cover: FIFO is empty")
property.cover(SourceIdSet > 0.U, "COVER at least one push", "Cover: At least one Source ID is pushed")
property.cover(SourceIdClear > 0.U, "COVER at least one pop", "Cover: At least one Source ID is popped")
}
}
}
object TLFIFOFixer
{
// Which slaves should have their FIFOness combined?
// NOTE: this transformation is still only applied for masters with requestFifo
type Policy = TLSlaveParameters => Boolean
import RegionType._
val all: Policy = m => true
val allFIFO: Policy = m => m.fifoId.isDefined
val allVolatile: Policy = m => m.regionType <= VOLATILE
def apply(policy: Policy = all)(implicit p: Parameters): TLNode =
{
val fixer = LazyModule(new TLFIFOFixer(policy))
fixer.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File SystemBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{
BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams
}
import freechips.rocketchip.tilelink.{
TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode,
TLFIFOFixer, TLTempNode
}
import freechips.rocketchip.util.Location
case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
policy: TLArbiter.Policy = TLArbiter.roundRobin,
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
val sbus = LazyModule(new SystemBus(this, loc.name))
sbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> sbus)
sbus
}
}
class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name)))
val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())
val outwardNode: TLOutwardNode = system_bus_xbar.node
def busView: TLEdge = system_bus_xbar.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module SystemBus_2( // @[ClockDomain.scala:14:9]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_system_bus_xbar_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_system_bus_xbar_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_system_bus_xbar_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_system_bus_xbar_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_system_bus_xbar_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_system_bus_xbar_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_system_bus_xbar_anon_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_system_bus_xbar_anon_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_system_bus_xbar_anon_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_system_bus_xbar_anon_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_system_bus_xbar_anon_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_system_bus_xbar_anon_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_system_bus_xbar_anon_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_system_bus_xbar_anon_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_system_bus_xbar_anon_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_system_bus_xbar_anon_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_system_bus_xbar_anon_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_system_bus_xbar_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_system_bus_xbar_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_system_bus_xbar_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_system_bus_xbar_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_system_bus_xbar_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_system_bus_xbar_anon_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_system_bus_xbar_anon_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_system_bus_xbar_anon_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25]
output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25]
input auto_csbus1_clock_groups_in_member_csbus1_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_csbus1_clock_groups_in_member_csbus1_0_reset // @[LazyModuleImp.scala:107:25]
);
wire fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire csbus1_clock_groups_auto_out_member_csbus1_0_reset; // @[ClockGroup.scala:53:9]
wire csbus1_clock_groups_auto_out_member_csbus1_0_clock; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0 = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_a_ready_0 = auto_system_bus_xbar_anon_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_b_valid_0 = auto_system_bus_xbar_anon_out_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_b_bits_opcode_0 = auto_system_bus_xbar_anon_out_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_system_bus_xbar_anon_out_b_bits_param_0 = auto_system_bus_xbar_anon_out_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_b_bits_size_0 = auto_system_bus_xbar_anon_out_b_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_b_bits_source_0 = auto_system_bus_xbar_anon_out_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_system_bus_xbar_anon_out_b_bits_address_0 = auto_system_bus_xbar_anon_out_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_system_bus_xbar_anon_out_b_bits_mask_0 = auto_system_bus_xbar_anon_out_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_system_bus_xbar_anon_out_b_bits_data_0 = auto_system_bus_xbar_anon_out_b_bits_data; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_b_bits_corrupt_0 = auto_system_bus_xbar_anon_out_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_c_ready_0 = auto_system_bus_xbar_anon_out_c_ready; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_d_valid_0 = auto_system_bus_xbar_anon_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_d_bits_opcode_0 = auto_system_bus_xbar_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_system_bus_xbar_anon_out_d_bits_param_0 = auto_system_bus_xbar_anon_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_d_bits_size_0 = auto_system_bus_xbar_anon_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_d_bits_source_0 = auto_system_bus_xbar_anon_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_d_bits_sink_0 = auto_system_bus_xbar_anon_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_d_bits_denied_0 = auto_system_bus_xbar_anon_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_system_bus_xbar_anon_out_d_bits_data_0 = auto_system_bus_xbar_anon_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_d_bits_corrupt_0 = auto_system_bus_xbar_anon_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_e_ready_0 = auto_system_bus_xbar_anon_out_e_ready; // @[ClockDomain.scala:14:9]
wire auto_csbus1_clock_groups_in_member_csbus1_0_clock_0 = auto_csbus1_clock_groups_in_member_csbus1_0_clock; // @[ClockDomain.scala:14:9]
wire auto_csbus1_clock_groups_in_member_csbus1_0_reset_0 = auto_csbus1_clock_groups_in_member_csbus1_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] fixer__allIDs_FIFOed_T = 3'h7; // @[FIFOFixer.scala:127:48]
wire [2:0] fixer__allIDs_FIFOed_T_1 = 3'h7; // @[FIFOFixer.scala:127:48]
wire [2:0] fixer__allIDs_FIFOed_T_2 = 3'h7; // @[FIFOFixer.scala:127:48]
wire [2:0] fixer__allIDs_FIFOed_T_3 = 3'h7; // @[FIFOFixer.scala:127:48]
wire fixer__a_id_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_1 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_1 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_3 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_4 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_3 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_4 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_14 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_6 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_7 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_6 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_7 = 1'h1; // @[FIFOFixer.scala:96:47]
wire fixer__a_id_T_19 = 1'h1; // @[Parameters.scala:137:59]
wire fixer__anonOut_a_valid_T_9 = 1'h1; // @[FIFOFixer.scala:95:50]
wire fixer__anonOut_a_valid_T_10 = 1'h1; // @[FIFOFixer.scala:95:47]
wire fixer__anonIn_a_ready_T_9 = 1'h1; // @[FIFOFixer.scala:96:50]
wire fixer__anonIn_a_ready_T_10 = 1'h1; // @[FIFOFixer.scala:96:47]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire csbus1_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire csbus1_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire csbus1_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixer__a_notFIFO_T_28 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_59 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_1 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_1_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_1_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_90 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_2 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_2_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_2_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__a_notFIFO_T_121 = 1'h0; // @[Mux.scala:30:73]
wire fixer_a_noDomain_3 = 1'h0; // @[FIFOFixer.scala:63:29]
wire fixer__flight_WIRE_3_0 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3_1 = 1'h0; // @[FIFOFixer.scala:79:35]
wire fixer__flight_WIRE_3_2 = 1'h0; // @[FIFOFixer.scala:79:35]
wire [32:0] fixer__a_id_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_12 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_13 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_17 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] fixer__a_id_T_18 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_valid_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_valid_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_valid_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire csbus1_clock_groups_auto_in_member_csbus1_0_clock = auto_csbus1_clock_groups_in_member_csbus1_0_clock_0; // @[ClockGroup.scala:53:9]
wire csbus1_clock_groups_auto_in_member_csbus1_0_reset = auto_csbus1_clock_groups_in_member_csbus1_0_reset_0; // @[ClockGroup.scala:53:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire csbus1_clock_groups_nodeIn_member_csbus1_0_clock = csbus1_clock_groups_auto_in_member_csbus1_0_clock; // @[ClockGroup.scala:53:9]
wire csbus1_clock_groups_nodeOut_member_csbus1_0_clock; // @[MixedNode.scala:542:17]
wire csbus1_clock_groups_nodeIn_member_csbus1_0_reset = csbus1_clock_groups_auto_in_member_csbus1_0_reset; // @[ClockGroup.scala:53:9]
wire csbus1_clock_groups_nodeOut_member_csbus1_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_csbus1_0_clock = csbus1_clock_groups_auto_out_member_csbus1_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_csbus1_0_reset = csbus1_clock_groups_auto_out_member_csbus1_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign csbus1_clock_groups_auto_out_member_csbus1_0_clock = csbus1_clock_groups_nodeOut_member_csbus1_0_clock; // @[ClockGroup.scala:53:9]
assign csbus1_clock_groups_auto_out_member_csbus1_0_reset = csbus1_clock_groups_nodeOut_member_csbus1_0_reset; // @[ClockGroup.scala:53:9]
assign csbus1_clock_groups_nodeOut_member_csbus1_0_clock = csbus1_clock_groups_nodeIn_member_csbus1_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign csbus1_clock_groups_nodeOut_member_csbus1_0_reset = csbus1_clock_groups_nodeIn_member_csbus1_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_csbus1_0_clock = clockGroup_auto_in_member_csbus1_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_csbus1_0_reset = clockGroup_auto_in_member_csbus1_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_csbus1_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_csbus1_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixer_x1_anonIn_2_a_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_a_ready = fixer_auto_anon_in_3_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_a_valid = fixer_auto_anon_in_3_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_2_a_bits_opcode = fixer_auto_anon_in_3_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_2_a_bits_param = fixer_auto_anon_in_3_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_2_a_bits_size = fixer_auto_anon_in_3_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_2_a_bits_source = fixer_auto_anon_in_3_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_2_a_bits_address = fixer_auto_anon_in_3_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_x1_anonIn_2_a_bits_mask = fixer_auto_anon_in_3_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_2_a_bits_data = fixer_auto_anon_in_3_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_a_bits_corrupt = fixer_auto_anon_in_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_b_ready = fixer_auto_anon_in_3_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_2_b_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_b_valid = fixer_auto_anon_in_3_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_2_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_3_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_2_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_param = fixer_auto_anon_in_3_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_2_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_3_auto_tl_out_b_bits_size = fixer_auto_anon_in_3_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonIn_2_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_b_bits_source = fixer_auto_anon_in_3_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonIn_2_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_3_auto_tl_out_b_bits_address = fixer_auto_anon_in_3_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_2_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_3_auto_tl_out_b_bits_mask = fixer_auto_anon_in_3_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_3_auto_tl_out_b_bits_data = fixer_auto_anon_in_3_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_c_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_c_ready = fixer_auto_anon_in_3_c_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_c_valid = fixer_auto_anon_in_3_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_2_c_bits_opcode = fixer_auto_anon_in_3_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_2_c_bits_param = fixer_auto_anon_in_3_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_2_c_bits_size = fixer_auto_anon_in_3_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_2_c_bits_source = fixer_auto_anon_in_3_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_2_c_bits_address = fixer_auto_anon_in_3_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_2_c_bits_data = fixer_auto_anon_in_3_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_c_bits_corrupt = fixer_auto_anon_in_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_d_ready = fixer_auto_anon_in_3_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_2_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_d_valid = fixer_auto_anon_in_3_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_2_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_3_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_2_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_param = fixer_auto_anon_in_3_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_2_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_3_auto_tl_out_d_bits_size = fixer_auto_anon_in_3_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonIn_2_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_auto_tl_out_d_bits_source = fixer_auto_anon_in_3_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_d_bits_sink = fixer_auto_anon_in_3_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_2_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_d_bits_denied = fixer_auto_anon_in_3_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_3_auto_tl_out_d_bits_data = fixer_auto_anon_in_3_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_2_e_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_e_ready = fixer_auto_anon_in_3_e_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_2_e_valid = fixer_auto_anon_in_3_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_2_e_bits_sink = fixer_auto_anon_in_3_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_a_ready = fixer_auto_anon_in_2_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_a_valid = fixer_auto_anon_in_2_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_a_bits_opcode = fixer_auto_anon_in_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_a_bits_param = fixer_auto_anon_in_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_1_a_bits_size = fixer_auto_anon_in_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_1_a_bits_source = fixer_auto_anon_in_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_1_a_bits_address = fixer_auto_anon_in_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_x1_anonIn_1_a_bits_mask = fixer_auto_anon_in_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_1_a_bits_data = fixer_auto_anon_in_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_a_bits_corrupt = fixer_auto_anon_in_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_b_ready = fixer_auto_anon_in_2_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_1_b_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_auto_tl_out_b_valid = fixer_auto_anon_in_2_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_2_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_1_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_param = fixer_auto_anon_in_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_2_auto_tl_out_b_bits_size = fixer_auto_anon_in_2_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonIn_1_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_b_bits_source = fixer_auto_anon_in_2_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonIn_1_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_2_auto_tl_out_b_bits_address = fixer_auto_anon_in_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_1_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_2_auto_tl_out_b_bits_mask = fixer_auto_anon_in_2_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_2_auto_tl_out_b_bits_data = fixer_auto_anon_in_2_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_c_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_c_ready = fixer_auto_anon_in_2_c_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_c_valid = fixer_auto_anon_in_2_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_c_bits_opcode = fixer_auto_anon_in_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_1_c_bits_param = fixer_auto_anon_in_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_1_c_bits_size = fixer_auto_anon_in_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_1_c_bits_source = fixer_auto_anon_in_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_1_c_bits_address = fixer_auto_anon_in_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_1_c_bits_data = fixer_auto_anon_in_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_c_bits_corrupt = fixer_auto_anon_in_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_d_ready = fixer_auto_anon_in_2_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_auto_tl_out_d_valid = fixer_auto_anon_in_2_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_param = fixer_auto_anon_in_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_2_auto_tl_out_d_bits_size = fixer_auto_anon_in_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_auto_tl_out_d_bits_source = fixer_auto_anon_in_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_d_bits_sink = fixer_auto_anon_in_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_auto_tl_out_d_bits_denied = fixer_auto_anon_in_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_2_auto_tl_out_d_bits_data = fixer_auto_anon_in_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_1_e_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_e_ready = fixer_auto_anon_in_2_e_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_1_e_valid = fixer_auto_anon_in_2_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_1_e_bits_sink = fixer_auto_anon_in_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_a_ready = fixer_auto_anon_in_1_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_valid = fixer_auto_anon_in_1_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_opcode = fixer_auto_anon_in_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_a_bits_param = fixer_auto_anon_in_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_a_bits_size = fixer_auto_anon_in_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_a_bits_source = fixer_auto_anon_in_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_a_bits_address = fixer_auto_anon_in_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_x1_anonIn_a_bits_mask = fixer_auto_anon_in_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_a_bits_data = fixer_auto_anon_in_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_a_bits_corrupt = fixer_auto_anon_in_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_b_ready = fixer_auto_anon_in_1_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_auto_tl_out_b_valid = fixer_auto_anon_in_1_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_1_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_param = fixer_auto_anon_in_1_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_1_auto_tl_out_b_bits_size = fixer_auto_anon_in_1_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_b_bits_source = fixer_auto_anon_in_1_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_1_auto_tl_out_b_bits_address = fixer_auto_anon_in_1_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_1_auto_tl_out_b_bits_mask = fixer_auto_anon_in_1_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_1_auto_tl_out_b_bits_data = fixer_auto_anon_in_1_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_c_ready = fixer_auto_anon_in_1_c_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_c_valid = fixer_auto_anon_in_1_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_c_bits_opcode = fixer_auto_anon_in_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_x1_anonIn_c_bits_param = fixer_auto_anon_in_1_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_x1_anonIn_c_bits_size = fixer_auto_anon_in_1_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_x1_anonIn_c_bits_source = fixer_auto_anon_in_1_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_x1_anonIn_c_bits_address = fixer_auto_anon_in_1_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_x1_anonIn_c_bits_data = fixer_auto_anon_in_1_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_c_bits_corrupt = fixer_auto_anon_in_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_d_ready = fixer_auto_anon_in_1_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_auto_tl_out_d_valid = fixer_auto_anon_in_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_param = fixer_auto_anon_in_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_1_auto_tl_out_d_bits_size = fixer_auto_anon_in_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_auto_tl_out_d_bits_source = fixer_auto_anon_in_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_d_bits_sink = fixer_auto_anon_in_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_auto_tl_out_d_bits_denied = fixer_auto_anon_in_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_1_auto_tl_out_d_bits_data = fixer_auto_anon_in_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_e_ready = fixer_auto_anon_in_1_e_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_x1_anonIn_e_valid = fixer_auto_anon_in_1_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire [2:0] fixer_x1_anonIn_e_bits_sink = fixer_auto_anon_in_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_ready = fixer_auto_anon_in_0_a_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_valid = fixer_auto_anon_in_0_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_a_bits_opcode = fixer_auto_anon_in_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_a_bits_param = fixer_auto_anon_in_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_anonIn_a_bits_size = fixer_auto_anon_in_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_auto_tl_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_anonIn_a_bits_source = fixer_auto_anon_in_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_anonIn_a_bits_address = fixer_auto_anon_in_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [7:0] fixer_anonIn_a_bits_mask = fixer_auto_anon_in_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_anonIn_a_bits_data = fixer_auto_anon_in_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_a_bits_corrupt = fixer_auto_anon_in_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_b_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_b_ready = fixer_auto_anon_in_0_b_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_b_valid = fixer_auto_anon_in_0_b_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_b_bits_opcode = fixer_auto_anon_in_0_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_param = fixer_auto_anon_in_0_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_b_bits_size = fixer_auto_anon_in_0_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_b_bits_source = fixer_auto_anon_in_0_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_auto_tl_out_b_bits_address = fixer_auto_anon_in_0_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_auto_tl_out_b_bits_mask = fixer_auto_anon_in_0_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_auto_tl_out_b_bits_data = fixer_auto_anon_in_0_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_b_bits_corrupt = fixer_auto_anon_in_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_c_ready = fixer_auto_anon_in_0_c_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_c_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_c_valid = fixer_auto_anon_in_0_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_c_bits_opcode = fixer_auto_anon_in_0_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_c_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_c_bits_param = fixer_auto_anon_in_0_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_auto_tl_out_c_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] fixer_anonIn_c_bits_size = fixer_auto_anon_in_0_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_auto_tl_out_c_bits_source; // @[LazyModuleImp.scala:138:7]
wire [1:0] fixer_anonIn_c_bits_source = fixer_auto_anon_in_0_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_auto_tl_out_c_bits_address; // @[LazyModuleImp.scala:138:7]
wire [31:0] fixer_anonIn_c_bits_address = fixer_auto_anon_in_0_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_auto_tl_out_c_bits_data; // @[LazyModuleImp.scala:138:7]
wire [63:0] fixer_anonIn_c_bits_data = fixer_auto_anon_in_0_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_c_bits_corrupt = fixer_auto_anon_in_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_d_ready = fixer_auto_anon_in_0_d_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] fixer_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_valid = fixer_auto_anon_in_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_opcode = fixer_auto_anon_in_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_param = fixer_auto_anon_in_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_auto_tl_out_d_bits_size = fixer_auto_anon_in_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_auto_tl_out_d_bits_source = fixer_auto_anon_in_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_auto_tl_out_d_bits_sink = fixer_auto_anon_in_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_bits_denied = fixer_auto_anon_in_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_auto_tl_out_d_bits_data = fixer_auto_anon_in_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_auto_tl_out_d_bits_corrupt = fixer_auto_anon_in_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_e_ready = fixer_auto_anon_in_0_e_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_auto_tl_out_e_valid; // @[LazyModuleImp.scala:138:7]
wire fixer_anonIn_e_valid = fixer_auto_anon_in_0_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[LazyModuleImp.scala:138:7]
wire [2:0] fixer_anonIn_e_bits_sink = fixer_auto_anon_in_0_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_a_ready = fixer_auto_anon_out_3_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_2_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_2_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_2_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_2_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_2_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_x1_anonOut_2_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_2_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_b_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_b_valid = fixer_auto_anon_out_3_b_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_2_b_bits_opcode = fixer_auto_anon_out_3_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_2_b_bits_param = fixer_auto_anon_out_3_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_2_b_bits_size = fixer_auto_anon_out_3_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_2_b_bits_source = fixer_auto_anon_out_3_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonOut_2_b_bits_address = fixer_auto_anon_out_3_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonOut_2_b_bits_mask = fixer_auto_anon_out_3_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_2_b_bits_data = fixer_auto_anon_out_3_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_b_bits_corrupt = fixer_auto_anon_out_3_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_c_ready = fixer_auto_anon_out_3_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_2_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_2_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_2_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_2_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_2_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_2_c_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_2_d_valid = fixer_auto_anon_out_3_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_2_d_bits_opcode = fixer_auto_anon_out_3_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_2_d_bits_param = fixer_auto_anon_out_3_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_2_d_bits_size = fixer_auto_anon_out_3_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_2_d_bits_source = fixer_auto_anon_out_3_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_2_d_bits_sink = fixer_auto_anon_out_3_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_d_bits_denied = fixer_auto_anon_out_3_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_2_d_bits_data = fixer_auto_anon_out_3_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_d_bits_corrupt = fixer_auto_anon_out_3_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_e_ready = fixer_auto_anon_out_3_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_2_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_2_e_bits_sink; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_a_ready = fixer_auto_anon_out_2_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_1_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_1_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_1_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_x1_anonOut_1_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_1_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_b_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_b_valid = fixer_auto_anon_out_2_b_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_1_b_bits_opcode = fixer_auto_anon_out_2_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_b_bits_param = fixer_auto_anon_out_2_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_1_b_bits_size = fixer_auto_anon_out_2_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_b_bits_source = fixer_auto_anon_out_2_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonOut_1_b_bits_address = fixer_auto_anon_out_2_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonOut_1_b_bits_mask = fixer_auto_anon_out_2_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_1_b_bits_data = fixer_auto_anon_out_2_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_b_bits_corrupt = fixer_auto_anon_out_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_c_ready = fixer_auto_anon_out_2_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_1_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_1_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_1_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_1_c_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_1_d_valid = fixer_auto_anon_out_2_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_1_d_bits_opcode = fixer_auto_anon_out_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_d_bits_param = fixer_auto_anon_out_2_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_1_d_bits_size = fixer_auto_anon_out_2_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_1_d_bits_source = fixer_auto_anon_out_2_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_1_d_bits_sink = fixer_auto_anon_out_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_d_bits_denied = fixer_auto_anon_out_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_1_d_bits_data = fixer_auto_anon_out_2_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_d_bits_corrupt = fixer_auto_anon_out_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_e_ready = fixer_auto_anon_out_2_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_1_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_1_e_bits_sink; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_ready = fixer_auto_anon_out_1_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_b_valid = fixer_auto_anon_out_1_b_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_b_bits_opcode = fixer_auto_anon_out_1_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_b_bits_param = fixer_auto_anon_out_1_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_b_bits_size = fixer_auto_anon_out_1_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_b_bits_source = fixer_auto_anon_out_1_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_x1_anonOut_b_bits_address = fixer_auto_anon_out_1_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_x1_anonOut_b_bits_mask = fixer_auto_anon_out_1_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_b_bits_data = fixer_auto_anon_out_1_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_b_bits_corrupt = fixer_auto_anon_out_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_c_ready = fixer_auto_anon_out_1_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_x1_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_x1_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_x1_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] fixer_x1_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_x1_anonOut_d_valid = fixer_auto_anon_out_1_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_opcode = fixer_auto_anon_out_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_d_bits_param = fixer_auto_anon_out_1_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_x1_anonOut_d_bits_size = fixer_auto_anon_out_1_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_x1_anonOut_d_bits_source = fixer_auto_anon_out_1_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_x1_anonOut_d_bits_sink = fixer_auto_anon_out_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_denied = fixer_auto_anon_out_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_x1_anonOut_d_bits_data = fixer_auto_anon_out_1_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_d_bits_corrupt = fixer_auto_anon_out_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_e_ready = fixer_auto_anon_out_1_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_x1_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_x1_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_ready = fixer_auto_anon_out_0_a_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] fixer_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_b_valid = fixer_auto_anon_out_0_b_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_b_bits_opcode = fixer_auto_anon_out_0_b_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_b_bits_param = fixer_auto_anon_out_0_b_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_b_bits_size = fixer_auto_anon_out_0_b_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_b_bits_source = fixer_auto_anon_out_0_b_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_anonOut_b_bits_address = fixer_auto_anon_out_0_b_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_anonOut_b_bits_mask = fixer_auto_anon_out_0_b_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_b_bits_data = fixer_auto_anon_out_0_b_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_b_bits_corrupt = fixer_auto_anon_out_0_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_c_ready = fixer_auto_anon_out_0_c_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] fixer_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] fixer_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] fixer_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] fixer_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire fixer_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire fixer_anonOut_d_valid = fixer_auto_anon_out_0_d_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_opcode = fixer_auto_anon_out_0_d_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_param = fixer_auto_anon_out_0_d_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_anonOut_d_bits_size = fixer_auto_anon_out_0_d_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_anonOut_d_bits_source = fixer_auto_anon_out_0_d_bits_source; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_anonOut_d_bits_sink = fixer_auto_anon_out_0_d_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_denied = fixer_auto_anon_out_0_d_bits_denied; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_anonOut_d_bits_data = fixer_auto_anon_out_0_d_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_d_bits_corrupt = fixer_auto_anon_out_0_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_e_ready = fixer_auto_anon_out_0_e_ready; // @[FIFOFixer.scala:50:9]
wire fixer_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] fixer_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] fixer_auto_anon_out_3_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_3_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_3_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_3_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_3_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_b_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_3_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_3_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_3_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_3_c_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_3_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_3_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_2_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_b_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_2_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_2_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_2_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_2_c_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_2_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_b_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_1_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_1_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_1_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_1_c_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_1_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] fixer_auto_anon_out_0_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_a_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_a_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_b_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] fixer_auto_anon_out_0_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] fixer_auto_anon_out_0_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] fixer_auto_anon_out_0_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] fixer_auto_anon_out_0_c_bits_data; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_c_valid; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_d_ready; // @[FIFOFixer.scala:50:9]
wire [2:0] fixer_auto_anon_out_0_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer_auto_anon_out_0_e_valid; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_2 = fixer_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_0_a_valid = fixer_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_opcode = fixer_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_param = fixer_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_size = fixer_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_source = fixer_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_address = fixer_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_mask = fixer_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_data = fixer_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_a_bits_corrupt = fixer_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_b_ready = fixer_anonOut_b_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_b_valid = fixer_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_opcode = fixer_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_param = fixer_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_size = fixer_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_source = fixer_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_address = fixer_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_mask = fixer_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_data = fixer_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_b_bits_corrupt = fixer_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_c_ready = fixer_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_0_c_valid = fixer_anonOut_c_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_opcode = fixer_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_param = fixer_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_size = fixer_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_source = fixer_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_address = fixer_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_data = fixer_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_c_bits_corrupt = fixer_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_d_ready = fixer_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonIn_d_valid = fixer_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_opcode = fixer_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_param = fixer_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_size = fixer_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_source = fixer_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_sink = fixer_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_denied = fixer_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_data = fixer_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_d_bits_corrupt = fixer_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonIn_e_ready = fixer_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_0_e_valid = fixer_anonOut_e_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_0_e_bits_sink = fixer_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_5 = fixer_x1_anonOut_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_1_a_valid = fixer_x1_anonOut_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_opcode = fixer_x1_anonOut_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_param = fixer_x1_anonOut_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_size = fixer_x1_anonOut_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_source = fixer_x1_anonOut_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_address = fixer_x1_anonOut_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_mask = fixer_x1_anonOut_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_data = fixer_x1_anonOut_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_a_bits_corrupt = fixer_x1_anonOut_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_b_ready = fixer_x1_anonOut_b_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_b_valid = fixer_x1_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_opcode = fixer_x1_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_param = fixer_x1_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_size = fixer_x1_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_source = fixer_x1_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_address = fixer_x1_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_mask = fixer_x1_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_data = fixer_x1_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_b_bits_corrupt = fixer_x1_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_c_ready = fixer_x1_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_1_c_valid = fixer_x1_anonOut_c_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_opcode = fixer_x1_anonOut_c_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_param = fixer_x1_anonOut_c_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_size = fixer_x1_anonOut_c_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_source = fixer_x1_anonOut_c_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_address = fixer_x1_anonOut_c_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_data = fixer_x1_anonOut_c_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_c_bits_corrupt = fixer_x1_anonOut_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_d_ready = fixer_x1_anonOut_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_d_valid = fixer_x1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_opcode = fixer_x1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_param = fixer_x1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_size = fixer_x1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_source = fixer_x1_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_sink = fixer_x1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_denied = fixer_x1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_data = fixer_x1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_d_bits_corrupt = fixer_x1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_e_ready = fixer_x1_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_1_e_valid = fixer_x1_anonOut_e_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_1_e_bits_sink = fixer_x1_anonOut_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_8 = fixer_x1_anonOut_1_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_2_a_valid = fixer_x1_anonOut_1_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_opcode = fixer_x1_anonOut_1_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_param = fixer_x1_anonOut_1_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_size = fixer_x1_anonOut_1_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_source = fixer_x1_anonOut_1_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_address = fixer_x1_anonOut_1_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_mask = fixer_x1_anonOut_1_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_data = fixer_x1_anonOut_1_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_a_bits_corrupt = fixer_x1_anonOut_1_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_b_ready = fixer_x1_anonOut_1_b_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_1_b_valid = fixer_x1_anonOut_1_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_opcode = fixer_x1_anonOut_1_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_param = fixer_x1_anonOut_1_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_size = fixer_x1_anonOut_1_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_source = fixer_x1_anonOut_1_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_address = fixer_x1_anonOut_1_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_mask = fixer_x1_anonOut_1_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_data = fixer_x1_anonOut_1_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_b_bits_corrupt = fixer_x1_anonOut_1_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_c_ready = fixer_x1_anonOut_1_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_2_c_valid = fixer_x1_anonOut_1_c_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_opcode = fixer_x1_anonOut_1_c_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_param = fixer_x1_anonOut_1_c_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_size = fixer_x1_anonOut_1_c_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_source = fixer_x1_anonOut_1_c_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_address = fixer_x1_anonOut_1_c_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_data = fixer_x1_anonOut_1_c_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_c_bits_corrupt = fixer_x1_anonOut_1_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_d_ready = fixer_x1_anonOut_1_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_1_d_valid = fixer_x1_anonOut_1_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_opcode = fixer_x1_anonOut_1_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_param = fixer_x1_anonOut_1_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_size = fixer_x1_anonOut_1_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_source = fixer_x1_anonOut_1_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_sink = fixer_x1_anonOut_1_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_denied = fixer_x1_anonOut_1_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_data = fixer_x1_anonOut_1_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_d_bits_corrupt = fixer_x1_anonOut_1_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_1_e_ready = fixer_x1_anonOut_1_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_2_e_valid = fixer_x1_anonOut_1_e_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_2_e_bits_sink = fixer_x1_anonOut_1_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33]
wire fixer__anonIn_a_ready_T_11 = fixer_x1_anonOut_2_a_ready; // @[FIFOFixer.scala:96:33]
assign fixer_auto_anon_out_3_a_valid = fixer_x1_anonOut_2_a_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_opcode = fixer_x1_anonOut_2_a_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_param = fixer_x1_anonOut_2_a_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_size = fixer_x1_anonOut_2_a_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_source = fixer_x1_anonOut_2_a_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_address = fixer_x1_anonOut_2_a_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_mask = fixer_x1_anonOut_2_a_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_data = fixer_x1_anonOut_2_a_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_a_bits_corrupt = fixer_x1_anonOut_2_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_b_ready = fixer_x1_anonOut_2_b_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_2_b_valid = fixer_x1_anonOut_2_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_opcode = fixer_x1_anonOut_2_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_param = fixer_x1_anonOut_2_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_size = fixer_x1_anonOut_2_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_source = fixer_x1_anonOut_2_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_address = fixer_x1_anonOut_2_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_mask = fixer_x1_anonOut_2_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_data = fixer_x1_anonOut_2_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_b_bits_corrupt = fixer_x1_anonOut_2_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_c_ready = fixer_x1_anonOut_2_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_3_c_valid = fixer_x1_anonOut_2_c_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_opcode = fixer_x1_anonOut_2_c_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_param = fixer_x1_anonOut_2_c_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_size = fixer_x1_anonOut_2_c_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_source = fixer_x1_anonOut_2_c_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_address = fixer_x1_anonOut_2_c_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_data = fixer_x1_anonOut_2_c_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_c_bits_corrupt = fixer_x1_anonOut_2_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_d_ready = fixer_x1_anonOut_2_d_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonIn_2_d_valid = fixer_x1_anonOut_2_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_opcode = fixer_x1_anonOut_2_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_param = fixer_x1_anonOut_2_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_size = fixer_x1_anonOut_2_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_source = fixer_x1_anonOut_2_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_sink = fixer_x1_anonOut_2_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_denied = fixer_x1_anonOut_2_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_data = fixer_x1_anonOut_2_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_d_bits_corrupt = fixer_x1_anonOut_2_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonIn_2_e_ready = fixer_x1_anonOut_2_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_out_3_e_valid = fixer_x1_anonOut_2_e_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_out_3_e_bits_sink = fixer_x1_anonOut_2_e_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_a_ready = fixer_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_2 = fixer_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_anonOut_a_bits_opcode = fixer_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_param = fixer_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_size = fixer_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_source = fixer_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_address = fixer_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T = fixer_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_anonOut_a_bits_mask = fixer_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_data = fixer_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_a_bits_corrupt = fixer_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_b_ready = fixer_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_b_valid = fixer_anonIn_b_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_opcode = fixer_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_param = fixer_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_size = fixer_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_source = fixer_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_address = fixer_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_mask = fixer_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_data = fixer_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_b_bits_corrupt = fixer_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_c_ready = fixer_anonIn_c_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonOut_c_valid = fixer_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_opcode = fixer_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_param = fixer_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_size = fixer_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_source = fixer_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_address = fixer_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_data = fixer_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_c_bits_corrupt = fixer_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_d_ready = fixer_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_0_d_valid = fixer_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_opcode = fixer_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_param = fixer_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_size = fixer_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_source = fixer_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_sink = fixer_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_denied = fixer_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_data = fixer_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_d_bits_corrupt = fixer_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_0_e_ready = fixer_anonIn_e_ready; // @[FIFOFixer.scala:50:9]
assign fixer_anonOut_e_valid = fixer_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_anonOut_e_bits_sink = fixer_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_a_ready = fixer_x1_anonIn_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_5 = fixer_x1_anonIn_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_a_bits_opcode = fixer_x1_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_param = fixer_x1_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_size = fixer_x1_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_source = fixer_x1_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_address = fixer_x1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_31 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_5 = fixer_x1_anonIn_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_a_bits_mask = fixer_x1_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_data = fixer_x1_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_a_bits_corrupt = fixer_x1_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_b_ready = fixer_x1_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_b_valid = fixer_x1_anonIn_b_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_opcode = fixer_x1_anonIn_b_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_param = fixer_x1_anonIn_b_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_size = fixer_x1_anonIn_b_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_source = fixer_x1_anonIn_b_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_address = fixer_x1_anonIn_b_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_mask = fixer_x1_anonIn_b_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_data = fixer_x1_anonIn_b_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_b_bits_corrupt = fixer_x1_anonIn_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_c_ready = fixer_x1_anonIn_c_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_c_valid = fixer_x1_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_opcode = fixer_x1_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_param = fixer_x1_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_size = fixer_x1_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_source = fixer_x1_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_address = fixer_x1_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_data = fixer_x1_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_c_bits_corrupt = fixer_x1_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_d_ready = fixer_x1_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_1_d_valid = fixer_x1_anonIn_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_opcode = fixer_x1_anonIn_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_param = fixer_x1_anonIn_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_size = fixer_x1_anonIn_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_source = fixer_x1_anonIn_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_sink = fixer_x1_anonIn_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_denied = fixer_x1_anonIn_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_data = fixer_x1_anonIn_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_d_bits_corrupt = fixer_x1_anonIn_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_1_e_ready = fixer_x1_anonIn_e_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_e_valid = fixer_x1_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_e_bits_sink = fixer_x1_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_2_a_ready = fixer_x1_anonIn_1_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_8 = fixer_x1_anonIn_1_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_1_a_bits_opcode = fixer_x1_anonIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_param = fixer_x1_anonIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_size = fixer_x1_anonIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_source = fixer_x1_anonIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_address = fixer_x1_anonIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_62 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_10 = fixer_x1_anonIn_1_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_1_a_bits_mask = fixer_x1_anonIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_data = fixer_x1_anonIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_a_bits_corrupt = fixer_x1_anonIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_b_ready = fixer_x1_anonIn_1_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_2_b_valid = fixer_x1_anonIn_1_b_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_opcode = fixer_x1_anonIn_1_b_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_param = fixer_x1_anonIn_1_b_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_size = fixer_x1_anonIn_1_b_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_source = fixer_x1_anonIn_1_b_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_address = fixer_x1_anonIn_1_b_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_mask = fixer_x1_anonIn_1_b_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_data = fixer_x1_anonIn_1_b_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_b_bits_corrupt = fixer_x1_anonIn_1_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_c_ready = fixer_x1_anonIn_1_c_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_1_c_valid = fixer_x1_anonIn_1_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_opcode = fixer_x1_anonIn_1_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_param = fixer_x1_anonIn_1_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_size = fixer_x1_anonIn_1_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_source = fixer_x1_anonIn_1_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_address = fixer_x1_anonIn_1_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_data = fixer_x1_anonIn_1_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_c_bits_corrupt = fixer_x1_anonIn_1_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_d_ready = fixer_x1_anonIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_2_d_valid = fixer_x1_anonIn_1_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_opcode = fixer_x1_anonIn_1_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_param = fixer_x1_anonIn_1_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_size = fixer_x1_anonIn_1_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_source = fixer_x1_anonIn_1_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_sink = fixer_x1_anonIn_1_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_denied = fixer_x1_anonIn_1_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_data = fixer_x1_anonIn_1_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_d_bits_corrupt = fixer_x1_anonIn_1_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_2_e_ready = fixer_x1_anonIn_1_e_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_1_e_valid = fixer_x1_anonIn_1_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_1_e_bits_sink = fixer_x1_anonIn_1_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_3_a_ready = fixer_x1_anonIn_2_a_ready; // @[FIFOFixer.scala:50:9]
assign fixer__anonOut_a_valid_T_11 = fixer_x1_anonIn_2_a_valid; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonOut_2_a_bits_opcode = fixer_x1_anonIn_2_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_param = fixer_x1_anonIn_2_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_size = fixer_x1_anonIn_2_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_source = fixer_x1_anonIn_2_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_address = fixer_x1_anonIn_2_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] fixer__a_notFIFO_T_93 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31]
wire [31:0] fixer__a_id_T_15 = fixer_x1_anonIn_2_a_bits_address; // @[Parameters.scala:137:31]
assign fixer_x1_anonOut_2_a_bits_mask = fixer_x1_anonIn_2_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_data = fixer_x1_anonIn_2_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_a_bits_corrupt = fixer_x1_anonIn_2_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_b_ready = fixer_x1_anonIn_2_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_3_b_valid = fixer_x1_anonIn_2_b_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_opcode = fixer_x1_anonIn_2_b_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_param = fixer_x1_anonIn_2_b_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_size = fixer_x1_anonIn_2_b_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_source = fixer_x1_anonIn_2_b_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_address = fixer_x1_anonIn_2_b_bits_address; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_mask = fixer_x1_anonIn_2_b_bits_mask; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_data = fixer_x1_anonIn_2_b_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_b_bits_corrupt = fixer_x1_anonIn_2_b_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_c_ready = fixer_x1_anonIn_2_c_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_2_c_valid = fixer_x1_anonIn_2_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_opcode = fixer_x1_anonIn_2_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_param = fixer_x1_anonIn_2_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_size = fixer_x1_anonIn_2_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_source = fixer_x1_anonIn_2_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_address = fixer_x1_anonIn_2_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_data = fixer_x1_anonIn_2_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_c_bits_corrupt = fixer_x1_anonIn_2_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_d_ready = fixer_x1_anonIn_2_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign fixer_auto_anon_in_3_d_valid = fixer_x1_anonIn_2_d_valid; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_opcode = fixer_x1_anonIn_2_d_bits_opcode; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_param = fixer_x1_anonIn_2_d_bits_param; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_size = fixer_x1_anonIn_2_d_bits_size; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_source = fixer_x1_anonIn_2_d_bits_source; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_sink = fixer_x1_anonIn_2_d_bits_sink; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_denied = fixer_x1_anonIn_2_d_bits_denied; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_data = fixer_x1_anonIn_2_d_bits_data; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_d_bits_corrupt = fixer_x1_anonIn_2_d_bits_corrupt; // @[FIFOFixer.scala:50:9]
assign fixer_auto_anon_in_3_e_ready = fixer_x1_anonIn_2_e_ready; // @[FIFOFixer.scala:50:9]
assign fixer_x1_anonOut_2_e_valid = fixer_x1_anonIn_2_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign fixer_x1_anonOut_2_e_bits_sink = fixer_x1_anonIn_2_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire [32:0] fixer__a_notFIFO_T_1 = {1'h0, fixer__a_notFIFO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_2 = fixer__a_notFIFO_T_1 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_3 = fixer__a_notFIFO_T_2; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_4 = fixer__a_notFIFO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_5 = {fixer_anonIn_a_bits_address[31:17], fixer_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_6 = {1'h0, fixer__a_notFIFO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_7 = fixer__a_notFIFO_T_6 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_8 = fixer__a_notFIFO_T_7; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_9 = fixer__a_notFIFO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_10 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_11 = {1'h0, fixer__a_notFIFO_T_10}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_12 = fixer__a_notFIFO_T_11 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_13 = fixer__a_notFIFO_T_12; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_14 = fixer__a_notFIFO_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_15 = fixer__a_notFIFO_T_4 | fixer__a_notFIFO_T_9; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_16 = fixer__a_notFIFO_T_15 | fixer__a_notFIFO_T_14; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_17 = {fixer_anonIn_a_bits_address[31:28], fixer_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_18 = {1'h0, fixer__a_notFIFO_T_17}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_19 = fixer__a_notFIFO_T_18 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_20 = fixer__a_notFIFO_T_19; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_21 = fixer__a_notFIFO_T_20 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_22 = fixer_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_23 = {1'h0, fixer__a_notFIFO_T_22}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_24 = fixer__a_notFIFO_T_23 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_25 = fixer__a_notFIFO_T_24; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_26 = fixer__a_notFIFO_T_25 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_27 = fixer__a_notFIFO_T_21 | fixer__a_notFIFO_T_26; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_29 = fixer__a_notFIFO_T_27; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_30 = fixer__a_notFIFO_T_29; // @[Mux.scala:30:73]
wire fixer_a_notFIFO = fixer__a_notFIFO_T_30; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_1 = {1'h0, fixer__a_id_T}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T = fixer_anonIn_a_ready & fixer_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T = 27'hFFF << fixer_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_1 = fixer__a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_2 = ~fixer__a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode = fixer__a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T = fixer_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata = ~fixer__a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1 = fixer_a_first_beats1_opdata ? fixer_a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T = {1'h0, fixer_a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1 = fixer__a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first = fixer_a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T = fixer_a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_1 = fixer_a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last = fixer__a_first_last_T | fixer__a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done = fixer_a_first_last & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T = ~fixer_a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count = fixer_a_first_beats1 & fixer__a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T = fixer_a_first ? fixer_a_first_beats1 : fixer_a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T = fixer_anonOut_d_ready & fixer_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T = 27'hFFF << fixer_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_1 = fixer__d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_2 = ~fixer__d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode = fixer__d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata = fixer_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1 = fixer_d_first_beats1_opdata ? fixer_d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T = {1'h0, fixer_d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1 = fixer__d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first = fixer_d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T = fixer_d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_1 = fixer_d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last = fixer__d_first_last_T | fixer__d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done = fixer_d_first_last & fixer__d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T = ~fixer_d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count = fixer_d_first_beats1 & fixer__d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T = fixer_d_first_first ? fixer_d_first_beats1 : fixer_d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_1 = fixer_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first = fixer_d_first_first & fixer__d_first_T_1; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T = ~fixer_a_notFIFO; // @[Mux.scala:30:73]
wire fixer__T_2 = fixer_anonIn_d_ready & fixer_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_anonOut_a_valid = fixer__anonOut_a_valid_T_2; // @[FIFOFixer.scala:95:33]
assign fixer_anonIn_a_ready = fixer__anonIn_a_ready_T_2; // @[FIFOFixer.scala:96:33]
reg [2:0] fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35]
wire [2:0] fixer_SourceIdSet; // @[FIFOFixer.scala:116:36]
wire [2:0] fixer_SourceIdClear; // @[FIFOFixer.scala:117:38]
wire [3:0] fixer__SourceIdSet_T = 4'h1 << fixer_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet = fixer_a_first & fixer__a_first_T & ~fixer_a_notFIFO ? fixer__SourceIdSet_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] fixer__SourceIdClear_T = 4'h1 << fixer_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear = fixer_d_first & fixer__T_2 ? fixer__SourceIdClear_T[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [2:0] fixer__SourceIdFIFOed_T = fixer_SourceIdFIFOed | fixer_SourceIdSet; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed = &fixer_SourceIdFIFOed; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_32 = {1'h0, fixer__a_notFIFO_T_31}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_33 = fixer__a_notFIFO_T_32 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_34 = fixer__a_notFIFO_T_33; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_35 = fixer__a_notFIFO_T_34 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_36 = {fixer_x1_anonIn_a_bits_address[31:17], fixer_x1_anonIn_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_37 = {1'h0, fixer__a_notFIFO_T_36}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_38 = fixer__a_notFIFO_T_37 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_39 = fixer__a_notFIFO_T_38; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_40 = fixer__a_notFIFO_T_39 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_41 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_42 = {1'h0, fixer__a_notFIFO_T_41}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_43 = fixer__a_notFIFO_T_42 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_44 = fixer__a_notFIFO_T_43; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_45 = fixer__a_notFIFO_T_44 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_46 = fixer__a_notFIFO_T_35 | fixer__a_notFIFO_T_40; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_47 = fixer__a_notFIFO_T_46 | fixer__a_notFIFO_T_45; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_48 = {fixer_x1_anonIn_a_bits_address[31:28], fixer_x1_anonIn_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_49 = {1'h0, fixer__a_notFIFO_T_48}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_50 = fixer__a_notFIFO_T_49 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_51 = fixer__a_notFIFO_T_50; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_52 = fixer__a_notFIFO_T_51 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_53 = fixer_x1_anonIn_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_54 = {1'h0, fixer__a_notFIFO_T_53}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_55 = fixer__a_notFIFO_T_54 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_56 = fixer__a_notFIFO_T_55; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_57 = fixer__a_notFIFO_T_56 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_58 = fixer__a_notFIFO_T_52 | fixer__a_notFIFO_T_57; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_60 = fixer__a_notFIFO_T_58; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_61 = fixer__a_notFIFO_T_60; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_1 = fixer__a_notFIFO_T_61; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_6 = {1'h0, fixer__a_id_T_5}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_1 = fixer_x1_anonIn_a_ready & fixer_x1_anonIn_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonIn_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_4 = fixer__a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_5 = ~fixer__a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode_1 = fixer__a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_1 = fixer_x1_anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_1 = ~fixer__a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1_1 = fixer_a_first_beats1_opdata_1 ? fixer_a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T_1 = {1'h0, fixer_a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1_1 = fixer__a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first_1 = fixer_a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_2 = fixer_a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_3 = fixer_a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_1 = fixer__a_first_last_T_2 | fixer__a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_1 = fixer_a_first_last_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T_1 = ~fixer_a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count_1 = fixer_a_first_beats1_1 & fixer__a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T_1 = fixer_a_first_1 ? fixer_a_first_beats1_1 : fixer_a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_2 = fixer_x1_anonOut_d_ready & fixer_x1_anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_3 = 27'hFFF << fixer_x1_anonOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_4 = fixer__d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_5 = ~fixer__d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode_1 = fixer__d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_1 = fixer_x1_anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1_1 = fixer_d_first_beats1_opdata_1 ? fixer_d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T_1 = {1'h0, fixer_d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1_1 = fixer__d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_1 = fixer_d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_2 = fixer_d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_3 = fixer_d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_1 = fixer__d_first_last_T_2 | fixer__d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_1 = fixer_d_first_last_1 & fixer__d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T_1 = ~fixer_d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count_1 = fixer_d_first_beats1_1 & fixer__d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T_1 = fixer_d_first_first_1 ? fixer_d_first_beats1_1 : fixer_d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_3 = fixer_x1_anonOut_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_1 = fixer_d_first_first_1 & fixer__d_first_T_3; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_1_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_1_2; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_1 = ~fixer_a_notFIFO_1; // @[Mux.scala:30:73]
wire fixer__T_18 = fixer_x1_anonIn_d_ready & fixer_x1_anonIn_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_a_valid = fixer__anonOut_a_valid_T_5; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_a_ready = fixer__anonIn_a_ready_T_5; // @[FIFOFixer.scala:96:33]
reg [2:0] fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35]
wire [2:0] fixer_SourceIdSet_1; // @[FIFOFixer.scala:116:36]
wire [2:0] fixer_SourceIdClear_1; // @[FIFOFixer.scala:117:38]
wire [3:0] fixer__SourceIdSet_T_1 = 4'h1 << fixer_x1_anonIn_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_1 = fixer_a_first_1 & fixer__a_first_T_1 & ~fixer_a_notFIFO_1 ? fixer__SourceIdSet_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] fixer__SourceIdClear_T_1 = 4'h1 << fixer_x1_anonIn_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_1 = fixer_d_first_1 & fixer__T_18 ? fixer__SourceIdClear_T_1[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [2:0] fixer__SourceIdFIFOed_T_1 = fixer_SourceIdFIFOed_1 | fixer_SourceIdSet_1; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_1 = &fixer_SourceIdFIFOed_1; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_63 = {1'h0, fixer__a_notFIFO_T_62}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_64 = fixer__a_notFIFO_T_63 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_65 = fixer__a_notFIFO_T_64; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_66 = fixer__a_notFIFO_T_65 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_67 = {fixer_x1_anonIn_1_a_bits_address[31:17], fixer_x1_anonIn_1_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_68 = {1'h0, fixer__a_notFIFO_T_67}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_69 = fixer__a_notFIFO_T_68 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_70 = fixer__a_notFIFO_T_69; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_71 = fixer__a_notFIFO_T_70 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_72 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_73 = {1'h0, fixer__a_notFIFO_T_72}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_74 = fixer__a_notFIFO_T_73 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_75 = fixer__a_notFIFO_T_74; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_76 = fixer__a_notFIFO_T_75 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_77 = fixer__a_notFIFO_T_66 | fixer__a_notFIFO_T_71; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_78 = fixer__a_notFIFO_T_77 | fixer__a_notFIFO_T_76; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_79 = {fixer_x1_anonIn_1_a_bits_address[31:28], fixer_x1_anonIn_1_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_80 = {1'h0, fixer__a_notFIFO_T_79}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_81 = fixer__a_notFIFO_T_80 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_82 = fixer__a_notFIFO_T_81; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_83 = fixer__a_notFIFO_T_82 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_84 = fixer_x1_anonIn_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_85 = {1'h0, fixer__a_notFIFO_T_84}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_86 = fixer__a_notFIFO_T_85 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_87 = fixer__a_notFIFO_T_86; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_88 = fixer__a_notFIFO_T_87 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_89 = fixer__a_notFIFO_T_83 | fixer__a_notFIFO_T_88; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_91 = fixer__a_notFIFO_T_89; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_92 = fixer__a_notFIFO_T_91; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_2 = fixer__a_notFIFO_T_92; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_11 = {1'h0, fixer__a_id_T_10}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_2 = fixer_x1_anonIn_1_a_ready & fixer_x1_anonIn_1_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonIn_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_7 = fixer__a_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_8 = ~fixer__a_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode_2 = fixer__a_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_2 = fixer_x1_anonIn_1_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_2 = ~fixer__a_first_beats1_opdata_T_2; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1_2 = fixer_a_first_beats1_opdata_2 ? fixer_a_first_beats1_decode_2 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T_2 = {1'h0, fixer_a_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1_2 = fixer__a_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first_2 = fixer_a_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_4 = fixer_a_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_5 = fixer_a_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_2 = fixer__a_first_last_T_4 | fixer__a_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_2 = fixer_a_first_last_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T_2 = ~fixer_a_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count_2 = fixer_a_first_beats1_2 & fixer__a_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T_2 = fixer_a_first_2 ? fixer_a_first_beats1_2 : fixer_a_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_4 = fixer_x1_anonOut_1_d_ready & fixer_x1_anonOut_1_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_6 = 27'hFFF << fixer_x1_anonOut_1_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_7 = fixer__d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_8 = ~fixer__d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode_2 = fixer__d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_2 = fixer_x1_anonOut_1_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1_2 = fixer_d_first_beats1_opdata_2 ? fixer_d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T_2 = {1'h0, fixer_d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1_2 = fixer__d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_2 = fixer_d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_4 = fixer_d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_5 = fixer_d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_2 = fixer__d_first_last_T_4 | fixer__d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_2 = fixer_d_first_last_2 & fixer__d_first_T_4; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T_2 = ~fixer_d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count_2 = fixer_d_first_beats1_2 & fixer__d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T_2 = fixer_d_first_first_2 ? fixer_d_first_beats1_2 : fixer_d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_5 = fixer_x1_anonOut_1_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_2 = fixer_d_first_first_2 & fixer__d_first_T_5; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_2_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_2_2; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_2 = ~fixer_a_notFIFO_2; // @[Mux.scala:30:73]
wire fixer__T_34 = fixer_x1_anonIn_1_d_ready & fixer_x1_anonIn_1_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_1_a_valid = fixer__anonOut_a_valid_T_8; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_1_a_ready = fixer__anonIn_a_ready_T_8; // @[FIFOFixer.scala:96:33]
reg [2:0] fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35]
wire [2:0] fixer_SourceIdSet_2; // @[FIFOFixer.scala:116:36]
wire [2:0] fixer_SourceIdClear_2; // @[FIFOFixer.scala:117:38]
wire [3:0] fixer__SourceIdSet_T_2 = 4'h1 << fixer_x1_anonIn_1_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_2 = fixer_a_first_2 & fixer__a_first_T_2 & ~fixer_a_notFIFO_2 ? fixer__SourceIdSet_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] fixer__SourceIdClear_T_2 = 4'h1 << fixer_x1_anonIn_1_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_2 = fixer_d_first_2 & fixer__T_34 ? fixer__SourceIdClear_T_2[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [2:0] fixer__SourceIdFIFOed_T_2 = fixer_SourceIdFIFOed_2 | fixer_SourceIdSet_2; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_2 = &fixer_SourceIdFIFOed_2; // @[FIFOFixer.scala:115:35, :127:41]
wire [32:0] fixer__a_notFIFO_T_94 = {1'h0, fixer__a_notFIFO_T_93}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_95 = fixer__a_notFIFO_T_94 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_96 = fixer__a_notFIFO_T_95; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_97 = fixer__a_notFIFO_T_96 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_98 = {fixer_x1_anonIn_2_a_bits_address[31:17], fixer_x1_anonIn_2_a_bits_address[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_99 = {1'h0, fixer__a_notFIFO_T_98}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_100 = fixer__a_notFIFO_T_99 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_101 = fixer__a_notFIFO_T_100; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_102 = fixer__a_notFIFO_T_101 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_103 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_104 = {1'h0, fixer__a_notFIFO_T_103}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_105 = fixer__a_notFIFO_T_104 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_106 = fixer__a_notFIFO_T_105; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_107 = fixer__a_notFIFO_T_106 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_108 = fixer__a_notFIFO_T_97 | fixer__a_notFIFO_T_102; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_109 = fixer__a_notFIFO_T_108 | fixer__a_notFIFO_T_107; // @[Parameters.scala:629:89]
wire [31:0] fixer__a_notFIFO_T_110 = {fixer_x1_anonIn_2_a_bits_address[31:28], fixer_x1_anonIn_2_a_bits_address[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_111 = {1'h0, fixer__a_notFIFO_T_110}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_112 = fixer__a_notFIFO_T_111 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_113 = fixer__a_notFIFO_T_112; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_114 = fixer__a_notFIFO_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] fixer__a_notFIFO_T_115 = fixer_x1_anonIn_2_a_bits_address ^ 32'h80000000; // @[Parameters.scala:137:31]
wire [32:0] fixer__a_notFIFO_T_116 = {1'h0, fixer__a_notFIFO_T_115}; // @[Parameters.scala:137:{31,41}]
wire [32:0] fixer__a_notFIFO_T_117 = fixer__a_notFIFO_T_116 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] fixer__a_notFIFO_T_118 = fixer__a_notFIFO_T_117; // @[Parameters.scala:137:46]
wire fixer__a_notFIFO_T_119 = fixer__a_notFIFO_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire fixer__a_notFIFO_T_120 = fixer__a_notFIFO_T_114 | fixer__a_notFIFO_T_119; // @[Parameters.scala:629:89]
wire fixer__a_notFIFO_T_122 = fixer__a_notFIFO_T_120; // @[Mux.scala:30:73]
wire fixer__a_notFIFO_T_123 = fixer__a_notFIFO_T_122; // @[Mux.scala:30:73]
wire fixer_a_notFIFO_3 = fixer__a_notFIFO_T_123; // @[Mux.scala:30:73]
wire [32:0] fixer__a_id_T_16 = {1'h0, fixer__a_id_T_15}; // @[Parameters.scala:137:{31,41}]
wire fixer__a_first_T_3 = fixer_x1_anonIn_2_a_ready & fixer_x1_anonIn_2_a_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__a_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonIn_2_a_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__a_first_beats1_decode_T_10 = fixer__a_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__a_first_beats1_decode_T_11 = ~fixer__a_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] fixer_a_first_beats1_decode_3 = fixer__a_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire fixer__a_first_beats1_opdata_T_3 = fixer_x1_anonIn_2_a_bits_opcode[2]; // @[Edges.scala:92:37]
wire fixer_a_first_beats1_opdata_3 = ~fixer__a_first_beats1_opdata_T_3; // @[Edges.scala:92:{28,37}]
wire [8:0] fixer_a_first_beats1_3 = fixer_a_first_beats1_opdata_3 ? fixer_a_first_beats1_decode_3 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] fixer_a_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] fixer__a_first_counter1_T_3 = {1'h0, fixer_a_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_a_first_counter1_3 = fixer__a_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire fixer_a_first_3 = fixer_a_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__a_first_last_T_6 = fixer_a_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__a_first_last_T_7 = fixer_a_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_a_first_last_3 = fixer__a_first_last_T_6 | fixer__a_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire fixer_a_first_done_3 = fixer_a_first_last_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35]
wire [8:0] fixer__a_first_count_T_3 = ~fixer_a_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_a_first_count_3 = fixer_a_first_beats1_3 & fixer__a_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__a_first_counter_T_3 = fixer_a_first_3 ? fixer_a_first_beats1_3 : fixer_a_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_6 = fixer_x1_anonOut_2_d_ready & fixer_x1_anonOut_2_d_valid; // @[Decoupled.scala:51:35]
wire [26:0] fixer__d_first_beats1_decode_T_9 = 27'hFFF << fixer_x1_anonOut_2_d_bits_size; // @[package.scala:243:71]
wire [11:0] fixer__d_first_beats1_decode_T_10 = fixer__d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] fixer__d_first_beats1_decode_T_11 = ~fixer__d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}]
wire [8:0] fixer_d_first_beats1_decode_3 = fixer__d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46]
wire fixer_d_first_beats1_opdata_3 = fixer_x1_anonOut_2_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] fixer_d_first_beats1_3 = fixer_d_first_beats1_opdata_3 ? fixer_d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] fixer_d_first_counter_3; // @[Edges.scala:229:27]
wire [9:0] fixer__d_first_counter1_T_3 = {1'h0, fixer_d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] fixer_d_first_counter1_3 = fixer__d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28]
wire fixer_d_first_first_3 = fixer_d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire fixer__d_first_last_T_6 = fixer_d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire fixer__d_first_last_T_7 = fixer_d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire fixer_d_first_last_3 = fixer__d_first_last_T_6 | fixer__d_first_last_T_7; // @[Edges.scala:232:{25,33,43}]
wire fixer_d_first_done_3 = fixer_d_first_last_3 & fixer__d_first_T_6; // @[Decoupled.scala:51:35]
wire [8:0] fixer__d_first_count_T_3 = ~fixer_d_first_counter1_3; // @[Edges.scala:230:28, :234:27]
wire [8:0] fixer_d_first_count_3 = fixer_d_first_beats1_3 & fixer__d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] fixer__d_first_counter_T_3 = fixer_d_first_first_3 ? fixer_d_first_beats1_3 : fixer_d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire fixer__d_first_T_7 = fixer_x1_anonOut_2_d_bits_opcode != 3'h6; // @[FIFOFixer.scala:75:63]
wire fixer_d_first_3 = fixer_d_first_first_3 & fixer__d_first_T_7; // @[FIFOFixer.scala:75:{42,63}]
reg fixer_flight_3_0; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3_1; // @[FIFOFixer.scala:79:27]
reg fixer_flight_3_2; // @[FIFOFixer.scala:79:27]
wire fixer__flight_T_3 = ~fixer_a_notFIFO_3; // @[Mux.scala:30:73]
wire fixer__T_50 = fixer_x1_anonIn_2_d_ready & fixer_x1_anonIn_2_d_valid; // @[Decoupled.scala:51:35]
assign fixer_x1_anonOut_2_a_valid = fixer__anonOut_a_valid_T_11; // @[FIFOFixer.scala:95:33]
assign fixer_x1_anonIn_2_a_ready = fixer__anonIn_a_ready_T_11; // @[FIFOFixer.scala:96:33]
reg [2:0] fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35]
wire [2:0] fixer_SourceIdSet_3; // @[FIFOFixer.scala:116:36]
wire [2:0] fixer_SourceIdClear_3; // @[FIFOFixer.scala:117:38]
wire [3:0] fixer__SourceIdSet_T_3 = 4'h1 << fixer_x1_anonIn_2_a_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdSet_3 = fixer_a_first_3 & fixer__a_first_T_3 & ~fixer_a_notFIFO_3 ? fixer__SourceIdSet_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [3:0] fixer__SourceIdClear_T_3 = 4'h1 << fixer_x1_anonIn_2_d_bits_source; // @[OneHot.scala:58:35]
assign fixer_SourceIdClear_3 = fixer_d_first_3 & fixer__T_50 ? fixer__SourceIdClear_T_3[2:0] : 3'h0; // @[OneHot.scala:58:35]
wire [2:0] fixer__SourceIdFIFOed_T_3 = fixer_SourceIdFIFOed_3 | fixer_SourceIdSet_3; // @[FIFOFixer.scala:115:35, :116:36, :126:40]
wire fixer_allIDs_FIFOed_3 = &fixer_SourceIdFIFOed_3; // @[FIFOFixer.scala:115:35, :127:41]
wire coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_a_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_b_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_c_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_ready = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0 = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_tlMasterClockXingIn_e_valid = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_tlOut_a_ready = coupler_from_rockettile_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_valid = coupler_from_rockettile_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_opcode = coupler_from_rockettile_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_param = coupler_from_rockettile_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_size = coupler_from_rockettile_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_source = coupler_from_rockettile_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_address = coupler_from_rockettile_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_mask = coupler_from_rockettile_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_data = coupler_from_rockettile_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_a_bits_corrupt = coupler_from_rockettile_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_b_ready = coupler_from_rockettile_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_b_valid = coupler_from_rockettile_auto_tl_out_b_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_b_bits_opcode = coupler_from_rockettile_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_b_bits_param = coupler_from_rockettile_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlOut_b_bits_size = coupler_from_rockettile_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_b_bits_source = coupler_from_rockettile_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_tlOut_b_bits_address = coupler_from_rockettile_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_tlOut_b_bits_mask = coupler_from_rockettile_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlOut_b_bits_data = coupler_from_rockettile_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_b_bits_corrupt = coupler_from_rockettile_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_c_ready = coupler_from_rockettile_auto_tl_out_c_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_valid = coupler_from_rockettile_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_opcode = coupler_from_rockettile_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_param = coupler_from_rockettile_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_size = coupler_from_rockettile_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_source = coupler_from_rockettile_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_address = coupler_from_rockettile_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_data = coupler_from_rockettile_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_c_bits_corrupt = coupler_from_rockettile_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_d_ready = coupler_from_rockettile_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlOut_d_valid = coupler_from_rockettile_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_d_bits_opcode = coupler_from_rockettile_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_d_bits_param = coupler_from_rockettile_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlOut_d_bits_size = coupler_from_rockettile_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlOut_d_bits_source = coupler_from_rockettile_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlOut_d_bits_sink = coupler_from_rockettile_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_denied = coupler_from_rockettile_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlOut_d_bits_data = coupler_from_rockettile_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_d_bits_corrupt = coupler_from_rockettile_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_e_ready = coupler_from_rockettile_auto_tl_out_e_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_e_valid = coupler_from_rockettile_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_0_e_bits_sink = coupler_from_rockettile_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_tlIn_a_ready = coupler_from_rockettile_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_valid = coupler_from_rockettile_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_opcode = coupler_from_rockettile_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_param = coupler_from_rockettile_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_size = coupler_from_rockettile_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_source = coupler_from_rockettile_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_address = coupler_from_rockettile_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_mask = coupler_from_rockettile_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_data = coupler_from_rockettile_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_b_ready = coupler_from_rockettile_tlOut_b_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_b_valid = coupler_from_rockettile_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_b_bits_opcode = coupler_from_rockettile_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_b_bits_param = coupler_from_rockettile_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlIn_b_bits_size = coupler_from_rockettile_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_b_bits_source = coupler_from_rockettile_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlIn_b_bits_address = coupler_from_rockettile_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_tlIn_b_bits_mask = coupler_from_rockettile_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlIn_b_bits_data = coupler_from_rockettile_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_b_bits_corrupt = coupler_from_rockettile_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_c_ready = coupler_from_rockettile_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_valid = coupler_from_rockettile_tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_opcode = coupler_from_rockettile_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_param = coupler_from_rockettile_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_size = coupler_from_rockettile_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_source = coupler_from_rockettile_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_address = coupler_from_rockettile_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_data = coupler_from_rockettile_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_d_ready = coupler_from_rockettile_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_tlIn_d_valid = coupler_from_rockettile_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_d_bits_opcode = coupler_from_rockettile_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_d_bits_param = coupler_from_rockettile_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlIn_d_bits_size = coupler_from_rockettile_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlIn_d_bits_source = coupler_from_rockettile_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlIn_d_bits_sink = coupler_from_rockettile_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_denied = coupler_from_rockettile_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlIn_d_bits_data = coupler_from_rockettile_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_d_bits_corrupt = coupler_from_rockettile_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_e_ready = coupler_from_rockettile_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_e_valid = coupler_from_rockettile_tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_out_e_bits_sink = coupler_from_rockettile_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_no_bufferOut_a_ready = coupler_from_rockettile_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_valid = coupler_from_rockettile_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_opcode = coupler_from_rockettile_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_param = coupler_from_rockettile_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_size = coupler_from_rockettile_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_source = coupler_from_rockettile_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_address = coupler_from_rockettile_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_mask = coupler_from_rockettile_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_data = coupler_from_rockettile_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_a_bits_corrupt = coupler_from_rockettile_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_b_ready = coupler_from_rockettile_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_b_valid = coupler_from_rockettile_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_b_bits_opcode = coupler_from_rockettile_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_param = coupler_from_rockettile_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_b_bits_size = coupler_from_rockettile_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_b_bits_source = coupler_from_rockettile_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferOut_b_bits_address = coupler_from_rockettile_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferOut_b_bits_mask = coupler_from_rockettile_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_b_bits_data = coupler_from_rockettile_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_c_ready = coupler_from_rockettile_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_valid = coupler_from_rockettile_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_opcode = coupler_from_rockettile_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_param = coupler_from_rockettile_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_size = coupler_from_rockettile_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_source = coupler_from_rockettile_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_address = coupler_from_rockettile_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_data = coupler_from_rockettile_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_c_bits_corrupt = coupler_from_rockettile_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_d_ready = coupler_from_rockettile_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_valid = coupler_from_rockettile_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_opcode = coupler_from_rockettile_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_param = coupler_from_rockettile_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferOut_d_bits_size = coupler_from_rockettile_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferOut_d_bits_source = coupler_from_rockettile_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_d_bits_sink = coupler_from_rockettile_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_denied = coupler_from_rockettile_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferOut_d_bits_data = coupler_from_rockettile_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_e_ready = coupler_from_rockettile_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_e_valid = coupler_from_rockettile_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_tlOut_e_bits_sink = coupler_from_rockettile_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_ready = coupler_from_rockettile_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_valid = coupler_from_rockettile_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_opcode = coupler_from_rockettile_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_param = coupler_from_rockettile_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_size = coupler_from_rockettile_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_source = coupler_from_rockettile_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_address = coupler_from_rockettile_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_mask = coupler_from_rockettile_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_data = coupler_from_rockettile_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_a_bits_corrupt = coupler_from_rockettile_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_b_ready = coupler_from_rockettile_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_b_valid = coupler_from_rockettile_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_b_bits_opcode = coupler_from_rockettile_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_param = coupler_from_rockettile_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_b_bits_size = coupler_from_rockettile_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_b_bits_source = coupler_from_rockettile_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferIn_b_bits_address = coupler_from_rockettile_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_no_bufferIn_b_bits_mask = coupler_from_rockettile_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_b_bits_data = coupler_from_rockettile_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_c_ready = coupler_from_rockettile_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_valid = coupler_from_rockettile_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_opcode = coupler_from_rockettile_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_param = coupler_from_rockettile_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_size = coupler_from_rockettile_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_source = coupler_from_rockettile_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_address = coupler_from_rockettile_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_data = coupler_from_rockettile_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_c_bits_corrupt = coupler_from_rockettile_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_d_ready = coupler_from_rockettile_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_valid = coupler_from_rockettile_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_opcode = coupler_from_rockettile_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_param = coupler_from_rockettile_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_no_bufferIn_d_bits_size = coupler_from_rockettile_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_no_bufferIn_d_bits_source = coupler_from_rockettile_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_d_bits_sink = coupler_from_rockettile_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_denied = coupler_from_rockettile_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_no_bufferIn_d_bits_data = coupler_from_rockettile_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_e_ready = coupler_from_rockettile_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_e_valid = coupler_from_rockettile_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlIn_e_bits_sink = coupler_from_rockettile_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_ready = coupler_from_rockettile_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_valid = coupler_from_rockettile_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_opcode = coupler_from_rockettile_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_param = coupler_from_rockettile_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_size = coupler_from_rockettile_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_source = coupler_from_rockettile_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_address = coupler_from_rockettile_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_mask = coupler_from_rockettile_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_data = coupler_from_rockettile_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_b_ready = coupler_from_rockettile_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_b_valid = coupler_from_rockettile_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_c_ready = coupler_from_rockettile_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_valid = coupler_from_rockettile_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_opcode = coupler_from_rockettile_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_param = coupler_from_rockettile_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_size = coupler_from_rockettile_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_source = coupler_from_rockettile_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_address = coupler_from_rockettile_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_data = coupler_from_rockettile_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_d_ready = coupler_from_rockettile_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_valid = coupler_from_rockettile_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_e_ready = coupler_from_rockettile_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_e_valid = coupler_from_rockettile_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_no_bufferOut_e_bits_sink = coupler_from_rockettile_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_a_ready = coupler_from_rockettile_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_valid = coupler_from_rockettile_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_param = coupler_from_rockettile_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_size = coupler_from_rockettile_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_source = coupler_from_rockettile_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_address = coupler_from_rockettile_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_data = coupler_from_rockettile_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_b_ready = coupler_from_rockettile_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_valid = coupler_from_rockettile_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_c_ready = coupler_from_rockettile_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_valid = coupler_from_rockettile_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_param = coupler_from_rockettile_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_size = coupler_from_rockettile_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_source = coupler_from_rockettile_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_address = coupler_from_rockettile_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_data = coupler_from_rockettile_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_d_ready = coupler_from_rockettile_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_valid = coupler_from_rockettile_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingIn_e_ready = coupler_from_rockettile_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_e_valid = coupler_from_rockettile_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_no_bufferIn_e_bits_sink = coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_valid = coupler_from_rockettile_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_b_ready = coupler_from_rockettile_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_valid = coupler_from_rockettile_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_d_ready = coupler_from_rockettile_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_e_valid = coupler_from_rockettile_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_a_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_b_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_c_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_d_ready = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0 = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_1_tlMasterClockXingIn_e_valid = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_1_tlOut_a_ready = coupler_from_rockettile_1_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_valid = coupler_from_rockettile_1_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_opcode = coupler_from_rockettile_1_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_param = coupler_from_rockettile_1_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_size = coupler_from_rockettile_1_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_source = coupler_from_rockettile_1_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_address = coupler_from_rockettile_1_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_mask = coupler_from_rockettile_1_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_data = coupler_from_rockettile_1_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_a_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_b_ready = coupler_from_rockettile_1_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_b_valid = coupler_from_rockettile_1_auto_tl_out_b_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlOut_b_bits_opcode = coupler_from_rockettile_1_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_param = coupler_from_rockettile_1_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_1_tlOut_b_bits_size = coupler_from_rockettile_1_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlOut_b_bits_source = coupler_from_rockettile_1_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_1_tlOut_b_bits_address = coupler_from_rockettile_1_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_1_tlOut_b_bits_mask = coupler_from_rockettile_1_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_1_tlOut_b_bits_data = coupler_from_rockettile_1_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_b_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_c_ready = coupler_from_rockettile_1_auto_tl_out_c_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_valid = coupler_from_rockettile_1_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_opcode = coupler_from_rockettile_1_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_param = coupler_from_rockettile_1_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_size = coupler_from_rockettile_1_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_source = coupler_from_rockettile_1_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_address = coupler_from_rockettile_1_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_data = coupler_from_rockettile_1_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_c_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_d_ready = coupler_from_rockettile_1_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlOut_d_valid = coupler_from_rockettile_1_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_opcode = coupler_from_rockettile_1_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_param = coupler_from_rockettile_1_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_1_tlOut_d_bits_size = coupler_from_rockettile_1_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlOut_d_bits_source = coupler_from_rockettile_1_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlOut_d_bits_sink = coupler_from_rockettile_1_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_d_bits_denied = coupler_from_rockettile_1_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_1_tlOut_d_bits_data = coupler_from_rockettile_1_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_d_bits_corrupt = coupler_from_rockettile_1_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_e_ready = coupler_from_rockettile_1_auto_tl_out_e_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_e_valid = coupler_from_rockettile_1_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_1_e_bits_sink = coupler_from_rockettile_1_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_1_tlIn_a_ready = coupler_from_rockettile_1_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_valid = coupler_from_rockettile_1_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_opcode = coupler_from_rockettile_1_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_param = coupler_from_rockettile_1_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_size = coupler_from_rockettile_1_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_source = coupler_from_rockettile_1_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_address = coupler_from_rockettile_1_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_mask = coupler_from_rockettile_1_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_data = coupler_from_rockettile_1_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_1_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_b_ready = coupler_from_rockettile_1_tlOut_b_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_b_valid = coupler_from_rockettile_1_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlIn_b_bits_opcode = coupler_from_rockettile_1_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_param = coupler_from_rockettile_1_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlIn_b_bits_size = coupler_from_rockettile_1_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlIn_b_bits_source = coupler_from_rockettile_1_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_tlIn_b_bits_address = coupler_from_rockettile_1_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_tlIn_b_bits_mask = coupler_from_rockettile_1_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlIn_b_bits_data = coupler_from_rockettile_1_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_b_bits_corrupt = coupler_from_rockettile_1_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_c_ready = coupler_from_rockettile_1_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_valid = coupler_from_rockettile_1_tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_opcode = coupler_from_rockettile_1_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_param = coupler_from_rockettile_1_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_size = coupler_from_rockettile_1_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_source = coupler_from_rockettile_1_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_address = coupler_from_rockettile_1_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_data = coupler_from_rockettile_1_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_1_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_d_ready = coupler_from_rockettile_1_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_tlIn_d_valid = coupler_from_rockettile_1_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_opcode = coupler_from_rockettile_1_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_param = coupler_from_rockettile_1_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlIn_d_bits_size = coupler_from_rockettile_1_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlIn_d_bits_source = coupler_from_rockettile_1_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlIn_d_bits_sink = coupler_from_rockettile_1_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_d_bits_denied = coupler_from_rockettile_1_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlIn_d_bits_data = coupler_from_rockettile_1_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_d_bits_corrupt = coupler_from_rockettile_1_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_e_ready = coupler_from_rockettile_1_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_e_valid = coupler_from_rockettile_1_tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_out_e_bits_sink = coupler_from_rockettile_1_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_1_no_bufferOut_a_ready = coupler_from_rockettile_1_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_valid = coupler_from_rockettile_1_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_opcode = coupler_from_rockettile_1_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_param = coupler_from_rockettile_1_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_size = coupler_from_rockettile_1_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_source = coupler_from_rockettile_1_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_address = coupler_from_rockettile_1_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_mask = coupler_from_rockettile_1_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_data = coupler_from_rockettile_1_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_a_bits_corrupt = coupler_from_rockettile_1_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_b_ready = coupler_from_rockettile_1_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_b_valid = coupler_from_rockettile_1_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_b_bits_opcode = coupler_from_rockettile_1_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_param = coupler_from_rockettile_1_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferOut_b_bits_size = coupler_from_rockettile_1_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_b_bits_source = coupler_from_rockettile_1_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferOut_b_bits_address = coupler_from_rockettile_1_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_no_bufferOut_b_bits_mask = coupler_from_rockettile_1_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferOut_b_bits_data = coupler_from_rockettile_1_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_1_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_c_ready = coupler_from_rockettile_1_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_valid = coupler_from_rockettile_1_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_opcode = coupler_from_rockettile_1_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_param = coupler_from_rockettile_1_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_size = coupler_from_rockettile_1_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_source = coupler_from_rockettile_1_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_address = coupler_from_rockettile_1_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_data = coupler_from_rockettile_1_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_c_bits_corrupt = coupler_from_rockettile_1_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_d_ready = coupler_from_rockettile_1_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_d_valid = coupler_from_rockettile_1_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_opcode = coupler_from_rockettile_1_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_param = coupler_from_rockettile_1_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferOut_d_bits_size = coupler_from_rockettile_1_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferOut_d_bits_source = coupler_from_rockettile_1_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_d_bits_sink = coupler_from_rockettile_1_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_d_bits_denied = coupler_from_rockettile_1_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferOut_d_bits_data = coupler_from_rockettile_1_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_1_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_e_ready = coupler_from_rockettile_1_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_e_valid = coupler_from_rockettile_1_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_tlOut_e_bits_sink = coupler_from_rockettile_1_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_a_ready = coupler_from_rockettile_1_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_valid = coupler_from_rockettile_1_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_opcode = coupler_from_rockettile_1_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_param = coupler_from_rockettile_1_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_size = coupler_from_rockettile_1_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_source = coupler_from_rockettile_1_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_address = coupler_from_rockettile_1_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_mask = coupler_from_rockettile_1_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_data = coupler_from_rockettile_1_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_a_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_b_ready = coupler_from_rockettile_1_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_b_valid = coupler_from_rockettile_1_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_b_bits_opcode = coupler_from_rockettile_1_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_param = coupler_from_rockettile_1_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferIn_b_bits_size = coupler_from_rockettile_1_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_b_bits_source = coupler_from_rockettile_1_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferIn_b_bits_address = coupler_from_rockettile_1_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_no_bufferIn_b_bits_mask = coupler_from_rockettile_1_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferIn_b_bits_data = coupler_from_rockettile_1_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_c_ready = coupler_from_rockettile_1_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_valid = coupler_from_rockettile_1_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_opcode = coupler_from_rockettile_1_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_param = coupler_from_rockettile_1_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_size = coupler_from_rockettile_1_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_source = coupler_from_rockettile_1_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_address = coupler_from_rockettile_1_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_data = coupler_from_rockettile_1_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_c_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_d_ready = coupler_from_rockettile_1_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_d_valid = coupler_from_rockettile_1_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_opcode = coupler_from_rockettile_1_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_param = coupler_from_rockettile_1_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_no_bufferIn_d_bits_size = coupler_from_rockettile_1_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_no_bufferIn_d_bits_source = coupler_from_rockettile_1_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_d_bits_sink = coupler_from_rockettile_1_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_d_bits_denied = coupler_from_rockettile_1_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_no_bufferIn_d_bits_data = coupler_from_rockettile_1_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_1_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_e_ready = coupler_from_rockettile_1_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_e_valid = coupler_from_rockettile_1_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlIn_e_bits_sink = coupler_from_rockettile_1_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_a_ready = coupler_from_rockettile_1_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_valid = coupler_from_rockettile_1_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_opcode = coupler_from_rockettile_1_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_param = coupler_from_rockettile_1_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_size = coupler_from_rockettile_1_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_source = coupler_from_rockettile_1_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_address = coupler_from_rockettile_1_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_mask = coupler_from_rockettile_1_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_data = coupler_from_rockettile_1_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_b_ready = coupler_from_rockettile_1_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_b_valid = coupler_from_rockettile_1_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_1_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_1_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_1_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_1_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_1_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_1_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_1_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_c_ready = coupler_from_rockettile_1_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_valid = coupler_from_rockettile_1_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_opcode = coupler_from_rockettile_1_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_param = coupler_from_rockettile_1_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_size = coupler_from_rockettile_1_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_source = coupler_from_rockettile_1_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_address = coupler_from_rockettile_1_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_data = coupler_from_rockettile_1_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_d_ready = coupler_from_rockettile_1_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_d_valid = coupler_from_rockettile_1_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_1_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_1_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_1_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_1_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_1_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_1_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_1_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_1_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_e_ready = coupler_from_rockettile_1_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_e_valid = coupler_from_rockettile_1_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_1_no_bufferOut_e_bits_sink = coupler_from_rockettile_1_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_a_ready = coupler_from_rockettile_1_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_valid = coupler_from_rockettile_1_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_b_ready = coupler_from_rockettile_1_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_valid = coupler_from_rockettile_1_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_c_ready = coupler_from_rockettile_1_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_valid = coupler_from_rockettile_1_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_d_ready = coupler_from_rockettile_1_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_valid = coupler_from_rockettile_1_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingIn_e_ready = coupler_from_rockettile_1_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_e_valid = coupler_from_rockettile_1_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_no_bufferIn_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_1_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_valid = coupler_from_rockettile_1_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_b_ready = coupler_from_rockettile_1_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_1_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_1_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_valid = coupler_from_rockettile_1_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_d_ready = coupler_from_rockettile_1_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_1_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_1_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_1_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_e_valid = coupler_from_rockettile_1_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_1_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_1_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_a_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_b_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_c_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_d_ready = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0 = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_2_tlMasterClockXingIn_e_valid = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_2_tlOut_a_ready = coupler_from_rockettile_2_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_valid = coupler_from_rockettile_2_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_opcode = coupler_from_rockettile_2_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_param = coupler_from_rockettile_2_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_size = coupler_from_rockettile_2_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_source = coupler_from_rockettile_2_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_address = coupler_from_rockettile_2_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_mask = coupler_from_rockettile_2_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_data = coupler_from_rockettile_2_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_a_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_b_ready = coupler_from_rockettile_2_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_b_valid = coupler_from_rockettile_2_auto_tl_out_b_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlOut_b_bits_opcode = coupler_from_rockettile_2_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_param = coupler_from_rockettile_2_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_2_tlOut_b_bits_size = coupler_from_rockettile_2_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlOut_b_bits_source = coupler_from_rockettile_2_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_2_tlOut_b_bits_address = coupler_from_rockettile_2_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_2_tlOut_b_bits_mask = coupler_from_rockettile_2_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_2_tlOut_b_bits_data = coupler_from_rockettile_2_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_b_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_c_ready = coupler_from_rockettile_2_auto_tl_out_c_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_valid = coupler_from_rockettile_2_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_opcode = coupler_from_rockettile_2_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_param = coupler_from_rockettile_2_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_size = coupler_from_rockettile_2_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_source = coupler_from_rockettile_2_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_address = coupler_from_rockettile_2_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_data = coupler_from_rockettile_2_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_c_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_d_ready = coupler_from_rockettile_2_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlOut_d_valid = coupler_from_rockettile_2_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_opcode = coupler_from_rockettile_2_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_param = coupler_from_rockettile_2_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_2_tlOut_d_bits_size = coupler_from_rockettile_2_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlOut_d_bits_source = coupler_from_rockettile_2_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlOut_d_bits_sink = coupler_from_rockettile_2_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_d_bits_denied = coupler_from_rockettile_2_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_2_tlOut_d_bits_data = coupler_from_rockettile_2_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_d_bits_corrupt = coupler_from_rockettile_2_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_e_ready = coupler_from_rockettile_2_auto_tl_out_e_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_e_valid = coupler_from_rockettile_2_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_2_e_bits_sink = coupler_from_rockettile_2_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_2_tlIn_a_ready = coupler_from_rockettile_2_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_valid = coupler_from_rockettile_2_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_opcode = coupler_from_rockettile_2_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_param = coupler_from_rockettile_2_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_size = coupler_from_rockettile_2_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_source = coupler_from_rockettile_2_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_address = coupler_from_rockettile_2_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_mask = coupler_from_rockettile_2_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_data = coupler_from_rockettile_2_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_2_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_b_ready = coupler_from_rockettile_2_tlOut_b_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_b_valid = coupler_from_rockettile_2_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlIn_b_bits_opcode = coupler_from_rockettile_2_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_param = coupler_from_rockettile_2_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlIn_b_bits_size = coupler_from_rockettile_2_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlIn_b_bits_source = coupler_from_rockettile_2_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_tlIn_b_bits_address = coupler_from_rockettile_2_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_tlIn_b_bits_mask = coupler_from_rockettile_2_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlIn_b_bits_data = coupler_from_rockettile_2_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_b_bits_corrupt = coupler_from_rockettile_2_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_c_ready = coupler_from_rockettile_2_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_valid = coupler_from_rockettile_2_tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_opcode = coupler_from_rockettile_2_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_param = coupler_from_rockettile_2_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_size = coupler_from_rockettile_2_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_source = coupler_from_rockettile_2_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_address = coupler_from_rockettile_2_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_data = coupler_from_rockettile_2_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_2_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_d_ready = coupler_from_rockettile_2_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_tlIn_d_valid = coupler_from_rockettile_2_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_opcode = coupler_from_rockettile_2_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_param = coupler_from_rockettile_2_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlIn_d_bits_size = coupler_from_rockettile_2_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlIn_d_bits_source = coupler_from_rockettile_2_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlIn_d_bits_sink = coupler_from_rockettile_2_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_d_bits_denied = coupler_from_rockettile_2_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlIn_d_bits_data = coupler_from_rockettile_2_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_d_bits_corrupt = coupler_from_rockettile_2_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_e_ready = coupler_from_rockettile_2_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_e_valid = coupler_from_rockettile_2_tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_out_e_bits_sink = coupler_from_rockettile_2_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_2_no_bufferOut_a_ready = coupler_from_rockettile_2_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_valid = coupler_from_rockettile_2_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_opcode = coupler_from_rockettile_2_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_param = coupler_from_rockettile_2_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_size = coupler_from_rockettile_2_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_source = coupler_from_rockettile_2_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_address = coupler_from_rockettile_2_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_mask = coupler_from_rockettile_2_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_data = coupler_from_rockettile_2_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_a_bits_corrupt = coupler_from_rockettile_2_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_b_ready = coupler_from_rockettile_2_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_b_valid = coupler_from_rockettile_2_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_b_bits_opcode = coupler_from_rockettile_2_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_param = coupler_from_rockettile_2_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferOut_b_bits_size = coupler_from_rockettile_2_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_b_bits_source = coupler_from_rockettile_2_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferOut_b_bits_address = coupler_from_rockettile_2_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_no_bufferOut_b_bits_mask = coupler_from_rockettile_2_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferOut_b_bits_data = coupler_from_rockettile_2_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_2_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_c_ready = coupler_from_rockettile_2_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_valid = coupler_from_rockettile_2_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_opcode = coupler_from_rockettile_2_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_param = coupler_from_rockettile_2_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_size = coupler_from_rockettile_2_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_source = coupler_from_rockettile_2_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_address = coupler_from_rockettile_2_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_data = coupler_from_rockettile_2_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_c_bits_corrupt = coupler_from_rockettile_2_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_d_ready = coupler_from_rockettile_2_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_d_valid = coupler_from_rockettile_2_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_opcode = coupler_from_rockettile_2_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_param = coupler_from_rockettile_2_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferOut_d_bits_size = coupler_from_rockettile_2_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferOut_d_bits_source = coupler_from_rockettile_2_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_d_bits_sink = coupler_from_rockettile_2_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_d_bits_denied = coupler_from_rockettile_2_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferOut_d_bits_data = coupler_from_rockettile_2_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_2_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_e_ready = coupler_from_rockettile_2_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_e_valid = coupler_from_rockettile_2_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_tlOut_e_bits_sink = coupler_from_rockettile_2_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_a_ready = coupler_from_rockettile_2_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_valid = coupler_from_rockettile_2_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_opcode = coupler_from_rockettile_2_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_param = coupler_from_rockettile_2_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_size = coupler_from_rockettile_2_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_source = coupler_from_rockettile_2_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_address = coupler_from_rockettile_2_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_mask = coupler_from_rockettile_2_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_data = coupler_from_rockettile_2_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_a_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_b_ready = coupler_from_rockettile_2_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_b_valid = coupler_from_rockettile_2_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_b_bits_opcode = coupler_from_rockettile_2_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_param = coupler_from_rockettile_2_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferIn_b_bits_size = coupler_from_rockettile_2_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_b_bits_source = coupler_from_rockettile_2_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferIn_b_bits_address = coupler_from_rockettile_2_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_no_bufferIn_b_bits_mask = coupler_from_rockettile_2_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferIn_b_bits_data = coupler_from_rockettile_2_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_c_ready = coupler_from_rockettile_2_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_valid = coupler_from_rockettile_2_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_opcode = coupler_from_rockettile_2_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_param = coupler_from_rockettile_2_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_size = coupler_from_rockettile_2_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_source = coupler_from_rockettile_2_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_address = coupler_from_rockettile_2_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_data = coupler_from_rockettile_2_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_c_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_d_ready = coupler_from_rockettile_2_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_d_valid = coupler_from_rockettile_2_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_opcode = coupler_from_rockettile_2_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_param = coupler_from_rockettile_2_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_no_bufferIn_d_bits_size = coupler_from_rockettile_2_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_no_bufferIn_d_bits_source = coupler_from_rockettile_2_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_d_bits_sink = coupler_from_rockettile_2_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_d_bits_denied = coupler_from_rockettile_2_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_no_bufferIn_d_bits_data = coupler_from_rockettile_2_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_2_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_e_ready = coupler_from_rockettile_2_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_e_valid = coupler_from_rockettile_2_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlIn_e_bits_sink = coupler_from_rockettile_2_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_a_ready = coupler_from_rockettile_2_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_valid = coupler_from_rockettile_2_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_opcode = coupler_from_rockettile_2_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_param = coupler_from_rockettile_2_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_size = coupler_from_rockettile_2_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_source = coupler_from_rockettile_2_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_address = coupler_from_rockettile_2_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_mask = coupler_from_rockettile_2_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_data = coupler_from_rockettile_2_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_b_ready = coupler_from_rockettile_2_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_b_valid = coupler_from_rockettile_2_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_2_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_2_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_2_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_2_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_2_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_2_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_2_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_c_ready = coupler_from_rockettile_2_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_valid = coupler_from_rockettile_2_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_opcode = coupler_from_rockettile_2_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_param = coupler_from_rockettile_2_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_size = coupler_from_rockettile_2_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_source = coupler_from_rockettile_2_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_address = coupler_from_rockettile_2_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_data = coupler_from_rockettile_2_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_d_ready = coupler_from_rockettile_2_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_d_valid = coupler_from_rockettile_2_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_2_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_2_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_2_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_2_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_2_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_2_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_2_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_2_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_e_ready = coupler_from_rockettile_2_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_e_valid = coupler_from_rockettile_2_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_2_no_bufferOut_e_bits_sink = coupler_from_rockettile_2_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_a_ready = coupler_from_rockettile_2_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_valid = coupler_from_rockettile_2_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_b_ready = coupler_from_rockettile_2_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_valid = coupler_from_rockettile_2_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_c_ready = coupler_from_rockettile_2_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_valid = coupler_from_rockettile_2_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_d_ready = coupler_from_rockettile_2_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_valid = coupler_from_rockettile_2_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingIn_e_ready = coupler_from_rockettile_2_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_e_valid = coupler_from_rockettile_2_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_no_bufferIn_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_2_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_valid = coupler_from_rockettile_2_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_b_ready = coupler_from_rockettile_2_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_2_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_2_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_valid = coupler_from_rockettile_2_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_d_ready = coupler_from_rockettile_2_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_2_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_2_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_2_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_e_valid = coupler_from_rockettile_2_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_2_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_2_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_a_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_b_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_c_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_address; // @[MixedNode.scala:551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_data; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_d_ready = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_ready; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0 = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready; // @[ClockDomain.scala:14:9]
wire coupler_from_rockettile_3_tlMasterClockXingIn_e_valid = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_valid; // @[MixedNode.scala:551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink = coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_from_rockettile_3_tlOut_a_ready = coupler_from_rockettile_3_auto_tl_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_valid = coupler_from_rockettile_3_auto_tl_out_a_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_opcode = coupler_from_rockettile_3_auto_tl_out_a_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_param = coupler_from_rockettile_3_auto_tl_out_a_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_size = coupler_from_rockettile_3_auto_tl_out_a_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_source = coupler_from_rockettile_3_auto_tl_out_a_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_address = coupler_from_rockettile_3_auto_tl_out_a_bits_address; // @[FIFOFixer.scala:50:9]
wire [7:0] coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_mask = coupler_from_rockettile_3_auto_tl_out_a_bits_mask; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_data = coupler_from_rockettile_3_auto_tl_out_a_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_a_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_b_ready = coupler_from_rockettile_3_auto_tl_out_b_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_b_valid = coupler_from_rockettile_3_auto_tl_out_b_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlOut_b_bits_opcode = coupler_from_rockettile_3_auto_tl_out_b_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_param = coupler_from_rockettile_3_auto_tl_out_b_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_3_tlOut_b_bits_size = coupler_from_rockettile_3_auto_tl_out_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlOut_b_bits_source = coupler_from_rockettile_3_auto_tl_out_b_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_3_tlOut_b_bits_address = coupler_from_rockettile_3_auto_tl_out_b_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_3_tlOut_b_bits_mask = coupler_from_rockettile_3_auto_tl_out_b_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_3_tlOut_b_bits_data = coupler_from_rockettile_3_auto_tl_out_b_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_b_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_c_ready = coupler_from_rockettile_3_auto_tl_out_c_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_valid = coupler_from_rockettile_3_auto_tl_out_c_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_opcode = coupler_from_rockettile_3_auto_tl_out_c_bits_opcode; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_param = coupler_from_rockettile_3_auto_tl_out_c_bits_param; // @[FIFOFixer.scala:50:9]
wire [3:0] coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_size = coupler_from_rockettile_3_auto_tl_out_c_bits_size; // @[FIFOFixer.scala:50:9]
wire [1:0] coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_source = coupler_from_rockettile_3_auto_tl_out_c_bits_source; // @[FIFOFixer.scala:50:9]
wire [31:0] coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_address = coupler_from_rockettile_3_auto_tl_out_c_bits_address; // @[FIFOFixer.scala:50:9]
wire [63:0] coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_data = coupler_from_rockettile_3_auto_tl_out_c_bits_data; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_c_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_d_ready = coupler_from_rockettile_3_auto_tl_out_d_ready; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlOut_d_valid = coupler_from_rockettile_3_auto_tl_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_opcode = coupler_from_rockettile_3_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_param = coupler_from_rockettile_3_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_3_tlOut_d_bits_size = coupler_from_rockettile_3_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlOut_d_bits_source = coupler_from_rockettile_3_auto_tl_out_d_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlOut_d_bits_sink = coupler_from_rockettile_3_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_d_bits_denied = coupler_from_rockettile_3_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_3_tlOut_d_bits_data = coupler_from_rockettile_3_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_d_bits_corrupt = coupler_from_rockettile_3_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_e_ready = coupler_from_rockettile_3_auto_tl_out_e_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_e_valid = coupler_from_rockettile_3_auto_tl_out_e_valid; // @[FIFOFixer.scala:50:9]
wire [2:0] coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign fixer_auto_anon_in_3_e_bits_sink = coupler_from_rockettile_3_auto_tl_out_e_bits_sink; // @[FIFOFixer.scala:50:9]
wire coupler_from_rockettile_3_tlIn_a_ready = coupler_from_rockettile_3_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_valid = coupler_from_rockettile_3_tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_opcode = coupler_from_rockettile_3_tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_param = coupler_from_rockettile_3_tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_size = coupler_from_rockettile_3_tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_source = coupler_from_rockettile_3_tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_address = coupler_from_rockettile_3_tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_mask = coupler_from_rockettile_3_tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_data = coupler_from_rockettile_3_tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_a_bits_corrupt = coupler_from_rockettile_3_tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_b_ready = coupler_from_rockettile_3_tlOut_b_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_b_valid = coupler_from_rockettile_3_tlOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlIn_b_bits_opcode = coupler_from_rockettile_3_tlOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_param = coupler_from_rockettile_3_tlOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlIn_b_bits_size = coupler_from_rockettile_3_tlOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlIn_b_bits_source = coupler_from_rockettile_3_tlOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_tlIn_b_bits_address = coupler_from_rockettile_3_tlOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_tlIn_b_bits_mask = coupler_from_rockettile_3_tlOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlIn_b_bits_data = coupler_from_rockettile_3_tlOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_b_bits_corrupt = coupler_from_rockettile_3_tlOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_c_ready = coupler_from_rockettile_3_tlOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_valid = coupler_from_rockettile_3_tlOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_opcode = coupler_from_rockettile_3_tlOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_param = coupler_from_rockettile_3_tlOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_size = coupler_from_rockettile_3_tlOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_source = coupler_from_rockettile_3_tlOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_address = coupler_from_rockettile_3_tlOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_data = coupler_from_rockettile_3_tlOut_c_bits_data; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_c_bits_corrupt = coupler_from_rockettile_3_tlOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_d_ready = coupler_from_rockettile_3_tlOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_tlIn_d_valid = coupler_from_rockettile_3_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_opcode = coupler_from_rockettile_3_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_param = coupler_from_rockettile_3_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlIn_d_bits_size = coupler_from_rockettile_3_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlIn_d_bits_source = coupler_from_rockettile_3_tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlIn_d_bits_sink = coupler_from_rockettile_3_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_d_bits_denied = coupler_from_rockettile_3_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlIn_d_bits_data = coupler_from_rockettile_3_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_d_bits_corrupt = coupler_from_rockettile_3_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_e_ready = coupler_from_rockettile_3_tlOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_e_valid = coupler_from_rockettile_3_tlOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_out_e_bits_sink = coupler_from_rockettile_3_tlOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_from_rockettile_3_no_bufferOut_a_ready = coupler_from_rockettile_3_tlIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_valid = coupler_from_rockettile_3_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_opcode = coupler_from_rockettile_3_tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_param = coupler_from_rockettile_3_tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_size = coupler_from_rockettile_3_tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_source = coupler_from_rockettile_3_tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_address = coupler_from_rockettile_3_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_mask = coupler_from_rockettile_3_tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_data = coupler_from_rockettile_3_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_a_bits_corrupt = coupler_from_rockettile_3_tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_b_ready = coupler_from_rockettile_3_tlIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_b_valid = coupler_from_rockettile_3_tlIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_b_bits_opcode = coupler_from_rockettile_3_tlIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_param = coupler_from_rockettile_3_tlIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferOut_b_bits_size = coupler_from_rockettile_3_tlIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_b_bits_source = coupler_from_rockettile_3_tlIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferOut_b_bits_address = coupler_from_rockettile_3_tlIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_no_bufferOut_b_bits_mask = coupler_from_rockettile_3_tlIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferOut_b_bits_data = coupler_from_rockettile_3_tlIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt = coupler_from_rockettile_3_tlIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_c_ready = coupler_from_rockettile_3_tlIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_valid = coupler_from_rockettile_3_tlIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_opcode = coupler_from_rockettile_3_tlIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_param = coupler_from_rockettile_3_tlIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_size = coupler_from_rockettile_3_tlIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_source = coupler_from_rockettile_3_tlIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_address = coupler_from_rockettile_3_tlIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_data = coupler_from_rockettile_3_tlIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_c_bits_corrupt = coupler_from_rockettile_3_tlIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_d_ready = coupler_from_rockettile_3_tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_d_valid = coupler_from_rockettile_3_tlIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_opcode = coupler_from_rockettile_3_tlIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_param = coupler_from_rockettile_3_tlIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferOut_d_bits_size = coupler_from_rockettile_3_tlIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferOut_d_bits_source = coupler_from_rockettile_3_tlIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_d_bits_sink = coupler_from_rockettile_3_tlIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_d_bits_denied = coupler_from_rockettile_3_tlIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferOut_d_bits_data = coupler_from_rockettile_3_tlIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt = coupler_from_rockettile_3_tlIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_e_ready = coupler_from_rockettile_3_tlIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_e_valid = coupler_from_rockettile_3_tlIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_tlOut_e_bits_sink = coupler_from_rockettile_3_tlIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_a_ready = coupler_from_rockettile_3_no_bufferOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_valid = coupler_from_rockettile_3_no_bufferOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_opcode = coupler_from_rockettile_3_no_bufferOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_param = coupler_from_rockettile_3_no_bufferOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_size = coupler_from_rockettile_3_no_bufferOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_source = coupler_from_rockettile_3_no_bufferOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_address = coupler_from_rockettile_3_no_bufferOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_mask = coupler_from_rockettile_3_no_bufferOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_data = coupler_from_rockettile_3_no_bufferOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_a_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_b_ready = coupler_from_rockettile_3_no_bufferOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_b_valid = coupler_from_rockettile_3_no_bufferOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_b_bits_opcode = coupler_from_rockettile_3_no_bufferOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_param = coupler_from_rockettile_3_no_bufferOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferIn_b_bits_size = coupler_from_rockettile_3_no_bufferOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_b_bits_source = coupler_from_rockettile_3_no_bufferOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferIn_b_bits_address = coupler_from_rockettile_3_no_bufferOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_no_bufferIn_b_bits_mask = coupler_from_rockettile_3_no_bufferOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferIn_b_bits_data = coupler_from_rockettile_3_no_bufferOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_c_ready = coupler_from_rockettile_3_no_bufferOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_valid = coupler_from_rockettile_3_no_bufferOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_opcode = coupler_from_rockettile_3_no_bufferOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_param = coupler_from_rockettile_3_no_bufferOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_size = coupler_from_rockettile_3_no_bufferOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_source = coupler_from_rockettile_3_no_bufferOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_address = coupler_from_rockettile_3_no_bufferOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_data = coupler_from_rockettile_3_no_bufferOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_c_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_d_ready = coupler_from_rockettile_3_no_bufferOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_d_valid = coupler_from_rockettile_3_no_bufferOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_opcode = coupler_from_rockettile_3_no_bufferOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_param = coupler_from_rockettile_3_no_bufferOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_no_bufferIn_d_bits_size = coupler_from_rockettile_3_no_bufferOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_no_bufferIn_d_bits_source = coupler_from_rockettile_3_no_bufferOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_d_bits_sink = coupler_from_rockettile_3_no_bufferOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_d_bits_denied = coupler_from_rockettile_3_no_bufferOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_no_bufferIn_d_bits_data = coupler_from_rockettile_3_no_bufferOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt = coupler_from_rockettile_3_no_bufferOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_e_ready = coupler_from_rockettile_3_no_bufferOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_e_valid = coupler_from_rockettile_3_no_bufferOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlIn_e_bits_sink = coupler_from_rockettile_3_no_bufferOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_a_ready = coupler_from_rockettile_3_no_bufferIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_valid = coupler_from_rockettile_3_no_bufferIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_opcode = coupler_from_rockettile_3_no_bufferIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_param = coupler_from_rockettile_3_no_bufferIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_size = coupler_from_rockettile_3_no_bufferIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_source = coupler_from_rockettile_3_no_bufferIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_address = coupler_from_rockettile_3_no_bufferIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_mask = coupler_from_rockettile_3_no_bufferIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_data = coupler_from_rockettile_3_no_bufferIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_a_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_b_ready = coupler_from_rockettile_3_no_bufferIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_b_valid = coupler_from_rockettile_3_no_bufferIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode = coupler_from_rockettile_3_no_bufferIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param = coupler_from_rockettile_3_no_bufferIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size = coupler_from_rockettile_3_no_bufferIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source = coupler_from_rockettile_3_no_bufferIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address = coupler_from_rockettile_3_no_bufferIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [7:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask = coupler_from_rockettile_3_no_bufferIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data = coupler_from_rockettile_3_no_bufferIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_c_ready = coupler_from_rockettile_3_no_bufferIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_valid = coupler_from_rockettile_3_no_bufferIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_opcode = coupler_from_rockettile_3_no_bufferIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_param = coupler_from_rockettile_3_no_bufferIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_size = coupler_from_rockettile_3_no_bufferIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_source = coupler_from_rockettile_3_no_bufferIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_address = coupler_from_rockettile_3_no_bufferIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_data = coupler_from_rockettile_3_no_bufferIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_c_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_d_ready = coupler_from_rockettile_3_no_bufferIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_d_valid = coupler_from_rockettile_3_no_bufferIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode = coupler_from_rockettile_3_no_bufferIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param = coupler_from_rockettile_3_no_bufferIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size = coupler_from_rockettile_3_no_bufferIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source = coupler_from_rockettile_3_no_bufferIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink = coupler_from_rockettile_3_no_bufferIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied = coupler_from_rockettile_3_no_bufferIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data = coupler_from_rockettile_3_no_bufferIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt = coupler_from_rockettile_3_no_bufferIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_e_ready = coupler_from_rockettile_3_no_bufferIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_e_valid = coupler_from_rockettile_3_no_bufferIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign coupler_from_rockettile_3_no_bufferOut_e_bits_sink = coupler_from_rockettile_3_no_bufferIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_a_ready = coupler_from_rockettile_3_tlMasterClockXingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_valid = coupler_from_rockettile_3_tlMasterClockXingOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_b_ready = coupler_from_rockettile_3_tlMasterClockXingOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_valid = coupler_from_rockettile_3_tlMasterClockXingOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_c_ready = coupler_from_rockettile_3_tlMasterClockXingOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_valid = coupler_from_rockettile_3_tlMasterClockXingOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_d_ready = coupler_from_rockettile_3_tlMasterClockXingOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_valid = coupler_from_rockettile_3_tlMasterClockXingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingIn_e_ready = coupler_from_rockettile_3_tlMasterClockXingOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_e_valid = coupler_from_rockettile_3_tlMasterClockXingOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_no_bufferIn_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_a_ready = coupler_from_rockettile_3_tlMasterClockXingIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_valid = coupler_from_rockettile_3_tlMasterClockXingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_a_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_b_ready = coupler_from_rockettile_3_tlMasterClockXingIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_valid = coupler_from_rockettile_3_tlMasterClockXingIn_b_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_address; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_mask = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_mask; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_b_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_c_ready = coupler_from_rockettile_3_tlMasterClockXingIn_c_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_valid = coupler_from_rockettile_3_tlMasterClockXingIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_address = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_c_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_d_ready = coupler_from_rockettile_3_tlMasterClockXingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_valid = coupler_from_rockettile_3_tlMasterClockXingIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_opcode = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_param = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_size = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_source = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_denied = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_data = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_d_bits_corrupt = coupler_from_rockettile_3_tlMasterClockXingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_auto_tl_master_clock_xing_in_e_ready = coupler_from_rockettile_3_tlMasterClockXingIn_e_ready; // @[MixedNode.scala:551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_e_valid = coupler_from_rockettile_3_tlMasterClockXingIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_from_rockettile_3_tlMasterClockXingOut_e_bits_sink = coupler_from_rockettile_3_tlMasterClockXingIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire fixer__T_1 = fixer_a_first & fixer__a_first_T; // @[Decoupled.scala:51:35]
wire fixer__T_3 = fixer_d_first & fixer__T_2; // @[Decoupled.scala:51:35]
wire fixer__T_17 = fixer_a_first_1 & fixer__a_first_T_1; // @[Decoupled.scala:51:35]
wire fixer__T_19 = fixer_d_first_1 & fixer__T_18; // @[Decoupled.scala:51:35]
wire fixer__T_33 = fixer_a_first_2 & fixer__a_first_T_2; // @[Decoupled.scala:51:35]
wire fixer__T_35 = fixer_d_first_2 & fixer__T_34; // @[Decoupled.scala:51:35]
wire fixer__T_49 = fixer_a_first_3 & fixer__a_first_T_3; // @[Decoupled.scala:51:35]
wire fixer__T_51 = fixer_d_first_3 & fixer__T_50; // @[Decoupled.scala:51:35]
always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31]
if (childReset) begin // @[LazyModuleImp.scala:155:31, :158:31]
fixer_a_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed <= 3'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_1 <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_1_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_1_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_1 <= 3'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_2 <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_2 <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_2_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_2_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_2 <= 3'h0; // @[FIFOFixer.scala:115:35]
fixer_a_first_counter_3 <= 9'h0; // @[Edges.scala:229:27]
fixer_d_first_counter_3 <= 9'h0; // @[Edges.scala:229:27]
fixer_flight_3_0 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3_1 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_flight_3_2 <= 1'h0; // @[FIFOFixer.scala:79:27]
fixer_SourceIdFIFOed_3 <= 3'h0; // @[FIFOFixer.scala:115:35]
end
else begin // @[LazyModuleImp.scala:155:31]
if (fixer__a_first_T) // @[Decoupled.scala:51:35]
fixer_a_first_counter <= fixer__a_first_counter_T; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T) // @[Decoupled.scala:51:35]
fixer_d_first_counter <= fixer__d_first_counter_T; // @[Edges.scala:229:27, :236:21]
fixer_flight_0 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h0) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h0 ? fixer__flight_T : fixer_flight_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h1) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h1 ? fixer__flight_T : fixer_flight_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2 <= ~(fixer__T_3 & fixer_anonIn_d_bits_source == 2'h2) & (fixer__T_1 & fixer_anonIn_a_bits_source == 2'h2 ? fixer__flight_T : fixer_flight_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed <= fixer__SourceIdFIFOed_T; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_1) // @[Decoupled.scala:51:35]
fixer_a_first_counter_1 <= fixer__a_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_2) // @[Decoupled.scala:51:35]
fixer_d_first_counter_1 <= fixer__d_first_counter_T_1; // @[Edges.scala:229:27, :236:21]
fixer_flight_1_0 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h0) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h0 ? fixer__flight_T_1 : fixer_flight_1_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_1 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h1) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h1 ? fixer__flight_T_1 : fixer_flight_1_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_1_2 <= ~(fixer__T_19 & fixer_x1_anonIn_d_bits_source == 2'h2) & (fixer__T_17 & fixer_x1_anonIn_a_bits_source == 2'h2 ? fixer__flight_T_1 : fixer_flight_1_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_1 <= fixer__SourceIdFIFOed_T_1; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_2) // @[Decoupled.scala:51:35]
fixer_a_first_counter_2 <= fixer__a_first_counter_T_2; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_4) // @[Decoupled.scala:51:35]
fixer_d_first_counter_2 <= fixer__d_first_counter_T_2; // @[Edges.scala:229:27, :236:21]
fixer_flight_2_0 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h0) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h0 ? fixer__flight_T_2 : fixer_flight_2_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2_1 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h1) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h1 ? fixer__flight_T_2 : fixer_flight_2_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_2_2 <= ~(fixer__T_35 & fixer_x1_anonIn_1_d_bits_source == 2'h2) & (fixer__T_33 & fixer_x1_anonIn_1_a_bits_source == 2'h2 ? fixer__flight_T_2 : fixer_flight_2_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_2 <= fixer__SourceIdFIFOed_T_2; // @[FIFOFixer.scala:115:35, :126:40]
if (fixer__a_first_T_3) // @[Decoupled.scala:51:35]
fixer_a_first_counter_3 <= fixer__a_first_counter_T_3; // @[Edges.scala:229:27, :236:21]
if (fixer__d_first_T_6) // @[Decoupled.scala:51:35]
fixer_d_first_counter_3 <= fixer__d_first_counter_T_3; // @[Edges.scala:229:27, :236:21]
fixer_flight_3_0 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h0) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h0 ? fixer__flight_T_3 : fixer_flight_3_0); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_3_1 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h1) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h1 ? fixer__flight_T_3 : fixer_flight_3_1); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_flight_3_2 <= ~(fixer__T_51 & fixer_x1_anonIn_2_d_bits_source == 2'h2) & (fixer__T_49 & fixer_x1_anonIn_2_a_bits_source == 2'h2 ? fixer__flight_T_3 : fixer_flight_3_2); // @[FIFOFixer.scala:79:27, :80:{21,35,62,65}, :81:{21,35,62}]
fixer_SourceIdFIFOed_3 <= fixer__SourceIdFIFOed_T_3; // @[FIFOFixer.scala:115:35, :126:40]
end
always @(posedge)
FixedClockBroadcast_7_2 fixedClockNode ( // @[ClockGroup.scala:115:114]
.auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9]
.auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9]
.auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0),
.auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0),
.auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0),
.auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0),
.auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0),
.auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0),
.auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0),
.auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0),
.auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0),
.auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0),
.auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0),
.auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0),
.auto_anon_out_0_clock (clockSinkNodeIn_clock),
.auto_anon_out_0_reset (clockSinkNodeIn_reset)
); // @[ClockGroup.scala:115:114]
TLXbar_csbus1_i4_o1_a32d64s4k3z4c system_bus_xbar ( // @[SystemBus.scala:47:43]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_3_a_ready (fixer_auto_anon_out_3_a_ready),
.auto_anon_in_3_a_valid (fixer_auto_anon_out_3_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_opcode (fixer_auto_anon_out_3_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_param (fixer_auto_anon_out_3_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_size (fixer_auto_anon_out_3_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_source (fixer_auto_anon_out_3_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_address (fixer_auto_anon_out_3_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_mask (fixer_auto_anon_out_3_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_data (fixer_auto_anon_out_3_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_a_bits_corrupt (fixer_auto_anon_out_3_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_b_ready (fixer_auto_anon_out_3_b_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_b_valid (fixer_auto_anon_out_3_b_valid),
.auto_anon_in_3_b_bits_opcode (fixer_auto_anon_out_3_b_bits_opcode),
.auto_anon_in_3_b_bits_param (fixer_auto_anon_out_3_b_bits_param),
.auto_anon_in_3_b_bits_size (fixer_auto_anon_out_3_b_bits_size),
.auto_anon_in_3_b_bits_source (fixer_auto_anon_out_3_b_bits_source),
.auto_anon_in_3_b_bits_address (fixer_auto_anon_out_3_b_bits_address),
.auto_anon_in_3_b_bits_mask (fixer_auto_anon_out_3_b_bits_mask),
.auto_anon_in_3_b_bits_data (fixer_auto_anon_out_3_b_bits_data),
.auto_anon_in_3_b_bits_corrupt (fixer_auto_anon_out_3_b_bits_corrupt),
.auto_anon_in_3_c_ready (fixer_auto_anon_out_3_c_ready),
.auto_anon_in_3_c_valid (fixer_auto_anon_out_3_c_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_opcode (fixer_auto_anon_out_3_c_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_param (fixer_auto_anon_out_3_c_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_size (fixer_auto_anon_out_3_c_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_source (fixer_auto_anon_out_3_c_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_address (fixer_auto_anon_out_3_c_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_data (fixer_auto_anon_out_3_c_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_c_bits_corrupt (fixer_auto_anon_out_3_c_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_d_ready (fixer_auto_anon_out_3_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_d_valid (fixer_auto_anon_out_3_d_valid),
.auto_anon_in_3_d_bits_opcode (fixer_auto_anon_out_3_d_bits_opcode),
.auto_anon_in_3_d_bits_param (fixer_auto_anon_out_3_d_bits_param),
.auto_anon_in_3_d_bits_size (fixer_auto_anon_out_3_d_bits_size),
.auto_anon_in_3_d_bits_source (fixer_auto_anon_out_3_d_bits_source),
.auto_anon_in_3_d_bits_sink (fixer_auto_anon_out_3_d_bits_sink),
.auto_anon_in_3_d_bits_denied (fixer_auto_anon_out_3_d_bits_denied),
.auto_anon_in_3_d_bits_data (fixer_auto_anon_out_3_d_bits_data),
.auto_anon_in_3_d_bits_corrupt (fixer_auto_anon_out_3_d_bits_corrupt),
.auto_anon_in_3_e_ready (fixer_auto_anon_out_3_e_ready),
.auto_anon_in_3_e_valid (fixer_auto_anon_out_3_e_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_3_e_bits_sink (fixer_auto_anon_out_3_e_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_ready (fixer_auto_anon_out_2_a_ready),
.auto_anon_in_2_a_valid (fixer_auto_anon_out_2_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_opcode (fixer_auto_anon_out_2_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_param (fixer_auto_anon_out_2_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_size (fixer_auto_anon_out_2_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_source (fixer_auto_anon_out_2_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_address (fixer_auto_anon_out_2_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_mask (fixer_auto_anon_out_2_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_data (fixer_auto_anon_out_2_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_a_bits_corrupt (fixer_auto_anon_out_2_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_b_ready (fixer_auto_anon_out_2_b_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_b_valid (fixer_auto_anon_out_2_b_valid),
.auto_anon_in_2_b_bits_opcode (fixer_auto_anon_out_2_b_bits_opcode),
.auto_anon_in_2_b_bits_param (fixer_auto_anon_out_2_b_bits_param),
.auto_anon_in_2_b_bits_size (fixer_auto_anon_out_2_b_bits_size),
.auto_anon_in_2_b_bits_source (fixer_auto_anon_out_2_b_bits_source),
.auto_anon_in_2_b_bits_address (fixer_auto_anon_out_2_b_bits_address),
.auto_anon_in_2_b_bits_mask (fixer_auto_anon_out_2_b_bits_mask),
.auto_anon_in_2_b_bits_data (fixer_auto_anon_out_2_b_bits_data),
.auto_anon_in_2_b_bits_corrupt (fixer_auto_anon_out_2_b_bits_corrupt),
.auto_anon_in_2_c_ready (fixer_auto_anon_out_2_c_ready),
.auto_anon_in_2_c_valid (fixer_auto_anon_out_2_c_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_opcode (fixer_auto_anon_out_2_c_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_param (fixer_auto_anon_out_2_c_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_size (fixer_auto_anon_out_2_c_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_source (fixer_auto_anon_out_2_c_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_address (fixer_auto_anon_out_2_c_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_data (fixer_auto_anon_out_2_c_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_c_bits_corrupt (fixer_auto_anon_out_2_c_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_d_ready (fixer_auto_anon_out_2_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_d_valid (fixer_auto_anon_out_2_d_valid),
.auto_anon_in_2_d_bits_opcode (fixer_auto_anon_out_2_d_bits_opcode),
.auto_anon_in_2_d_bits_param (fixer_auto_anon_out_2_d_bits_param),
.auto_anon_in_2_d_bits_size (fixer_auto_anon_out_2_d_bits_size),
.auto_anon_in_2_d_bits_source (fixer_auto_anon_out_2_d_bits_source),
.auto_anon_in_2_d_bits_sink (fixer_auto_anon_out_2_d_bits_sink),
.auto_anon_in_2_d_bits_denied (fixer_auto_anon_out_2_d_bits_denied),
.auto_anon_in_2_d_bits_data (fixer_auto_anon_out_2_d_bits_data),
.auto_anon_in_2_d_bits_corrupt (fixer_auto_anon_out_2_d_bits_corrupt),
.auto_anon_in_2_e_ready (fixer_auto_anon_out_2_e_ready),
.auto_anon_in_2_e_valid (fixer_auto_anon_out_2_e_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_2_e_bits_sink (fixer_auto_anon_out_2_e_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_ready (fixer_auto_anon_out_1_a_ready),
.auto_anon_in_1_a_valid (fixer_auto_anon_out_1_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_opcode (fixer_auto_anon_out_1_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_param (fixer_auto_anon_out_1_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_size (fixer_auto_anon_out_1_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_source (fixer_auto_anon_out_1_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_address (fixer_auto_anon_out_1_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_mask (fixer_auto_anon_out_1_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_data (fixer_auto_anon_out_1_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_a_bits_corrupt (fixer_auto_anon_out_1_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_b_ready (fixer_auto_anon_out_1_b_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_b_valid (fixer_auto_anon_out_1_b_valid),
.auto_anon_in_1_b_bits_opcode (fixer_auto_anon_out_1_b_bits_opcode),
.auto_anon_in_1_b_bits_param (fixer_auto_anon_out_1_b_bits_param),
.auto_anon_in_1_b_bits_size (fixer_auto_anon_out_1_b_bits_size),
.auto_anon_in_1_b_bits_source (fixer_auto_anon_out_1_b_bits_source),
.auto_anon_in_1_b_bits_address (fixer_auto_anon_out_1_b_bits_address),
.auto_anon_in_1_b_bits_mask (fixer_auto_anon_out_1_b_bits_mask),
.auto_anon_in_1_b_bits_data (fixer_auto_anon_out_1_b_bits_data),
.auto_anon_in_1_b_bits_corrupt (fixer_auto_anon_out_1_b_bits_corrupt),
.auto_anon_in_1_c_ready (fixer_auto_anon_out_1_c_ready),
.auto_anon_in_1_c_valid (fixer_auto_anon_out_1_c_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_opcode (fixer_auto_anon_out_1_c_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_param (fixer_auto_anon_out_1_c_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_size (fixer_auto_anon_out_1_c_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_source (fixer_auto_anon_out_1_c_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_address (fixer_auto_anon_out_1_c_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_data (fixer_auto_anon_out_1_c_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_c_bits_corrupt (fixer_auto_anon_out_1_c_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_ready (fixer_auto_anon_out_1_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_d_valid (fixer_auto_anon_out_1_d_valid),
.auto_anon_in_1_d_bits_opcode (fixer_auto_anon_out_1_d_bits_opcode),
.auto_anon_in_1_d_bits_param (fixer_auto_anon_out_1_d_bits_param),
.auto_anon_in_1_d_bits_size (fixer_auto_anon_out_1_d_bits_size),
.auto_anon_in_1_d_bits_source (fixer_auto_anon_out_1_d_bits_source),
.auto_anon_in_1_d_bits_sink (fixer_auto_anon_out_1_d_bits_sink),
.auto_anon_in_1_d_bits_denied (fixer_auto_anon_out_1_d_bits_denied),
.auto_anon_in_1_d_bits_data (fixer_auto_anon_out_1_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (fixer_auto_anon_out_1_d_bits_corrupt),
.auto_anon_in_1_e_ready (fixer_auto_anon_out_1_e_ready),
.auto_anon_in_1_e_valid (fixer_auto_anon_out_1_e_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_1_e_bits_sink (fixer_auto_anon_out_1_e_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_ready (fixer_auto_anon_out_0_a_ready),
.auto_anon_in_0_a_valid (fixer_auto_anon_out_0_a_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_opcode (fixer_auto_anon_out_0_a_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_param (fixer_auto_anon_out_0_a_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_size (fixer_auto_anon_out_0_a_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_source (fixer_auto_anon_out_0_a_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_address (fixer_auto_anon_out_0_a_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_mask (fixer_auto_anon_out_0_a_bits_mask), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_data (fixer_auto_anon_out_0_a_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_a_bits_corrupt (fixer_auto_anon_out_0_a_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_b_ready (fixer_auto_anon_out_0_b_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_b_valid (fixer_auto_anon_out_0_b_valid),
.auto_anon_in_0_b_bits_opcode (fixer_auto_anon_out_0_b_bits_opcode),
.auto_anon_in_0_b_bits_param (fixer_auto_anon_out_0_b_bits_param),
.auto_anon_in_0_b_bits_size (fixer_auto_anon_out_0_b_bits_size),
.auto_anon_in_0_b_bits_source (fixer_auto_anon_out_0_b_bits_source),
.auto_anon_in_0_b_bits_address (fixer_auto_anon_out_0_b_bits_address),
.auto_anon_in_0_b_bits_mask (fixer_auto_anon_out_0_b_bits_mask),
.auto_anon_in_0_b_bits_data (fixer_auto_anon_out_0_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (fixer_auto_anon_out_0_b_bits_corrupt),
.auto_anon_in_0_c_ready (fixer_auto_anon_out_0_c_ready),
.auto_anon_in_0_c_valid (fixer_auto_anon_out_0_c_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_opcode (fixer_auto_anon_out_0_c_bits_opcode), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_param (fixer_auto_anon_out_0_c_bits_param), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_size (fixer_auto_anon_out_0_c_bits_size), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_source (fixer_auto_anon_out_0_c_bits_source), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_address (fixer_auto_anon_out_0_c_bits_address), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_data (fixer_auto_anon_out_0_c_bits_data), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_c_bits_corrupt (fixer_auto_anon_out_0_c_bits_corrupt), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_ready (fixer_auto_anon_out_0_d_ready), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_d_valid (fixer_auto_anon_out_0_d_valid),
.auto_anon_in_0_d_bits_opcode (fixer_auto_anon_out_0_d_bits_opcode),
.auto_anon_in_0_d_bits_param (fixer_auto_anon_out_0_d_bits_param),
.auto_anon_in_0_d_bits_size (fixer_auto_anon_out_0_d_bits_size),
.auto_anon_in_0_d_bits_source (fixer_auto_anon_out_0_d_bits_source),
.auto_anon_in_0_d_bits_sink (fixer_auto_anon_out_0_d_bits_sink),
.auto_anon_in_0_d_bits_denied (fixer_auto_anon_out_0_d_bits_denied),
.auto_anon_in_0_d_bits_data (fixer_auto_anon_out_0_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (fixer_auto_anon_out_0_d_bits_corrupt),
.auto_anon_in_0_e_ready (fixer_auto_anon_out_0_e_ready),
.auto_anon_in_0_e_valid (fixer_auto_anon_out_0_e_valid), // @[FIFOFixer.scala:50:9]
.auto_anon_in_0_e_bits_sink (fixer_auto_anon_out_0_e_bits_sink), // @[FIFOFixer.scala:50:9]
.auto_anon_out_a_ready (auto_system_bus_xbar_anon_out_a_ready_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_a_valid (auto_system_bus_xbar_anon_out_a_valid_0),
.auto_anon_out_a_bits_opcode (auto_system_bus_xbar_anon_out_a_bits_opcode_0),
.auto_anon_out_a_bits_param (auto_system_bus_xbar_anon_out_a_bits_param_0),
.auto_anon_out_a_bits_size (auto_system_bus_xbar_anon_out_a_bits_size_0),
.auto_anon_out_a_bits_source (auto_system_bus_xbar_anon_out_a_bits_source_0),
.auto_anon_out_a_bits_address (auto_system_bus_xbar_anon_out_a_bits_address_0),
.auto_anon_out_a_bits_mask (auto_system_bus_xbar_anon_out_a_bits_mask_0),
.auto_anon_out_a_bits_data (auto_system_bus_xbar_anon_out_a_bits_data_0),
.auto_anon_out_a_bits_corrupt (auto_system_bus_xbar_anon_out_a_bits_corrupt_0),
.auto_anon_out_b_ready (auto_system_bus_xbar_anon_out_b_ready_0),
.auto_anon_out_b_valid (auto_system_bus_xbar_anon_out_b_valid_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_opcode (auto_system_bus_xbar_anon_out_b_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_param (auto_system_bus_xbar_anon_out_b_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_size (auto_system_bus_xbar_anon_out_b_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_source (auto_system_bus_xbar_anon_out_b_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_address (auto_system_bus_xbar_anon_out_b_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_mask (auto_system_bus_xbar_anon_out_b_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_data (auto_system_bus_xbar_anon_out_b_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_b_bits_corrupt (auto_system_bus_xbar_anon_out_b_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_c_ready (auto_system_bus_xbar_anon_out_c_ready_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_c_valid (auto_system_bus_xbar_anon_out_c_valid_0),
.auto_anon_out_c_bits_opcode (auto_system_bus_xbar_anon_out_c_bits_opcode_0),
.auto_anon_out_c_bits_param (auto_system_bus_xbar_anon_out_c_bits_param_0),
.auto_anon_out_c_bits_size (auto_system_bus_xbar_anon_out_c_bits_size_0),
.auto_anon_out_c_bits_source (auto_system_bus_xbar_anon_out_c_bits_source_0),
.auto_anon_out_c_bits_address (auto_system_bus_xbar_anon_out_c_bits_address_0),
.auto_anon_out_c_bits_data (auto_system_bus_xbar_anon_out_c_bits_data_0),
.auto_anon_out_c_bits_corrupt (auto_system_bus_xbar_anon_out_c_bits_corrupt_0),
.auto_anon_out_d_ready (auto_system_bus_xbar_anon_out_d_ready_0),
.auto_anon_out_d_valid (auto_system_bus_xbar_anon_out_d_valid_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_opcode (auto_system_bus_xbar_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_param (auto_system_bus_xbar_anon_out_d_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_size (auto_system_bus_xbar_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_source (auto_system_bus_xbar_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_sink (auto_system_bus_xbar_anon_out_d_bits_sink_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_denied (auto_system_bus_xbar_anon_out_d_bits_denied_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_data (auto_system_bus_xbar_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_d_bits_corrupt (auto_system_bus_xbar_anon_out_d_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_e_ready (auto_system_bus_xbar_anon_out_e_ready_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_e_valid (auto_system_bus_xbar_anon_out_e_valid_0),
.auto_anon_out_e_bits_sink (auto_system_bus_xbar_anon_out_e_bits_sink_0)
); // @[SystemBus.scala:47:43]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_3_e_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_2_e_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_1_e_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_b_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready = auto_coupler_from_rockettile_tl_master_clock_xing_in_0_e_ready_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_valid = auto_system_bus_xbar_anon_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_opcode = auto_system_bus_xbar_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_param = auto_system_bus_xbar_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_size = auto_system_bus_xbar_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_source = auto_system_bus_xbar_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_address = auto_system_bus_xbar_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_mask = auto_system_bus_xbar_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_data = auto_system_bus_xbar_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_a_bits_corrupt = auto_system_bus_xbar_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_b_ready = auto_system_bus_xbar_anon_out_b_ready_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_valid = auto_system_bus_xbar_anon_out_c_valid_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_opcode = auto_system_bus_xbar_anon_out_c_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_param = auto_system_bus_xbar_anon_out_c_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_size = auto_system_bus_xbar_anon_out_c_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_source = auto_system_bus_xbar_anon_out_c_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_address = auto_system_bus_xbar_anon_out_c_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_data = auto_system_bus_xbar_anon_out_c_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_c_bits_corrupt = auto_system_bus_xbar_anon_out_c_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_d_ready = auto_system_bus_xbar_anon_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_e_valid = auto_system_bus_xbar_anon_out_e_valid_0; // @[ClockDomain.scala:14:9]
assign auto_system_bus_xbar_anon_out_e_bits_sink = auto_system_bus_xbar_anon_out_e_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9]
assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
| module MSHR_1( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [7:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 8'hA0; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28] |
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
| module InputUnit_120( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_2_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_9, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [9:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_9; // @[InputUnit.scala:266:32]
wire vcalloc_vals_8; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_8_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_8_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_8_g; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg states_8_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_8_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_8_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_8_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_9_g; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_2_9; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_1_9; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_8_valid = states_8_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [9:0] mask; // @[InputUnit.scala:250:21]
wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, vcalloc_vals_8, 8'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : vcalloc_vals_8 ? 20'h40000 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_8 | vcalloc_vals_9; // @[package.scala:81:59]
assign vcalloc_vals_8 = states_8_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[8]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_339( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerShiftReg_w1_d3_i0_95( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_159 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File rob.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Re-order Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Bank the ROB, such that each "dispatch" group gets its own row of the ROB,
// and each instruction in the dispatch group goes to a different bank.
// We can compress out the PC by only saving the high-order bits!
//
// ASSUMPTIONS:
// - dispatch groups are aligned to the PC.
//
// NOTES:
// - Currently we do not compress out bubbles in the ROB.
// - Exceptions are only taken when at the head of the commit bundle --
// this helps deal with loads, stores, and refetch instructions.
package boom.v4.exu
import scala.math.ceil
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import boom.v4.common._
import boom.v4.util._
/**
* IO bundle to interact with the ROB
*
* @param numWakeupPorts number of wakeup ports to the rob
* @param numFpuPorts number of fpu ports that will write back fflags
*/
class RobIo(
val numWakeupPorts: Int
)(implicit p: Parameters) extends BoomBundle
{
// Decode Stage
// (Allocate, write instruction to ROB).
val enq_valids = Input(Vec(coreWidth, Bool()))
val enq_uops = Input(Vec(coreWidth, new MicroOp()))
val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,
// and stalling on the rest of it (don't
// advance the tail ptr)
val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))
val rob_tail_idx = Output(UInt(robAddrSz.W))
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
// Handle Branch Misspeculations
val brupdate = Input(new BrUpdateInfo())
// Write-back Stage
// (Update of ROB)
// Instruction is no longer busy and can be committed
val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))
// Unbusying ports for stores.
val lsu_clr_bsy = Input(Vec(coreWidth, Valid(UInt(robAddrSz.W))))
// Port for unmarking loads/stores as speculation hazards..
val lsu_clr_unsafe = Input(Vec(lsuWidth, Valid(UInt(robAddrSz.W))))
val lxcpt = Flipped(new ValidIO(new Exception())) // LSU
val csr_replay = Input(Valid(new Exception()))
// Commit stage (free resources).
val commit = Output(new CommitSignals())
val rollback = Bool()
// tell the LSU that the head of the ROB is a load
// (some loads can only execute once they are at the head of the ROB).
val com_load_is_at_rob_head = Output(Bool())
// Communicate exceptions to the CSRFile
val com_xcpt = Valid(new CommitExceptionSignals())
// Let the CSRFile stall us (e.g., wfi).
val csr_stall = Input(Bool())
// Flush signals (including exceptions, pipeline replays, and memory ordering failures)
// to send to the frontend for redirection.
val flush = Valid(new CommitExceptionSignals)
// Stall Decode as appropriate
val empty = Output(Bool())
val ready = Output(Bool()) // ROB is busy unrolling rename state...
// Stall the frontend if we know we will redirect the PC
val flush_frontend = Output(Bool())
val debug_tsc = Input(UInt(xLen.W))
}
/**
* Bundle to send commit signals across processor
*/
class CommitSignals(implicit p: Parameters) extends BoomBundle
{
val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn
val arch_valids = Vec(retireWidth, Bool())
val uops = Vec(retireWidth, new MicroOp())
val fflags = Valid(UInt(5.W))
// These come a cycle later
val debug_insts = Vec(retireWidth, UInt(32.W))
val debug_wdata = Vec(retireWidth, UInt(xLen.W))
}
/**
* Bundle to communicate exceptions to CSRFile
*
* TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).
*/
class CommitExceptionSignals(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val edge_inst = Bool()
val is_rvc = Bool()
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
val cause = UInt(xLen.W)
val badvaddr = UInt(xLen.W)
// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)
// so the FTQ can drive the frontend with the correct redirected PC.
val flush_typ = FlushTypes()
}
/**
* Tell the frontend the type of flush so it can set up the next PC properly.
*/
object FlushTypes
{
def SZ = 3
def apply() = UInt(SZ.W)
def none = 0.U
def xcpt = 1.U // An exception occurred.
def eret = (2+1).U // Execute an environment return instruction.
def refetch = 2.U // Flush and refetch the head instruction.
def next = 4.U // Flush and fetch the next instruction.
def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U
def useSamePC(typ: UInt): Bool = typ === refetch
def usePCplus4(typ: UInt): Bool = typ === next
def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {
val ret =
Mux(!valid, none,
Mux(i_eret, eret,
Mux(i_xcpt, xcpt,
Mux(i_refetch, refetch,
next))))
ret
}
}
/**
* Bundle of signals indicating that an exception occurred
*/
class Exception(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)
val badvaddr = UInt(coreMaxAddrBits.W)
}
/**
* Bundle for debug ROB signals
* These should not be synthesized!
*/
class DebugRobSignals(implicit p: Parameters) extends BoomBundle
{
val state = UInt()
val rob_head = UInt(robAddrSz.W)
val rob_pnr = UInt(robAddrSz.W)
val xcpt_val = Bool()
val xcpt_uop = new MicroOp()
val xcpt_badvaddr = UInt(xLen.W)
}
/**
* Reorder Buffer to keep track of dependencies and inflight instructions
*
* @param numWakeupPorts number of wakeup ports to the ROB
* @param numFpuPorts number of FPU units that will write back fflags
*/
class Rob(
val numWakeupPorts: Int,
val usingTrace: Boolean
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new RobIo(numWakeupPorts))
// ROB Finite State Machine
val s_reset :: s_normal :: s_wait_till_empty :: s_rollback :: Nil = Enum(4)
val rob_state = RegInit(s_reset)
//commit entries at the head, and unwind exceptions from the tail
val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)
val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)
val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)
val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)
val next_rob_head = WireInit(rob_head)
rob_head := next_rob_head
val full = Wire(Bool())
val empty = Wire(Bool())
val will_commit = Wire(Vec(coreWidth, Bool()))
val can_commit = Wire(Vec(coreWidth, Bool()))
val can_throw_exception = Wire(Vec(coreWidth, Bool()))
val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?
val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?
val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)
val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))
val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))
val rob_head_fflags = Wire(Vec(coreWidth, Valid(UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
val exception_thrown = Wire(Bool())
// exception info
// TODO compress xcpt cause size. Most bits in the middle are zero.
val r_xcpt_val = RegInit(false.B)
val r_xcpt_uop = Reg(new MicroOp())
val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))
io.flush_frontend := r_xcpt_val
//--------------------------------------------------
// Utility
def GetRowIdx(rob_idx: UInt): UInt = {
if (coreWidth == 1) return rob_idx
else return rob_idx >> log2Ceil(coreWidth).U
}
def GetBankIdx(rob_idx: UInt): UInt = {
if(coreWidth == 1) { return 0.U }
else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }
}
// **************************************************************************
// Debug
class DebugRobBundle extends BoomBundle
{
val valid = Bool()
val busy = Bool()
val unsafe = Bool()
val uop = new MicroOp()
val exception = Bool()
}
val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))
debug_entry := DontCare // override in statements below
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.
val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))
val rob_debug_inst_rdata = Wire(Vec(coreWidth, UInt(32.W)))
val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))
val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))
// Used for trace port, for debug purposes only
if (usingTrace) {
val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))
rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)
rob_debug_inst_rdata := rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))
} else {
rob_debug_inst_rdata := DontCare
}
// Branch resolution
val brupdate_b2_rob_row = GetRowIdx(io.brupdate.b2.uop.rob_idx)
val brupdate_b2_rob_row_oh = UIntToOH(brupdate_b2_rob_row)
val brupdate_b2_rob_clr_oh = IsYoungerMask(brupdate_b2_rob_row, rob_head, numRobRows)
val brupdate_b2_rob_bank_idx = GetBankIdx(io.brupdate.b2.uop.rob_idx)
val brupdate_b2_rob_bank_clr_oh = ~MaskLower(UIntToOH(brupdate_b2_rob_bank_idx))
class RobCompactUop extends Bundle {
val is_fencei = Bool()
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val uses_ldq = Bool()
val uses_stq = Bool()
val dst_rtype = UInt(2.W)
val ldst = UInt(lregSz.W)
val pdst = UInt(maxPregSz.W)
val stale_pdst = UInt(maxPregSz.W)
}
val compactUopWidth = 1 + log2Ceil(ftqSz) + 1 + 1 + 2 + lregSz + maxPregSz + maxPregSz
def compact_to_uop(compact: RobCompactUop, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.is_fencei := compact.is_fencei
out.ftq_idx := compact.ftq_idx
out.uses_ldq := compact.uses_ldq
out.uses_stq := compact.uses_stq
out.dst_rtype := compact.dst_rtype
out.ldst := compact.ldst
out.pdst := compact.pdst
out.stale_pdst := compact.stale_pdst
out
}
def uop_to_compact(uop: MicroOp): RobCompactUop = {
val out = Wire(new RobCompactUop)
out.is_fencei := uop.is_fencei
out.ftq_idx := uop.ftq_idx
out.uses_ldq := uop.uses_ldq
out.uses_stq := uop.uses_stq
out.dst_rtype := uop.dst_rtype
out.ldst := uop.ldst
out.pdst := uop.pdst
out.stale_pdst := uop.stale_pdst
out
}
// More efficient rob uop storage in 1R1W masked SRAM
val rob_compact_uop_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(compactUopWidth.W)))
val rob_compact_uop_wdata = VecInit(io.enq_uops.map(u => uop_to_compact(u).asUInt))
rob_compact_uop_mem.write(rob_tail, rob_compact_uop_wdata, io.enq_valids)
val rob_compact_uop_rdata = rob_compact_uop_mem.read(next_rob_head)
val rob_compact_uop_might_bypass = rob_head === RegNext(rob_tail)
val rob_compact_uop_bypassed = (0 until coreWidth) map { w =>
Mux(rob_head === RegNext(rob_tail) && RegNext(io.enq_valids(w)),
RegNext(rob_compact_uop_wdata(w)),
Mux(rob_head === ShiftRegister(rob_tail, 2) && ShiftRegister(io.enq_valids(w), 2),
ShiftRegister(rob_compact_uop_wdata(w), 2),
rob_compact_uop_rdata(w)
)
).asTypeOf(new RobCompactUop)
}
val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
for (w <- 0 until coreWidth) {
def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)
// one bank
val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))
val rob_bsy = Reg(Vec(numRobRows, Bool()))
val rob_unsafe = Reg(Vec(numRobRows, Bool()))
val rob_uop = Reg(Vec(numRobRows, new MicroOp()))
val rob_exception = Reg(Vec(numRobRows, Bool()))
val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?
val rob_fflags = Reg(Vec(numRobRows, Valid(Bits(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))
//-----------------------------------------------
// Dispatch: Add Entry to ROB
rob_debug_inst_wmask(w) := io.enq_valids(w)
rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst
when (io.enq_valids(w)) {
rob_val(rob_tail) := true.B
rob_bsy(rob_tail) := io.enq_uops(w).starts_bsy
rob_unsafe(rob_tail) := io.enq_uops(w).starts_unsafe
rob_uop(rob_tail) := io.enq_uops(w)
rob_exception(rob_tail) := io.enq_uops(w).exception
rob_predicated(rob_tail) := false.B
rob_fflags(rob_tail).valid := false.B
rob_fflags(rob_tail).bits := 0.U
assert (rob_val(rob_tail) === false.B, "[rob] overwriting a valid entry.")
assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)
} .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {
}
//-----------------------------------------------
// Writeback
for (i <- 0 until numWakeupPorts) {
val wb_resp = io.wb_resps(i)
val wb_uop = wb_resp.bits.uop
val row_idx = GetRowIdx(wb_uop.rob_idx)
when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {
rob_bsy(row_idx) := false.B
rob_unsafe(row_idx) := false.B
rob_predicated(row_idx) := wb_resp.bits.predicated
when (wb_resp.bits.fflags.valid) {
assert(!rob_fflags(row_idx).valid)
rob_fflags(row_idx).valid := true.B
rob_fflags(row_idx).bits := wb_resp.bits.fflags.bits
}
}
}
// Stores have a separate method to clear busy bits
for (clr_rob_idx <- io.lsu_clr_bsy) {
when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {
val cidx = GetRowIdx(clr_rob_idx.bits)
rob_bsy(cidx) := false.B
rob_unsafe(cidx) := false.B
assert (rob_val(cidx) === true.B, "[rob] store writing back to invalid entry.")
assert (rob_bsy(cidx) === true.B, "[rob] store writing back to a not-busy entry.")
}
}
for (clr <- io.lsu_clr_unsafe) {
when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {
val cidx = GetRowIdx(clr.bits)
rob_unsafe(cidx) := false.B
}
}
//-----------------------------------------------------
// Exceptions
// (the cause bits are compressed and stored elsewhere)
when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B
when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {
// In the case of a mem-ordering failure, the failing load will have been marked safe already.
assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),
"An instruction marked as safe is causing an exception")
}
}
when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B
}
can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)
//-----------------------------------------------
// Commit
// Can this instruction commit? (the check for exceptions/rob_state happens later).
// Block commit if there is mispredict
can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall && !io.brupdate.b2.mispredict
// use the same "com_uop" for both rollback AND commit
// Perform Commit
io.commit.valids(w) := will_commit(w)
io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(rob_head)
io.commit.uops(w) := compact_to_uop(rob_compact_uop_bypassed(w), rob_uop(rob_head))
io.commit.debug_insts(w) := rob_debug_inst_rdata(w)
// We unbusy branches in b1, but its easier to mark the taken/provider src in b2,
// when the branch might be committing
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&
GetRowIdx(io.brupdate.b2.uop.rob_idx) === rob_head) {
io.commit.uops(w).debug_fsrc := BSRC_C
io.commit.uops(w).taken := io.brupdate.b2.taken
}
when (rob_state === s_rollback) {
for (i <- 0 until numRobRows) {
rob_val(i) := false.B
rob_bsy(i) := false.B
}
}
// -----------------------------------------------
// Kill speculated entries on branch mispredict
for (i <- 0 until numRobRows) {
val br_mask = rob_uop(i).br_mask
when (io.brupdate.b2.mispredict && (
brupdate_b2_rob_clr_oh(i) ||
(brupdate_b2_rob_row_oh(i) && brupdate_b2_rob_bank_clr_oh(w))
)) {
rob_val(i) := false.B
}
// //kill instruction if mispredict & br mask match
// when (IsKilledByBranch(io.brupdate, false.B, br_mask))
// {
// rob_val(i) := false.B
// } .elsewhen (rob_val(i)) {
// // clear speculation bit even on correct speculation
// rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)
// }
}
// Debug signal to figure out which prediction structure
// or core resolved a branch correctly
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken
}
// -----------------------------------------------
// Commit
when (will_commit(w)) {
rob_val(rob_head) := false.B
}
// -----------------------------------------------
// Outputs
rob_head_vals(w) := rob_val(rob_head)
rob_tail_vals(w) := rob_val(rob_tail)
rob_head_fflags(w) := rob_fflags(rob_head)
rob_head_uses_stq(w) := io.commit.uops(w).uses_stq
rob_head_uses_ldq(w) := io.commit.uops(w).uses_ldq
//------------------------------------------------
// Invalid entries are safe; thrown exceptions are unsafe.
for (i <- 0 until numRobRows) {
rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))
}
// Read unsafe status of PNR row.
rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))
//--------------------------------------------------
// Debug: for debug purposes, track side-effects to all register destinations
for (i <- 0 until numWakeupPorts) {
val rob_idx = io.wb_resps(i).bits.uop.rob_idx
when (io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx))) {
rob_debug_wdata(GetRowIdx(rob_idx)) := io.wb_resps(i).bits.data
}
val temp_uop = rob_uop(GetRowIdx(rob_idx))
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_val(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to an invalid ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_bsy(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to a not-busy ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
temp_uop.dst_rtype =/= RT_X && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),
"[rob] writeback (" + i + ") occurred to the wrong pdst.")
}
io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)
} //for (w <- 0 until coreWidth)
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// -----------------------------------------------
// Commit Logic
// need to take a "can_commit" array, and let the first can_commits commit
// previous instructions may block the commit of younger instructions in the commit bundle
// e.g., exception, or (valid && busy).
// Finally, don't throw an exception if there are instructions in front of
// it that want to commit (only throw exception when head of the bundle).
var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))
var will_throw_exception = false.B
var block_xcpt = false.B
for (w <- 0 until coreWidth) {
will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception
will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit
block_commit = (rob_head_vals(w) &&
(!can_commit(w) || can_throw_exception(w))) || block_commit
block_xcpt = will_commit(w)
}
// Note: exception must be in the commit bundle.
// Note: exception must be the first valid instruction in the commit bundle.
exception_thrown := will_throw_exception
val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)
io.com_xcpt.valid := exception_thrown && !is_mini_exception
io.com_xcpt.bits := DontCare
io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause
io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)
val insn_sys_pc2epc =
rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})
val refetch_inst = exception_thrown || insn_sys_pc2epc
val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)
io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx
io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst
io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc
io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob
val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}
val flush_commit = flush_commit_mask.reduce(_|_)
val flush_val = exception_thrown || flush_commit
assert(!(PopCount(flush_commit_mask) > 1.U),
"[rob] Can't commit multiple flush_on_commit instructions on one cycle")
val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))
// delay a cycle for critical path considerations
io.flush.valid := flush_val
io.flush.bits.badvaddr := DontCare
io.flush.bits.cause := DontCare
io.flush.bits.ftq_idx := flush_uop.ftq_idx
io.flush.bits.pc_lob := flush_uop.pc_lob
io.flush.bits.edge_inst := flush_uop.edge_inst
io.flush.bits.is_rvc := flush_uop.is_rvc
io.flush.bits.flush_typ := FlushTypes.getType(flush_val,
exception_thrown && !is_mini_exception,
flush_commit && flush_uop.is_eret,
refetch_inst)
io.rollback := rob_state === s_rollback
// -----------------------------------------------
// FP Exceptions
// send fflags bits to the CSRFile to accrue
val fflags_val = Wire(Vec(coreWidth, Bool()))
val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
for (w <- 0 until coreWidth) {
fflags_val(w) := rob_head_fflags(w).valid && io.commit.valids(w)
fflags(w) := Mux(fflags_val(w), rob_head_fflags(w).bits, 0.U)
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
!(io.commit.uops(w).uses_stq || io.commit.uops(w).uses_ldq) &&
!rob_head_fflags(w).valid),
"Committed FP instruction did not set fflag bits")
assert (!(io.commit.valids(w) &&
!io.commit.uops(w).fp_val &&
rob_head_fflags(w).valid),
"Committed non-FP instruction has non-zero fflag bits.")
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
(io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&
(rob_head_fflags(w).bits =/= 0.U && rob_head_fflags(w).valid)),
"Committed FP load or store has non-zero fflag bits.")
}
io.commit.fflags.valid := fflags_val.reduce(_|_)
io.commit.fflags.bits := fflags.reduce(_|_)
// -----------------------------------------------
// Exception Tracking Logic
// only store the oldest exception, since only one can happen!
val next_xcpt_uop = Wire(new MicroOp())
next_xcpt_uop := r_xcpt_uop
val enq_xcpts = Wire(Vec(coreWidth, Bool()))
for (i <- 0 until coreWidth) {
enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception
}
when (!(io.flush.valid || exception_thrown)) {
val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid
val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)
val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when (new_xcpt_valid) {
when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {
r_xcpt_val := true.B
next_xcpt_uop := new_xcpt.uop
next_xcpt_uop.exc_cause := new_xcpt.cause
r_xcpt_badvaddr := new_xcpt.badvaddr
}
} .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {
val idx = enq_xcpts.indexWhere{i: Bool => i}
// if no exception yet, dispatch exception wins
r_xcpt_val := true.B
next_xcpt_uop := io.enq_uops(idx)
r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob
}
}
r_xcpt_uop := next_xcpt_uop
r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)
when (IsKilledByBranch(io.brupdate, io.flush.valid, next_xcpt_uop)) {
r_xcpt_val := false.B
}
assert (!(exception_thrown && !r_xcpt_val),
"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause")
assert (!(empty && r_xcpt_val),
"ROB is empty, but believes it has an outstanding exception.")
assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),
"ROB is throwing an exception, but the stored exception information's " +
"rob_idx does not match the rob_head")
// -----------------------------------------------
// ROB Head Logic
// remember if we're still waiting on the rest of the dispatch packet, and prevent
// the rob_head from advancing if it commits a partial parket before we
// dispatch the rest of it.
// update when committed ALL valid instructions in commit_bundle
val r_partial_row = RegInit(false.B)
val finished_committing_row =
(io.commit.valids.asUInt =/= 0.U) &&
((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&
!(r_partial_row && rob_head === rob_tail && !io.brupdate.b2.mispredict)
when (finished_committing_row) {
next_rob_head := WrapInc(rob_head, numRobRows)
rob_head_lsb := 0.U
} .elsewhen (rob_state === s_rollback) {
rob_head_lsb := 0.U
} .otherwise {
rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))
}
// -----------------------------------------------
// ROB Point-of-No-Return (PNR) Logic
// Acts as a second head, but only waits on busy instructions which might cause misspeculation.
// TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?
// Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.
// Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.
if (enableFastPNR) {
val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)
val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,
AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),
rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))
rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)
if (coreWidth > 1)
rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)
} else {
val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty
val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && !(rob_pnr === rob_tail && !io.brupdate.b2.mispredict)
when (rob_state === s_rollback) {
assert(rob_pnr === rob_head)
rob_pnr_lsb := 0.U
} .elsewhen (empty && io.enq_valids.asUInt =/= 0.U) {
// Unforunately for us, the ROB does not use its entries in monotonically
// increasing order, even in the case of no exceptions. The edge case
// arises when partial rows are enqueued and committed, leaving an empty
// ROB.
rob_pnr := rob_head
rob_pnr_lsb := PriorityEncoder(io.enq_valids)
} .elsewhen (safe_to_inc && do_inc_row) {
rob_pnr := WrapInc(rob_pnr, numRobRows)
rob_pnr_lsb := 0.U
} .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail)) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)
} .elsewhen (safe_to_inc && !full && !empty) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))
}
}
// Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.
assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)
// PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.
assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)
// -----------------------------------------------
// ROB Tail Logic
when (io.brupdate.b2.mispredict) {
rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)
rob_tail_lsb := 0.U
r_partial_row := false.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {
rob_tail := WrapInc(rob_tail, numRobRows)
rob_tail_lsb := 0.U
r_partial_row := false.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {
rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))
r_partial_row := true.B
}
// -----------------------------------------------
// Full/Empty Logic
full := WrapInc(rob_tail, numRobRows) === rob_head
empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)
io.rob_head_idx := rob_head_idx
io.rob_tail_idx := rob_tail_idx
io.rob_pnr_idx := rob_pnr_idx
io.empty := empty
io.ready := (rob_state === s_normal) && !full && !r_xcpt_val
//-----------------------------------------------
//-----------------------------------------------
//-----------------------------------------------
// ROB FSM
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
rob_tail := rob_head
rob_tail_lsb := 0.U
rob_state := s_normal
}
is (s_wait_till_empty) {
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .elsewhen (empty) {
rob_state := s_normal
}
}
}
// -----------------------------------------------
// Outputs
io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&
!will_commit.reduce(_||_))
override def toString: String = BoomCoreStringPrefix(
"==ROB==",
"Machine Width : " + coreWidth,
"Rob Entries : " + numRobEntries,
"Rob Rows : " + numRobRows,
"Rob Row size : " + log2Ceil(numRobRows),
"log2Ceil(coreWidth): " + log2Ceil(coreWidth))
}
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
| module Rob( // @[rob.scala:199:7]
input clock, // @[rob.scala:199:7]
input reset, // @[rob.scala:199:7]
input io_enq_valids_0, // @[rob.scala:204:14]
input io_enq_valids_1, // @[rob.scala:204:14]
input [31:0] io_enq_uops_0_inst, // @[rob.scala:204:14]
input [31:0] io_enq_uops_0_debug_inst, // @[rob.scala:204:14]
input io_enq_uops_0_is_rvc, // @[rob.scala:204:14]
input [39:0] io_enq_uops_0_debug_pc, // @[rob.scala:204:14]
input io_enq_uops_0_iq_type_0, // @[rob.scala:204:14]
input io_enq_uops_0_iq_type_1, // @[rob.scala:204:14]
input io_enq_uops_0_iq_type_2, // @[rob.scala:204:14]
input io_enq_uops_0_iq_type_3, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_0, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_1, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_2, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_3, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_4, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_5, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_6, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_7, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_8, // @[rob.scala:204:14]
input io_enq_uops_0_fu_code_9, // @[rob.scala:204:14]
input io_enq_uops_0_iw_issued, // @[rob.scala:204:14]
input io_enq_uops_0_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_enq_uops_0_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_enq_uops_0_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_enq_uops_0_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_enq_uops_0_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_enq_uops_0_br_mask, // @[rob.scala:204:14]
input [3:0] io_enq_uops_0_br_tag, // @[rob.scala:204:14]
input [3:0] io_enq_uops_0_br_type, // @[rob.scala:204:14]
input io_enq_uops_0_is_sfb, // @[rob.scala:204:14]
input io_enq_uops_0_is_fence, // @[rob.scala:204:14]
input io_enq_uops_0_is_fencei, // @[rob.scala:204:14]
input io_enq_uops_0_is_sfence, // @[rob.scala:204:14]
input io_enq_uops_0_is_amo, // @[rob.scala:204:14]
input io_enq_uops_0_is_eret, // @[rob.scala:204:14]
input io_enq_uops_0_is_sys_pc2epc, // @[rob.scala:204:14]
input io_enq_uops_0_is_rocc, // @[rob.scala:204:14]
input io_enq_uops_0_is_mov, // @[rob.scala:204:14]
input [4:0] io_enq_uops_0_ftq_idx, // @[rob.scala:204:14]
input io_enq_uops_0_edge_inst, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_pc_lob, // @[rob.scala:204:14]
input io_enq_uops_0_taken, // @[rob.scala:204:14]
input io_enq_uops_0_imm_rename, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_imm_sel, // @[rob.scala:204:14]
input [4:0] io_enq_uops_0_pimm, // @[rob.scala:204:14]
input [19:0] io_enq_uops_0_imm_packed, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_op1_sel, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_op2_sel, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_wen, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_toint, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_fma, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_div, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_enq_uops_0_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_rob_idx, // @[rob.scala:204:14]
input [3:0] io_enq_uops_0_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_enq_uops_0_stq_idx, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_enq_uops_0_pdst, // @[rob.scala:204:14]
input [6:0] io_enq_uops_0_prs1, // @[rob.scala:204:14]
input [6:0] io_enq_uops_0_prs2, // @[rob.scala:204:14]
input [6:0] io_enq_uops_0_prs3, // @[rob.scala:204:14]
input [4:0] io_enq_uops_0_ppred, // @[rob.scala:204:14]
input io_enq_uops_0_prs1_busy, // @[rob.scala:204:14]
input io_enq_uops_0_prs2_busy, // @[rob.scala:204:14]
input io_enq_uops_0_prs3_busy, // @[rob.scala:204:14]
input io_enq_uops_0_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_enq_uops_0_stale_pdst, // @[rob.scala:204:14]
input io_enq_uops_0_exception, // @[rob.scala:204:14]
input [63:0] io_enq_uops_0_exc_cause, // @[rob.scala:204:14]
input [4:0] io_enq_uops_0_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_mem_size, // @[rob.scala:204:14]
input io_enq_uops_0_mem_signed, // @[rob.scala:204:14]
input io_enq_uops_0_uses_ldq, // @[rob.scala:204:14]
input io_enq_uops_0_uses_stq, // @[rob.scala:204:14]
input io_enq_uops_0_is_unique, // @[rob.scala:204:14]
input io_enq_uops_0_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_csr_cmd, // @[rob.scala:204:14]
input io_enq_uops_0_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_ldst, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_lrs1, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_lrs2, // @[rob.scala:204:14]
input [5:0] io_enq_uops_0_lrs3, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_lrs2_rtype, // @[rob.scala:204:14]
input io_enq_uops_0_frs3_en, // @[rob.scala:204:14]
input io_enq_uops_0_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_enq_uops_0_fcn_op, // @[rob.scala:204:14]
input io_enq_uops_0_fp_val, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_fp_rm, // @[rob.scala:204:14]
input [1:0] io_enq_uops_0_fp_typ, // @[rob.scala:204:14]
input io_enq_uops_0_xcpt_pf_if, // @[rob.scala:204:14]
input io_enq_uops_0_xcpt_ae_if, // @[rob.scala:204:14]
input io_enq_uops_0_xcpt_ma_if, // @[rob.scala:204:14]
input io_enq_uops_0_bp_debug_if, // @[rob.scala:204:14]
input io_enq_uops_0_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_enq_uops_0_debug_tsrc, // @[rob.scala:204:14]
input [31:0] io_enq_uops_1_inst, // @[rob.scala:204:14]
input [31:0] io_enq_uops_1_debug_inst, // @[rob.scala:204:14]
input io_enq_uops_1_is_rvc, // @[rob.scala:204:14]
input [39:0] io_enq_uops_1_debug_pc, // @[rob.scala:204:14]
input io_enq_uops_1_iq_type_0, // @[rob.scala:204:14]
input io_enq_uops_1_iq_type_1, // @[rob.scala:204:14]
input io_enq_uops_1_iq_type_2, // @[rob.scala:204:14]
input io_enq_uops_1_iq_type_3, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_0, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_1, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_2, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_3, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_4, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_5, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_6, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_7, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_8, // @[rob.scala:204:14]
input io_enq_uops_1_fu_code_9, // @[rob.scala:204:14]
input io_enq_uops_1_iw_issued, // @[rob.scala:204:14]
input io_enq_uops_1_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_enq_uops_1_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_enq_uops_1_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_enq_uops_1_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_enq_uops_1_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_enq_uops_1_br_mask, // @[rob.scala:204:14]
input [3:0] io_enq_uops_1_br_tag, // @[rob.scala:204:14]
input [3:0] io_enq_uops_1_br_type, // @[rob.scala:204:14]
input io_enq_uops_1_is_sfb, // @[rob.scala:204:14]
input io_enq_uops_1_is_fence, // @[rob.scala:204:14]
input io_enq_uops_1_is_fencei, // @[rob.scala:204:14]
input io_enq_uops_1_is_sfence, // @[rob.scala:204:14]
input io_enq_uops_1_is_amo, // @[rob.scala:204:14]
input io_enq_uops_1_is_eret, // @[rob.scala:204:14]
input io_enq_uops_1_is_sys_pc2epc, // @[rob.scala:204:14]
input io_enq_uops_1_is_rocc, // @[rob.scala:204:14]
input io_enq_uops_1_is_mov, // @[rob.scala:204:14]
input [4:0] io_enq_uops_1_ftq_idx, // @[rob.scala:204:14]
input io_enq_uops_1_edge_inst, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_pc_lob, // @[rob.scala:204:14]
input io_enq_uops_1_taken, // @[rob.scala:204:14]
input io_enq_uops_1_imm_rename, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_imm_sel, // @[rob.scala:204:14]
input [4:0] io_enq_uops_1_pimm, // @[rob.scala:204:14]
input [19:0] io_enq_uops_1_imm_packed, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_op1_sel, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_op2_sel, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_wen, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_toint, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_fma, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_div, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_enq_uops_1_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_rob_idx, // @[rob.scala:204:14]
input [3:0] io_enq_uops_1_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_enq_uops_1_stq_idx, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_enq_uops_1_pdst, // @[rob.scala:204:14]
input [6:0] io_enq_uops_1_prs1, // @[rob.scala:204:14]
input [6:0] io_enq_uops_1_prs2, // @[rob.scala:204:14]
input [6:0] io_enq_uops_1_prs3, // @[rob.scala:204:14]
input [4:0] io_enq_uops_1_ppred, // @[rob.scala:204:14]
input io_enq_uops_1_prs1_busy, // @[rob.scala:204:14]
input io_enq_uops_1_prs2_busy, // @[rob.scala:204:14]
input io_enq_uops_1_prs3_busy, // @[rob.scala:204:14]
input io_enq_uops_1_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_enq_uops_1_stale_pdst, // @[rob.scala:204:14]
input io_enq_uops_1_exception, // @[rob.scala:204:14]
input [63:0] io_enq_uops_1_exc_cause, // @[rob.scala:204:14]
input [4:0] io_enq_uops_1_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_mem_size, // @[rob.scala:204:14]
input io_enq_uops_1_mem_signed, // @[rob.scala:204:14]
input io_enq_uops_1_uses_ldq, // @[rob.scala:204:14]
input io_enq_uops_1_uses_stq, // @[rob.scala:204:14]
input io_enq_uops_1_is_unique, // @[rob.scala:204:14]
input io_enq_uops_1_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_csr_cmd, // @[rob.scala:204:14]
input io_enq_uops_1_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_ldst, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_lrs1, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_lrs2, // @[rob.scala:204:14]
input [5:0] io_enq_uops_1_lrs3, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_lrs2_rtype, // @[rob.scala:204:14]
input io_enq_uops_1_frs3_en, // @[rob.scala:204:14]
input io_enq_uops_1_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_enq_uops_1_fcn_op, // @[rob.scala:204:14]
input io_enq_uops_1_fp_val, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_fp_rm, // @[rob.scala:204:14]
input [1:0] io_enq_uops_1_fp_typ, // @[rob.scala:204:14]
input io_enq_uops_1_xcpt_pf_if, // @[rob.scala:204:14]
input io_enq_uops_1_xcpt_ae_if, // @[rob.scala:204:14]
input io_enq_uops_1_xcpt_ma_if, // @[rob.scala:204:14]
input io_enq_uops_1_bp_debug_if, // @[rob.scala:204:14]
input io_enq_uops_1_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_enq_uops_1_debug_tsrc, // @[rob.scala:204:14]
input io_enq_partial_stall, // @[rob.scala:204:14]
input [39:0] io_xcpt_fetch_pc, // @[rob.scala:204:14]
output [5:0] io_rob_tail_idx, // @[rob.scala:204:14]
output [5:0] io_rob_pnr_idx, // @[rob.scala:204:14]
output [5:0] io_rob_head_idx, // @[rob.scala:204:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[rob.scala:204:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[rob.scala:204:14]
input [31:0] io_brupdate_b2_uop_inst, // @[rob.scala:204:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iq_type_0, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iq_type_1, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iq_type_2, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iq_type_3, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_0, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_1, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_2, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_3, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_4, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_5, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_6, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_7, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_8, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fu_code_9, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_issued, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_sfb, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_fence, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_fencei, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_sfence, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_amo, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_eret, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_rocc, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[rob.scala:204:14]
input io_brupdate_b2_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[rob.scala:204:14]
input io_brupdate_b2_uop_taken, // @[rob.scala:204:14]
input io_brupdate_b2_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[rob.scala:204:14]
input io_brupdate_b2_uop_prs1_busy, // @[rob.scala:204:14]
input io_brupdate_b2_uop_prs2_busy, // @[rob.scala:204:14]
input io_brupdate_b2_uop_prs3_busy, // @[rob.scala:204:14]
input io_brupdate_b2_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[rob.scala:204:14]
input io_brupdate_b2_uop_exception, // @[rob.scala:204:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[rob.scala:204:14]
input io_brupdate_b2_uop_mem_signed, // @[rob.scala:204:14]
input io_brupdate_b2_uop_uses_ldq, // @[rob.scala:204:14]
input io_brupdate_b2_uop_uses_stq, // @[rob.scala:204:14]
input io_brupdate_b2_uop_is_unique, // @[rob.scala:204:14]
input io_brupdate_b2_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[rob.scala:204:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_brupdate_b2_uop_frs3_en, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[rob.scala:204:14]
input io_brupdate_b2_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[rob.scala:204:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_brupdate_b2_uop_bp_debug_if, // @[rob.scala:204:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[rob.scala:204:14]
input io_brupdate_b2_mispredict, // @[rob.scala:204:14]
input io_brupdate_b2_taken, // @[rob.scala:204:14]
input [2:0] io_brupdate_b2_cfi_type, // @[rob.scala:204:14]
input [1:0] io_brupdate_b2_pc_sel, // @[rob.scala:204:14]
input [39:0] io_brupdate_b2_jalr_target, // @[rob.scala:204:14]
input [20:0] io_brupdate_b2_target_offset, // @[rob.scala:204:14]
input io_wb_resps_0_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_0_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_0_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_0_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_0_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_0_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_0_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_0_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_0_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_0_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_0_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_0_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_0_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_0_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_0_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_0_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_0_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_0_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_0_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_0_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_0_bits_data, // @[rob.scala:204:14]
input io_wb_resps_0_bits_predicated, // @[rob.scala:204:14]
input io_wb_resps_0_bits_fflags_valid, // @[rob.scala:204:14]
input [4:0] io_wb_resps_0_bits_fflags_bits, // @[rob.scala:204:14]
input io_wb_resps_1_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_1_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_1_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_1_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_1_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_1_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_1_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_1_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_1_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_1_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_1_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_1_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_1_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_1_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_1_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_1_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_1_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_1_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_1_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_1_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_1_bits_data, // @[rob.scala:204:14]
input io_wb_resps_1_bits_predicated, // @[rob.scala:204:14]
input io_wb_resps_1_bits_fflags_valid, // @[rob.scala:204:14]
input [4:0] io_wb_resps_1_bits_fflags_bits, // @[rob.scala:204:14]
input io_wb_resps_2_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_2_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_2_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_2_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_2_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_2_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_2_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_2_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_2_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_2_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_2_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_2_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_2_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_2_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_2_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_2_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_2_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_2_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_2_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_2_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_2_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_2_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_2_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_2_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_2_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_2_bits_data, // @[rob.scala:204:14]
input io_wb_resps_2_bits_predicated, // @[rob.scala:204:14]
input io_wb_resps_3_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_3_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_3_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_3_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_3_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_3_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_3_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_3_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_3_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_3_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_3_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_3_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_3_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_3_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_3_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_3_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_3_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_3_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_3_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_3_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_3_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_3_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_3_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_3_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_3_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_3_bits_data, // @[rob.scala:204:14]
input io_wb_resps_3_bits_predicated, // @[rob.scala:204:14]
input io_wb_resps_4_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_4_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_4_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_4_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_4_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_4_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_4_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_4_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_4_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_4_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_4_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_4_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_4_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_4_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_4_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_4_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_4_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_4_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_4_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_4_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_4_bits_data, // @[rob.scala:204:14]
input io_wb_resps_4_bits_fflags_valid, // @[rob.scala:204:14]
input [4:0] io_wb_resps_4_bits_fflags_bits, // @[rob.scala:204:14]
input io_wb_resps_5_valid, // @[rob.scala:204:14]
input [31:0] io_wb_resps_5_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_wb_resps_5_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_wb_resps_5_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_wb_resps_5_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_wb_resps_5_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_wb_resps_5_bits_uop_br_type, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_fence, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_amo, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_eret, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_taken, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_wb_resps_5_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_5_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_wb_resps_5_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_wb_resps_5_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_wb_resps_5_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_wb_resps_5_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_wb_resps_5_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_uop_ppred, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_wb_resps_5_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_wb_resps_5_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_mem_size, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_is_unique, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_wb_resps_5_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_wb_resps_5_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_wb_resps_5_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_wb_resps_5_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [64:0] io_wb_resps_5_bits_data, // @[rob.scala:204:14]
input io_wb_resps_5_bits_predicated, // @[rob.scala:204:14]
input io_wb_resps_5_bits_fflags_valid, // @[rob.scala:204:14]
input [4:0] io_wb_resps_5_bits_fflags_bits, // @[rob.scala:204:14]
input io_lsu_clr_bsy_0_valid, // @[rob.scala:204:14]
input [5:0] io_lsu_clr_bsy_0_bits, // @[rob.scala:204:14]
input io_lsu_clr_bsy_1_valid, // @[rob.scala:204:14]
input [5:0] io_lsu_clr_bsy_1_bits, // @[rob.scala:204:14]
input io_lsu_clr_unsafe_0_valid, // @[rob.scala:204:14]
input [5:0] io_lsu_clr_unsafe_0_bits, // @[rob.scala:204:14]
input io_lxcpt_valid, // @[rob.scala:204:14]
input [31:0] io_lxcpt_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_lxcpt_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_lxcpt_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_lxcpt_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_lxcpt_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_lxcpt_bits_uop_br_type, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_fence, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_amo, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_eret, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_taken, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_lxcpt_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_lxcpt_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_lxcpt_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_lxcpt_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_lxcpt_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_lxcpt_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_lxcpt_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_uop_ppred, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_lxcpt_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_lxcpt_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_mem_size, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_is_unique, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_lxcpt_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_lxcpt_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_lxcpt_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_lxcpt_bits_uop_debug_tsrc, // @[rob.scala:204:14]
input [4:0] io_lxcpt_bits_cause, // @[rob.scala:204:14]
input [39:0] io_lxcpt_bits_badvaddr, // @[rob.scala:204:14]
input [31:0] io_csr_replay_bits_uop_inst, // @[rob.scala:204:14]
input [31:0] io_csr_replay_bits_uop_debug_inst, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_rvc, // @[rob.scala:204:14]
input [39:0] io_csr_replay_bits_uop_debug_pc, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iq_type_0, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iq_type_1, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iq_type_2, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iq_type_3, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_0, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_1, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_2, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_3, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_4, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_5, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_6, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_7, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_8, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fu_code_9, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_issued, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_issued_partial_agen, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_issued_partial_dgen, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_iw_p1_speculative_child, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_iw_p2_speculative_child, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_p1_bypass_hint, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_p2_bypass_hint, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_iw_p3_bypass_hint, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_dis_col_sel, // @[rob.scala:204:14]
input [11:0] io_csr_replay_bits_uop_br_mask, // @[rob.scala:204:14]
input [3:0] io_csr_replay_bits_uop_br_tag, // @[rob.scala:204:14]
input [3:0] io_csr_replay_bits_uop_br_type, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_sfb, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_fence, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_fencei, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_sfence, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_amo, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_eret, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_sys_pc2epc, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_rocc, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_mov, // @[rob.scala:204:14]
input [4:0] io_csr_replay_bits_uop_ftq_idx, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_edge_inst, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_pc_lob, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_taken, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_imm_rename, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_imm_sel, // @[rob.scala:204:14]
input [4:0] io_csr_replay_bits_uop_pimm, // @[rob.scala:204:14]
input [19:0] io_csr_replay_bits_uop_imm_packed, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_op1_sel, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_op2_sel, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_ldst, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_wen, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_ren1, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_ren2, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_ren3, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_swap12, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_swap23, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_fromint, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_toint, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_fastpipe, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_fma, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_div, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_sqrt, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_wflags, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_ctrl_vec, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_rob_idx, // @[rob.scala:204:14]
input [3:0] io_csr_replay_bits_uop_ldq_idx, // @[rob.scala:204:14]
input [3:0] io_csr_replay_bits_uop_stq_idx, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_rxq_idx, // @[rob.scala:204:14]
input [6:0] io_csr_replay_bits_uop_pdst, // @[rob.scala:204:14]
input [6:0] io_csr_replay_bits_uop_prs1, // @[rob.scala:204:14]
input [6:0] io_csr_replay_bits_uop_prs2, // @[rob.scala:204:14]
input [6:0] io_csr_replay_bits_uop_prs3, // @[rob.scala:204:14]
input [4:0] io_csr_replay_bits_uop_ppred, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_prs1_busy, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_prs2_busy, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_prs3_busy, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_ppred_busy, // @[rob.scala:204:14]
input [6:0] io_csr_replay_bits_uop_stale_pdst, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_exception, // @[rob.scala:204:14]
input [63:0] io_csr_replay_bits_uop_exc_cause, // @[rob.scala:204:14]
input [4:0] io_csr_replay_bits_uop_mem_cmd, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_mem_size, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_mem_signed, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_uses_ldq, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_uses_stq, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_is_unique, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_flush_on_commit, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_csr_cmd, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_ldst_is_rs1, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_ldst, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_lrs1, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_lrs2, // @[rob.scala:204:14]
input [5:0] io_csr_replay_bits_uop_lrs3, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_dst_rtype, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_lrs1_rtype, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_lrs2_rtype, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_frs3_en, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fcn_dw, // @[rob.scala:204:14]
input [4:0] io_csr_replay_bits_uop_fcn_op, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_fp_val, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_fp_rm, // @[rob.scala:204:14]
input [1:0] io_csr_replay_bits_uop_fp_typ, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_xcpt_pf_if, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_xcpt_ae_if, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_xcpt_ma_if, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_bp_debug_if, // @[rob.scala:204:14]
input io_csr_replay_bits_uop_bp_xcpt_if, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_debug_fsrc, // @[rob.scala:204:14]
input [2:0] io_csr_replay_bits_uop_debug_tsrc, // @[rob.scala:204:14]
output io_commit_valids_0, // @[rob.scala:204:14]
output io_commit_valids_1, // @[rob.scala:204:14]
output io_commit_arch_valids_0, // @[rob.scala:204:14]
output io_commit_arch_valids_1, // @[rob.scala:204:14]
output [31:0] io_commit_uops_0_inst, // @[rob.scala:204:14]
output [31:0] io_commit_uops_0_debug_inst, // @[rob.scala:204:14]
output io_commit_uops_0_is_rvc, // @[rob.scala:204:14]
output [39:0] io_commit_uops_0_debug_pc, // @[rob.scala:204:14]
output io_commit_uops_0_iq_type_0, // @[rob.scala:204:14]
output io_commit_uops_0_iq_type_1, // @[rob.scala:204:14]
output io_commit_uops_0_iq_type_2, // @[rob.scala:204:14]
output io_commit_uops_0_iq_type_3, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_0, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_1, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_2, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_3, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_4, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_5, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_6, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_7, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_8, // @[rob.scala:204:14]
output io_commit_uops_0_fu_code_9, // @[rob.scala:204:14]
output io_commit_uops_0_iw_issued, // @[rob.scala:204:14]
output io_commit_uops_0_iw_issued_partial_agen, // @[rob.scala:204:14]
output io_commit_uops_0_iw_issued_partial_dgen, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_iw_p1_speculative_child, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_iw_p2_speculative_child, // @[rob.scala:204:14]
output io_commit_uops_0_iw_p1_bypass_hint, // @[rob.scala:204:14]
output io_commit_uops_0_iw_p2_bypass_hint, // @[rob.scala:204:14]
output io_commit_uops_0_iw_p3_bypass_hint, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_dis_col_sel, // @[rob.scala:204:14]
output [11:0] io_commit_uops_0_br_mask, // @[rob.scala:204:14]
output [3:0] io_commit_uops_0_br_tag, // @[rob.scala:204:14]
output [3:0] io_commit_uops_0_br_type, // @[rob.scala:204:14]
output io_commit_uops_0_is_sfb, // @[rob.scala:204:14]
output io_commit_uops_0_is_fence, // @[rob.scala:204:14]
output io_commit_uops_0_is_fencei, // @[rob.scala:204:14]
output io_commit_uops_0_is_sfence, // @[rob.scala:204:14]
output io_commit_uops_0_is_amo, // @[rob.scala:204:14]
output io_commit_uops_0_is_eret, // @[rob.scala:204:14]
output io_commit_uops_0_is_sys_pc2epc, // @[rob.scala:204:14]
output io_commit_uops_0_is_rocc, // @[rob.scala:204:14]
output io_commit_uops_0_is_mov, // @[rob.scala:204:14]
output [4:0] io_commit_uops_0_ftq_idx, // @[rob.scala:204:14]
output io_commit_uops_0_edge_inst, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_pc_lob, // @[rob.scala:204:14]
output io_commit_uops_0_taken, // @[rob.scala:204:14]
output io_commit_uops_0_imm_rename, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_imm_sel, // @[rob.scala:204:14]
output [4:0] io_commit_uops_0_pimm, // @[rob.scala:204:14]
output [19:0] io_commit_uops_0_imm_packed, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_op1_sel, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_op2_sel, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_ldst, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_wen, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_ren1, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_ren2, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_ren3, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_swap12, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_swap23, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_fromint, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_toint, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_fastpipe, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_fma, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_div, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_sqrt, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_wflags, // @[rob.scala:204:14]
output io_commit_uops_0_fp_ctrl_vec, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_rob_idx, // @[rob.scala:204:14]
output [3:0] io_commit_uops_0_ldq_idx, // @[rob.scala:204:14]
output [3:0] io_commit_uops_0_stq_idx, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_rxq_idx, // @[rob.scala:204:14]
output [6:0] io_commit_uops_0_pdst, // @[rob.scala:204:14]
output [6:0] io_commit_uops_0_prs1, // @[rob.scala:204:14]
output [6:0] io_commit_uops_0_prs2, // @[rob.scala:204:14]
output [6:0] io_commit_uops_0_prs3, // @[rob.scala:204:14]
output [4:0] io_commit_uops_0_ppred, // @[rob.scala:204:14]
output io_commit_uops_0_prs1_busy, // @[rob.scala:204:14]
output io_commit_uops_0_prs2_busy, // @[rob.scala:204:14]
output io_commit_uops_0_prs3_busy, // @[rob.scala:204:14]
output io_commit_uops_0_ppred_busy, // @[rob.scala:204:14]
output [6:0] io_commit_uops_0_stale_pdst, // @[rob.scala:204:14]
output io_commit_uops_0_exception, // @[rob.scala:204:14]
output [63:0] io_commit_uops_0_exc_cause, // @[rob.scala:204:14]
output [4:0] io_commit_uops_0_mem_cmd, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_mem_size, // @[rob.scala:204:14]
output io_commit_uops_0_mem_signed, // @[rob.scala:204:14]
output io_commit_uops_0_uses_ldq, // @[rob.scala:204:14]
output io_commit_uops_0_uses_stq, // @[rob.scala:204:14]
output io_commit_uops_0_is_unique, // @[rob.scala:204:14]
output io_commit_uops_0_flush_on_commit, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_csr_cmd, // @[rob.scala:204:14]
output io_commit_uops_0_ldst_is_rs1, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_ldst, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_lrs1, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_lrs2, // @[rob.scala:204:14]
output [5:0] io_commit_uops_0_lrs3, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_dst_rtype, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_lrs1_rtype, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_lrs2_rtype, // @[rob.scala:204:14]
output io_commit_uops_0_frs3_en, // @[rob.scala:204:14]
output io_commit_uops_0_fcn_dw, // @[rob.scala:204:14]
output [4:0] io_commit_uops_0_fcn_op, // @[rob.scala:204:14]
output io_commit_uops_0_fp_val, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_fp_rm, // @[rob.scala:204:14]
output [1:0] io_commit_uops_0_fp_typ, // @[rob.scala:204:14]
output io_commit_uops_0_xcpt_pf_if, // @[rob.scala:204:14]
output io_commit_uops_0_xcpt_ae_if, // @[rob.scala:204:14]
output io_commit_uops_0_xcpt_ma_if, // @[rob.scala:204:14]
output io_commit_uops_0_bp_debug_if, // @[rob.scala:204:14]
output io_commit_uops_0_bp_xcpt_if, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_debug_fsrc, // @[rob.scala:204:14]
output [2:0] io_commit_uops_0_debug_tsrc, // @[rob.scala:204:14]
output [31:0] io_commit_uops_1_inst, // @[rob.scala:204:14]
output [31:0] io_commit_uops_1_debug_inst, // @[rob.scala:204:14]
output io_commit_uops_1_is_rvc, // @[rob.scala:204:14]
output [39:0] io_commit_uops_1_debug_pc, // @[rob.scala:204:14]
output io_commit_uops_1_iq_type_0, // @[rob.scala:204:14]
output io_commit_uops_1_iq_type_1, // @[rob.scala:204:14]
output io_commit_uops_1_iq_type_2, // @[rob.scala:204:14]
output io_commit_uops_1_iq_type_3, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_0, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_1, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_2, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_3, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_4, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_5, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_6, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_7, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_8, // @[rob.scala:204:14]
output io_commit_uops_1_fu_code_9, // @[rob.scala:204:14]
output io_commit_uops_1_iw_issued, // @[rob.scala:204:14]
output io_commit_uops_1_iw_issued_partial_agen, // @[rob.scala:204:14]
output io_commit_uops_1_iw_issued_partial_dgen, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_iw_p1_speculative_child, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_iw_p2_speculative_child, // @[rob.scala:204:14]
output io_commit_uops_1_iw_p1_bypass_hint, // @[rob.scala:204:14]
output io_commit_uops_1_iw_p2_bypass_hint, // @[rob.scala:204:14]
output io_commit_uops_1_iw_p3_bypass_hint, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_dis_col_sel, // @[rob.scala:204:14]
output [11:0] io_commit_uops_1_br_mask, // @[rob.scala:204:14]
output [3:0] io_commit_uops_1_br_tag, // @[rob.scala:204:14]
output [3:0] io_commit_uops_1_br_type, // @[rob.scala:204:14]
output io_commit_uops_1_is_sfb, // @[rob.scala:204:14]
output io_commit_uops_1_is_fence, // @[rob.scala:204:14]
output io_commit_uops_1_is_fencei, // @[rob.scala:204:14]
output io_commit_uops_1_is_sfence, // @[rob.scala:204:14]
output io_commit_uops_1_is_amo, // @[rob.scala:204:14]
output io_commit_uops_1_is_eret, // @[rob.scala:204:14]
output io_commit_uops_1_is_sys_pc2epc, // @[rob.scala:204:14]
output io_commit_uops_1_is_rocc, // @[rob.scala:204:14]
output io_commit_uops_1_is_mov, // @[rob.scala:204:14]
output [4:0] io_commit_uops_1_ftq_idx, // @[rob.scala:204:14]
output io_commit_uops_1_edge_inst, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_pc_lob, // @[rob.scala:204:14]
output io_commit_uops_1_taken, // @[rob.scala:204:14]
output io_commit_uops_1_imm_rename, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_imm_sel, // @[rob.scala:204:14]
output [4:0] io_commit_uops_1_pimm, // @[rob.scala:204:14]
output [19:0] io_commit_uops_1_imm_packed, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_op1_sel, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_op2_sel, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_ldst, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_wen, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_ren1, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_ren2, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_ren3, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_swap12, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_swap23, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_fp_ctrl_typeTagIn, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_fp_ctrl_typeTagOut, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_fromint, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_toint, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_fastpipe, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_fma, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_div, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_sqrt, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_wflags, // @[rob.scala:204:14]
output io_commit_uops_1_fp_ctrl_vec, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_rob_idx, // @[rob.scala:204:14]
output [3:0] io_commit_uops_1_ldq_idx, // @[rob.scala:204:14]
output [3:0] io_commit_uops_1_stq_idx, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_rxq_idx, // @[rob.scala:204:14]
output [6:0] io_commit_uops_1_pdst, // @[rob.scala:204:14]
output [6:0] io_commit_uops_1_prs1, // @[rob.scala:204:14]
output [6:0] io_commit_uops_1_prs2, // @[rob.scala:204:14]
output [6:0] io_commit_uops_1_prs3, // @[rob.scala:204:14]
output [4:0] io_commit_uops_1_ppred, // @[rob.scala:204:14]
output io_commit_uops_1_prs1_busy, // @[rob.scala:204:14]
output io_commit_uops_1_prs2_busy, // @[rob.scala:204:14]
output io_commit_uops_1_prs3_busy, // @[rob.scala:204:14]
output io_commit_uops_1_ppred_busy, // @[rob.scala:204:14]
output [6:0] io_commit_uops_1_stale_pdst, // @[rob.scala:204:14]
output io_commit_uops_1_exception, // @[rob.scala:204:14]
output [63:0] io_commit_uops_1_exc_cause, // @[rob.scala:204:14]
output [4:0] io_commit_uops_1_mem_cmd, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_mem_size, // @[rob.scala:204:14]
output io_commit_uops_1_mem_signed, // @[rob.scala:204:14]
output io_commit_uops_1_uses_ldq, // @[rob.scala:204:14]
output io_commit_uops_1_uses_stq, // @[rob.scala:204:14]
output io_commit_uops_1_is_unique, // @[rob.scala:204:14]
output io_commit_uops_1_flush_on_commit, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_csr_cmd, // @[rob.scala:204:14]
output io_commit_uops_1_ldst_is_rs1, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_ldst, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_lrs1, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_lrs2, // @[rob.scala:204:14]
output [5:0] io_commit_uops_1_lrs3, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_dst_rtype, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_lrs1_rtype, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_lrs2_rtype, // @[rob.scala:204:14]
output io_commit_uops_1_frs3_en, // @[rob.scala:204:14]
output io_commit_uops_1_fcn_dw, // @[rob.scala:204:14]
output [4:0] io_commit_uops_1_fcn_op, // @[rob.scala:204:14]
output io_commit_uops_1_fp_val, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_fp_rm, // @[rob.scala:204:14]
output [1:0] io_commit_uops_1_fp_typ, // @[rob.scala:204:14]
output io_commit_uops_1_xcpt_pf_if, // @[rob.scala:204:14]
output io_commit_uops_1_xcpt_ae_if, // @[rob.scala:204:14]
output io_commit_uops_1_xcpt_ma_if, // @[rob.scala:204:14]
output io_commit_uops_1_bp_debug_if, // @[rob.scala:204:14]
output io_commit_uops_1_bp_xcpt_if, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_debug_fsrc, // @[rob.scala:204:14]
output [2:0] io_commit_uops_1_debug_tsrc, // @[rob.scala:204:14]
output io_commit_fflags_valid, // @[rob.scala:204:14]
output [4:0] io_commit_fflags_bits, // @[rob.scala:204:14]
output [63:0] io_commit_debug_wdata_0, // @[rob.scala:204:14]
output [63:0] io_commit_debug_wdata_1, // @[rob.scala:204:14]
output io_rollback, // @[rob.scala:204:14]
output io_com_load_is_at_rob_head, // @[rob.scala:204:14]
output io_com_xcpt_valid, // @[rob.scala:204:14]
output [4:0] io_com_xcpt_bits_ftq_idx, // @[rob.scala:204:14]
output io_com_xcpt_bits_edge_inst, // @[rob.scala:204:14]
output [5:0] io_com_xcpt_bits_pc_lob, // @[rob.scala:204:14]
output [63:0] io_com_xcpt_bits_cause, // @[rob.scala:204:14]
output [63:0] io_com_xcpt_bits_badvaddr, // @[rob.scala:204:14]
input io_csr_stall, // @[rob.scala:204:14]
output io_flush_valid, // @[rob.scala:204:14]
output [4:0] io_flush_bits_ftq_idx, // @[rob.scala:204:14]
output io_flush_bits_edge_inst, // @[rob.scala:204:14]
output io_flush_bits_is_rvc, // @[rob.scala:204:14]
output [5:0] io_flush_bits_pc_lob, // @[rob.scala:204:14]
output [2:0] io_flush_bits_flush_typ, // @[rob.scala:204:14]
output io_empty, // @[rob.scala:204:14]
output io_ready, // @[rob.scala:204:14]
output io_flush_frontend, // @[rob.scala:204:14]
input [63:0] io_debug_tsc // @[rob.scala:204:14]
);
wire [6:0] rob_compact_uop_bypassed_1_pdst; // @[rob.scala:349:15]
wire [5:0] rob_compact_uop_bypassed_1_ldst; // @[rob.scala:349:15]
wire [1:0] rob_compact_uop_bypassed_1_dst_rtype; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_1_uses_stq; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_1_uses_ldq; // @[rob.scala:349:15]
wire [4:0] rob_compact_uop_bypassed_1_ftq_idx; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_1_is_fencei; // @[rob.scala:349:15]
wire [6:0] rob_compact_uop_bypassed_0_pdst; // @[rob.scala:349:15]
wire [5:0] rob_compact_uop_bypassed_0_ldst; // @[rob.scala:349:15]
wire [1:0] rob_compact_uop_bypassed_0_dst_rtype; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_0_uses_stq; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_0_uses_ldq; // @[rob.scala:349:15]
wire [4:0] rob_compact_uop_bypassed_0_ftq_idx; // @[rob.scala:349:15]
wire rob_compact_uop_bypassed_0_is_fencei; // @[rob.scala:349:15]
wire io_commit_uops_1_uses_stq_0; // @[rob.scala:199:7]
wire io_commit_uops_1_uses_ldq_0; // @[rob.scala:199:7]
wire io_commit_uops_0_uses_stq_0; // @[rob.scala:199:7]
wire io_commit_uops_0_uses_ldq_0; // @[rob.scala:199:7]
wire [59:0] _rob_compact_uop_mem_R0_data; // @[rob.scala:337:40]
wire io_enq_valids_0_0 = io_enq_valids_0; // @[rob.scala:199:7]
wire io_enq_valids_1_0 = io_enq_valids_1; // @[rob.scala:199:7]
wire [31:0] io_enq_uops_0_inst_0 = io_enq_uops_0_inst; // @[rob.scala:199:7]
wire [31:0] io_enq_uops_0_debug_inst_0 = io_enq_uops_0_debug_inst; // @[rob.scala:199:7]
wire io_enq_uops_0_is_rvc_0 = io_enq_uops_0_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_enq_uops_0_debug_pc_0 = io_enq_uops_0_debug_pc; // @[rob.scala:199:7]
wire io_enq_uops_0_iq_type_0_0 = io_enq_uops_0_iq_type_0; // @[rob.scala:199:7]
wire io_enq_uops_0_iq_type_1_0 = io_enq_uops_0_iq_type_1; // @[rob.scala:199:7]
wire io_enq_uops_0_iq_type_2_0 = io_enq_uops_0_iq_type_2; // @[rob.scala:199:7]
wire io_enq_uops_0_iq_type_3_0 = io_enq_uops_0_iq_type_3; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_0_0 = io_enq_uops_0_fu_code_0; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_1_0 = io_enq_uops_0_fu_code_1; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_2_0 = io_enq_uops_0_fu_code_2; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_3_0 = io_enq_uops_0_fu_code_3; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_4_0 = io_enq_uops_0_fu_code_4; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_5_0 = io_enq_uops_0_fu_code_5; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_6_0 = io_enq_uops_0_fu_code_6; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_7_0 = io_enq_uops_0_fu_code_7; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_8_0 = io_enq_uops_0_fu_code_8; // @[rob.scala:199:7]
wire io_enq_uops_0_fu_code_9_0 = io_enq_uops_0_fu_code_9; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_issued_0 = io_enq_uops_0_iw_issued; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_issued_partial_agen_0 = io_enq_uops_0_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_issued_partial_dgen_0 = io_enq_uops_0_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_iw_p1_speculative_child_0 = io_enq_uops_0_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_iw_p2_speculative_child_0 = io_enq_uops_0_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_p1_bypass_hint_0 = io_enq_uops_0_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_p2_bypass_hint_0 = io_enq_uops_0_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_enq_uops_0_iw_p3_bypass_hint_0 = io_enq_uops_0_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_dis_col_sel_0 = io_enq_uops_0_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_enq_uops_0_br_mask_0 = io_enq_uops_0_br_mask; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_0_br_tag_0 = io_enq_uops_0_br_tag; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_0_br_type_0 = io_enq_uops_0_br_type; // @[rob.scala:199:7]
wire io_enq_uops_0_is_sfb_0 = io_enq_uops_0_is_sfb; // @[rob.scala:199:7]
wire io_enq_uops_0_is_fence_0 = io_enq_uops_0_is_fence; // @[rob.scala:199:7]
wire io_enq_uops_0_is_fencei_0 = io_enq_uops_0_is_fencei; // @[rob.scala:199:7]
wire io_enq_uops_0_is_sfence_0 = io_enq_uops_0_is_sfence; // @[rob.scala:199:7]
wire io_enq_uops_0_is_amo_0 = io_enq_uops_0_is_amo; // @[rob.scala:199:7]
wire io_enq_uops_0_is_eret_0 = io_enq_uops_0_is_eret; // @[rob.scala:199:7]
wire io_enq_uops_0_is_sys_pc2epc_0 = io_enq_uops_0_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_enq_uops_0_is_rocc_0 = io_enq_uops_0_is_rocc; // @[rob.scala:199:7]
wire io_enq_uops_0_is_mov_0 = io_enq_uops_0_is_mov; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_0_ftq_idx_0 = io_enq_uops_0_ftq_idx; // @[rob.scala:199:7]
wire io_enq_uops_0_edge_inst_0 = io_enq_uops_0_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_pc_lob_0 = io_enq_uops_0_pc_lob; // @[rob.scala:199:7]
wire io_enq_uops_0_taken_0 = io_enq_uops_0_taken; // @[rob.scala:199:7]
wire io_enq_uops_0_imm_rename_0 = io_enq_uops_0_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_imm_sel_0 = io_enq_uops_0_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_0_pimm_0 = io_enq_uops_0_pimm; // @[rob.scala:199:7]
wire [19:0] io_enq_uops_0_imm_packed_0 = io_enq_uops_0_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_op1_sel_0 = io_enq_uops_0_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_op2_sel_0 = io_enq_uops_0_op2_sel; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_ldst_0 = io_enq_uops_0_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_wen_0 = io_enq_uops_0_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_ren1_0 = io_enq_uops_0_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_ren2_0 = io_enq_uops_0_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_ren3_0 = io_enq_uops_0_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_swap12_0 = io_enq_uops_0_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_swap23_0 = io_enq_uops_0_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_fp_ctrl_typeTagIn_0 = io_enq_uops_0_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_fp_ctrl_typeTagOut_0 = io_enq_uops_0_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_fromint_0 = io_enq_uops_0_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_toint_0 = io_enq_uops_0_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_fastpipe_0 = io_enq_uops_0_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_fma_0 = io_enq_uops_0_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_div_0 = io_enq_uops_0_fp_ctrl_div; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_sqrt_0 = io_enq_uops_0_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_wflags_0 = io_enq_uops_0_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_ctrl_vec_0 = io_enq_uops_0_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_rob_idx_0 = io_enq_uops_0_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_0_ldq_idx_0 = io_enq_uops_0_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_0_stq_idx_0 = io_enq_uops_0_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_rxq_idx_0 = io_enq_uops_0_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_0_pdst_0 = io_enq_uops_0_pdst; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_0_prs1_0 = io_enq_uops_0_prs1; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_0_prs2_0 = io_enq_uops_0_prs2; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_0_prs3_0 = io_enq_uops_0_prs3; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_0_ppred_0 = io_enq_uops_0_ppred; // @[rob.scala:199:7]
wire io_enq_uops_0_prs1_busy_0 = io_enq_uops_0_prs1_busy; // @[rob.scala:199:7]
wire io_enq_uops_0_prs2_busy_0 = io_enq_uops_0_prs2_busy; // @[rob.scala:199:7]
wire io_enq_uops_0_prs3_busy_0 = io_enq_uops_0_prs3_busy; // @[rob.scala:199:7]
wire io_enq_uops_0_ppred_busy_0 = io_enq_uops_0_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_0_stale_pdst_0 = io_enq_uops_0_stale_pdst; // @[rob.scala:199:7]
wire io_enq_uops_0_exception_0 = io_enq_uops_0_exception; // @[rob.scala:199:7]
wire [63:0] io_enq_uops_0_exc_cause_0 = io_enq_uops_0_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_0_mem_cmd_0 = io_enq_uops_0_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_mem_size_0 = io_enq_uops_0_mem_size; // @[rob.scala:199:7]
wire io_enq_uops_0_mem_signed_0 = io_enq_uops_0_mem_signed; // @[rob.scala:199:7]
wire io_enq_uops_0_uses_ldq_0 = io_enq_uops_0_uses_ldq; // @[rob.scala:199:7]
wire io_enq_uops_0_uses_stq_0 = io_enq_uops_0_uses_stq; // @[rob.scala:199:7]
wire io_enq_uops_0_is_unique_0 = io_enq_uops_0_is_unique; // @[rob.scala:199:7]
wire io_enq_uops_0_flush_on_commit_0 = io_enq_uops_0_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_csr_cmd_0 = io_enq_uops_0_csr_cmd; // @[rob.scala:199:7]
wire io_enq_uops_0_ldst_is_rs1_0 = io_enq_uops_0_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_ldst_0 = io_enq_uops_0_ldst; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_lrs1_0 = io_enq_uops_0_lrs1; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_lrs2_0 = io_enq_uops_0_lrs2; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_0_lrs3_0 = io_enq_uops_0_lrs3; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_dst_rtype_0 = io_enq_uops_0_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_lrs1_rtype_0 = io_enq_uops_0_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_lrs2_rtype_0 = io_enq_uops_0_lrs2_rtype; // @[rob.scala:199:7]
wire io_enq_uops_0_frs3_en_0 = io_enq_uops_0_frs3_en; // @[rob.scala:199:7]
wire io_enq_uops_0_fcn_dw_0 = io_enq_uops_0_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_0_fcn_op_0 = io_enq_uops_0_fcn_op; // @[rob.scala:199:7]
wire io_enq_uops_0_fp_val_0 = io_enq_uops_0_fp_val; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_fp_rm_0 = io_enq_uops_0_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_0_fp_typ_0 = io_enq_uops_0_fp_typ; // @[rob.scala:199:7]
wire io_enq_uops_0_xcpt_pf_if_0 = io_enq_uops_0_xcpt_pf_if; // @[rob.scala:199:7]
wire io_enq_uops_0_xcpt_ae_if_0 = io_enq_uops_0_xcpt_ae_if; // @[rob.scala:199:7]
wire io_enq_uops_0_xcpt_ma_if_0 = io_enq_uops_0_xcpt_ma_if; // @[rob.scala:199:7]
wire io_enq_uops_0_bp_debug_if_0 = io_enq_uops_0_bp_debug_if; // @[rob.scala:199:7]
wire io_enq_uops_0_bp_xcpt_if_0 = io_enq_uops_0_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_debug_fsrc_0 = io_enq_uops_0_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_0_debug_tsrc_0 = io_enq_uops_0_debug_tsrc; // @[rob.scala:199:7]
wire [31:0] io_enq_uops_1_inst_0 = io_enq_uops_1_inst; // @[rob.scala:199:7]
wire [31:0] io_enq_uops_1_debug_inst_0 = io_enq_uops_1_debug_inst; // @[rob.scala:199:7]
wire io_enq_uops_1_is_rvc_0 = io_enq_uops_1_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_enq_uops_1_debug_pc_0 = io_enq_uops_1_debug_pc; // @[rob.scala:199:7]
wire io_enq_uops_1_iq_type_0_0 = io_enq_uops_1_iq_type_0; // @[rob.scala:199:7]
wire io_enq_uops_1_iq_type_1_0 = io_enq_uops_1_iq_type_1; // @[rob.scala:199:7]
wire io_enq_uops_1_iq_type_2_0 = io_enq_uops_1_iq_type_2; // @[rob.scala:199:7]
wire io_enq_uops_1_iq_type_3_0 = io_enq_uops_1_iq_type_3; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_0_0 = io_enq_uops_1_fu_code_0; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_1_0 = io_enq_uops_1_fu_code_1; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_2_0 = io_enq_uops_1_fu_code_2; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_3_0 = io_enq_uops_1_fu_code_3; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_4_0 = io_enq_uops_1_fu_code_4; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_5_0 = io_enq_uops_1_fu_code_5; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_6_0 = io_enq_uops_1_fu_code_6; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_7_0 = io_enq_uops_1_fu_code_7; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_8_0 = io_enq_uops_1_fu_code_8; // @[rob.scala:199:7]
wire io_enq_uops_1_fu_code_9_0 = io_enq_uops_1_fu_code_9; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_issued_0 = io_enq_uops_1_iw_issued; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_issued_partial_agen_0 = io_enq_uops_1_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_issued_partial_dgen_0 = io_enq_uops_1_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_iw_p1_speculative_child_0 = io_enq_uops_1_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_iw_p2_speculative_child_0 = io_enq_uops_1_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_p1_bypass_hint_0 = io_enq_uops_1_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_p2_bypass_hint_0 = io_enq_uops_1_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_enq_uops_1_iw_p3_bypass_hint_0 = io_enq_uops_1_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_dis_col_sel_0 = io_enq_uops_1_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_enq_uops_1_br_mask_0 = io_enq_uops_1_br_mask; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_1_br_tag_0 = io_enq_uops_1_br_tag; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_1_br_type_0 = io_enq_uops_1_br_type; // @[rob.scala:199:7]
wire io_enq_uops_1_is_sfb_0 = io_enq_uops_1_is_sfb; // @[rob.scala:199:7]
wire io_enq_uops_1_is_fence_0 = io_enq_uops_1_is_fence; // @[rob.scala:199:7]
wire io_enq_uops_1_is_fencei_0 = io_enq_uops_1_is_fencei; // @[rob.scala:199:7]
wire io_enq_uops_1_is_sfence_0 = io_enq_uops_1_is_sfence; // @[rob.scala:199:7]
wire io_enq_uops_1_is_amo_0 = io_enq_uops_1_is_amo; // @[rob.scala:199:7]
wire io_enq_uops_1_is_eret_0 = io_enq_uops_1_is_eret; // @[rob.scala:199:7]
wire io_enq_uops_1_is_sys_pc2epc_0 = io_enq_uops_1_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_enq_uops_1_is_rocc_0 = io_enq_uops_1_is_rocc; // @[rob.scala:199:7]
wire io_enq_uops_1_is_mov_0 = io_enq_uops_1_is_mov; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_1_ftq_idx_0 = io_enq_uops_1_ftq_idx; // @[rob.scala:199:7]
wire io_enq_uops_1_edge_inst_0 = io_enq_uops_1_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_pc_lob_0 = io_enq_uops_1_pc_lob; // @[rob.scala:199:7]
wire io_enq_uops_1_taken_0 = io_enq_uops_1_taken; // @[rob.scala:199:7]
wire io_enq_uops_1_imm_rename_0 = io_enq_uops_1_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_imm_sel_0 = io_enq_uops_1_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_1_pimm_0 = io_enq_uops_1_pimm; // @[rob.scala:199:7]
wire [19:0] io_enq_uops_1_imm_packed_0 = io_enq_uops_1_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_op1_sel_0 = io_enq_uops_1_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_op2_sel_0 = io_enq_uops_1_op2_sel; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_ldst_0 = io_enq_uops_1_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_wen_0 = io_enq_uops_1_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_ren1_0 = io_enq_uops_1_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_ren2_0 = io_enq_uops_1_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_ren3_0 = io_enq_uops_1_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_swap12_0 = io_enq_uops_1_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_swap23_0 = io_enq_uops_1_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_fp_ctrl_typeTagIn_0 = io_enq_uops_1_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_fp_ctrl_typeTagOut_0 = io_enq_uops_1_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_fromint_0 = io_enq_uops_1_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_toint_0 = io_enq_uops_1_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_fastpipe_0 = io_enq_uops_1_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_fma_0 = io_enq_uops_1_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_div_0 = io_enq_uops_1_fp_ctrl_div; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_sqrt_0 = io_enq_uops_1_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_wflags_0 = io_enq_uops_1_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_ctrl_vec_0 = io_enq_uops_1_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_rob_idx_0 = io_enq_uops_1_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_1_ldq_idx_0 = io_enq_uops_1_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_enq_uops_1_stq_idx_0 = io_enq_uops_1_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_rxq_idx_0 = io_enq_uops_1_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_1_pdst_0 = io_enq_uops_1_pdst; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_1_prs1_0 = io_enq_uops_1_prs1; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_1_prs2_0 = io_enq_uops_1_prs2; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_1_prs3_0 = io_enq_uops_1_prs3; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_1_ppred_0 = io_enq_uops_1_ppred; // @[rob.scala:199:7]
wire io_enq_uops_1_prs1_busy_0 = io_enq_uops_1_prs1_busy; // @[rob.scala:199:7]
wire io_enq_uops_1_prs2_busy_0 = io_enq_uops_1_prs2_busy; // @[rob.scala:199:7]
wire io_enq_uops_1_prs3_busy_0 = io_enq_uops_1_prs3_busy; // @[rob.scala:199:7]
wire io_enq_uops_1_ppred_busy_0 = io_enq_uops_1_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_enq_uops_1_stale_pdst_0 = io_enq_uops_1_stale_pdst; // @[rob.scala:199:7]
wire io_enq_uops_1_exception_0 = io_enq_uops_1_exception; // @[rob.scala:199:7]
wire [63:0] io_enq_uops_1_exc_cause_0 = io_enq_uops_1_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_1_mem_cmd_0 = io_enq_uops_1_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_mem_size_0 = io_enq_uops_1_mem_size; // @[rob.scala:199:7]
wire io_enq_uops_1_mem_signed_0 = io_enq_uops_1_mem_signed; // @[rob.scala:199:7]
wire io_enq_uops_1_uses_ldq_0 = io_enq_uops_1_uses_ldq; // @[rob.scala:199:7]
wire io_enq_uops_1_uses_stq_0 = io_enq_uops_1_uses_stq; // @[rob.scala:199:7]
wire io_enq_uops_1_is_unique_0 = io_enq_uops_1_is_unique; // @[rob.scala:199:7]
wire io_enq_uops_1_flush_on_commit_0 = io_enq_uops_1_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_csr_cmd_0 = io_enq_uops_1_csr_cmd; // @[rob.scala:199:7]
wire io_enq_uops_1_ldst_is_rs1_0 = io_enq_uops_1_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_ldst_0 = io_enq_uops_1_ldst; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_lrs1_0 = io_enq_uops_1_lrs1; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_lrs2_0 = io_enq_uops_1_lrs2; // @[rob.scala:199:7]
wire [5:0] io_enq_uops_1_lrs3_0 = io_enq_uops_1_lrs3; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_dst_rtype_0 = io_enq_uops_1_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_lrs1_rtype_0 = io_enq_uops_1_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_lrs2_rtype_0 = io_enq_uops_1_lrs2_rtype; // @[rob.scala:199:7]
wire io_enq_uops_1_frs3_en_0 = io_enq_uops_1_frs3_en; // @[rob.scala:199:7]
wire io_enq_uops_1_fcn_dw_0 = io_enq_uops_1_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_enq_uops_1_fcn_op_0 = io_enq_uops_1_fcn_op; // @[rob.scala:199:7]
wire io_enq_uops_1_fp_val_0 = io_enq_uops_1_fp_val; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_fp_rm_0 = io_enq_uops_1_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_enq_uops_1_fp_typ_0 = io_enq_uops_1_fp_typ; // @[rob.scala:199:7]
wire io_enq_uops_1_xcpt_pf_if_0 = io_enq_uops_1_xcpt_pf_if; // @[rob.scala:199:7]
wire io_enq_uops_1_xcpt_ae_if_0 = io_enq_uops_1_xcpt_ae_if; // @[rob.scala:199:7]
wire io_enq_uops_1_xcpt_ma_if_0 = io_enq_uops_1_xcpt_ma_if; // @[rob.scala:199:7]
wire io_enq_uops_1_bp_debug_if_0 = io_enq_uops_1_bp_debug_if; // @[rob.scala:199:7]
wire io_enq_uops_1_bp_xcpt_if_0 = io_enq_uops_1_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_debug_fsrc_0 = io_enq_uops_1_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_enq_uops_1_debug_tsrc_0 = io_enq_uops_1_debug_tsrc; // @[rob.scala:199:7]
wire io_enq_partial_stall_0 = io_enq_partial_stall; // @[rob.scala:199:7]
wire [39:0] io_xcpt_fetch_pc_0 = io_xcpt_fetch_pc; // @[rob.scala:199:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[rob.scala:199:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[rob.scala:199:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[rob.scala:199:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[rob.scala:199:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[rob.scala:199:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[rob.scala:199:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[rob.scala:199:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[rob.scala:199:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[rob.scala:199:7]
wire io_wb_resps_0_valid_0 = io_wb_resps_0_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_0_bits_uop_inst_0 = io_wb_resps_0_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_0_bits_uop_debug_inst_0 = io_wb_resps_0_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_rvc_0 = io_wb_resps_0_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_0_bits_uop_debug_pc_0 = io_wb_resps_0_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iq_type_0_0 = io_wb_resps_0_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iq_type_1_0 = io_wb_resps_0_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iq_type_2_0 = io_wb_resps_0_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iq_type_3_0 = io_wb_resps_0_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_0_0 = io_wb_resps_0_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_1_0 = io_wb_resps_0_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_2_0 = io_wb_resps_0_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_3_0 = io_wb_resps_0_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_4_0 = io_wb_resps_0_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_5_0 = io_wb_resps_0_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_6_0 = io_wb_resps_0_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_7_0 = io_wb_resps_0_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_8_0 = io_wb_resps_0_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fu_code_9_0 = io_wb_resps_0_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_issued_0 = io_wb_resps_0_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_0_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_0_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_0_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_0_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_0_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_0_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_0_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_dis_col_sel_0 = io_wb_resps_0_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_0_bits_uop_br_mask_0 = io_wb_resps_0_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_0_bits_uop_br_tag_0 = io_wb_resps_0_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_0_bits_uop_br_type_0 = io_wb_resps_0_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_sfb_0 = io_wb_resps_0_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_fence_0 = io_wb_resps_0_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_fencei_0 = io_wb_resps_0_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_sfence_0 = io_wb_resps_0_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_amo_0 = io_wb_resps_0_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_eret_0 = io_wb_resps_0_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_sys_pc2epc_0 = io_wb_resps_0_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_rocc_0 = io_wb_resps_0_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_mov_0 = io_wb_resps_0_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_uop_ftq_idx_0 = io_wb_resps_0_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_edge_inst_0 = io_wb_resps_0_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_pc_lob_0 = io_wb_resps_0_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_taken_0 = io_wb_resps_0_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_imm_rename_0 = io_wb_resps_0_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_imm_sel_0 = io_wb_resps_0_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_uop_pimm_0 = io_wb_resps_0_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_0_bits_uop_imm_packed_0 = io_wb_resps_0_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_op1_sel_0 = io_wb_resps_0_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_op2_sel_0 = io_wb_resps_0_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_0_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_wen_0 = io_wb_resps_0_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_0_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_0_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_0_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_0_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_0_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_0_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_0_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_0_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_toint_0 = io_wb_resps_0_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_0_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_fma_0 = io_wb_resps_0_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_div_0 = io_wb_resps_0_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_0_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_0_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_ctrl_vec_0 = io_wb_resps_0_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_rob_idx_0 = io_wb_resps_0_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_0_bits_uop_ldq_idx_0 = io_wb_resps_0_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_0_bits_uop_stq_idx_0 = io_wb_resps_0_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_rxq_idx_0 = io_wb_resps_0_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_0_bits_uop_pdst_0 = io_wb_resps_0_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_0_bits_uop_prs1_0 = io_wb_resps_0_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_0_bits_uop_prs2_0 = io_wb_resps_0_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_0_bits_uop_prs3_0 = io_wb_resps_0_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_uop_ppred_0 = io_wb_resps_0_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_prs1_busy_0 = io_wb_resps_0_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_prs2_busy_0 = io_wb_resps_0_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_prs3_busy_0 = io_wb_resps_0_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_ppred_busy_0 = io_wb_resps_0_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_0_bits_uop_stale_pdst_0 = io_wb_resps_0_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_exception_0 = io_wb_resps_0_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_0_bits_uop_exc_cause_0 = io_wb_resps_0_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_uop_mem_cmd_0 = io_wb_resps_0_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_mem_size_0 = io_wb_resps_0_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_mem_signed_0 = io_wb_resps_0_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_uses_ldq_0 = io_wb_resps_0_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_uses_stq_0 = io_wb_resps_0_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_is_unique_0 = io_wb_resps_0_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_flush_on_commit_0 = io_wb_resps_0_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_csr_cmd_0 = io_wb_resps_0_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_ldst_is_rs1_0 = io_wb_resps_0_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_ldst_0 = io_wb_resps_0_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs1_0 = io_wb_resps_0_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs2_0 = io_wb_resps_0_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_0_bits_uop_lrs3_0 = io_wb_resps_0_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_dst_rtype_0 = io_wb_resps_0_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs1_rtype_0 = io_wb_resps_0_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_lrs2_rtype_0 = io_wb_resps_0_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_frs3_en_0 = io_wb_resps_0_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fcn_dw_0 = io_wb_resps_0_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_uop_fcn_op_0 = io_wb_resps_0_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_fp_val_0 = io_wb_resps_0_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_fp_rm_0 = io_wb_resps_0_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_0_bits_uop_fp_typ_0 = io_wb_resps_0_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_xcpt_pf_if_0 = io_wb_resps_0_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_xcpt_ae_if_0 = io_wb_resps_0_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_xcpt_ma_if_0 = io_wb_resps_0_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_bp_debug_if_0 = io_wb_resps_0_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_uop_bp_xcpt_if_0 = io_wb_resps_0_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_debug_fsrc_0 = io_wb_resps_0_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_0_bits_uop_debug_tsrc_0 = io_wb_resps_0_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_0_bits_data_0 = io_wb_resps_0_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_predicated_0 = io_wb_resps_0_bits_predicated; // @[rob.scala:199:7]
wire io_wb_resps_0_bits_fflags_valid_0 = io_wb_resps_0_bits_fflags_valid; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_0_bits_fflags_bits_0 = io_wb_resps_0_bits_fflags_bits; // @[rob.scala:199:7]
wire io_wb_resps_1_valid_0 = io_wb_resps_1_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_1_bits_uop_inst_0 = io_wb_resps_1_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_1_bits_uop_debug_inst_0 = io_wb_resps_1_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_rvc_0 = io_wb_resps_1_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_1_bits_uop_debug_pc_0 = io_wb_resps_1_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iq_type_0_0 = io_wb_resps_1_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iq_type_1_0 = io_wb_resps_1_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iq_type_2_0 = io_wb_resps_1_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iq_type_3_0 = io_wb_resps_1_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_0_0 = io_wb_resps_1_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_1_0 = io_wb_resps_1_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_2_0 = io_wb_resps_1_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_3_0 = io_wb_resps_1_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_4_0 = io_wb_resps_1_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_5_0 = io_wb_resps_1_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_6_0 = io_wb_resps_1_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_7_0 = io_wb_resps_1_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_8_0 = io_wb_resps_1_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fu_code_9_0 = io_wb_resps_1_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_issued_0 = io_wb_resps_1_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_1_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_1_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_1_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_1_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_1_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_1_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_1_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_dis_col_sel_0 = io_wb_resps_1_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_1_bits_uop_br_mask_0 = io_wb_resps_1_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_1_bits_uop_br_tag_0 = io_wb_resps_1_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_1_bits_uop_br_type_0 = io_wb_resps_1_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_sfb_0 = io_wb_resps_1_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_fence_0 = io_wb_resps_1_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_fencei_0 = io_wb_resps_1_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_sfence_0 = io_wb_resps_1_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_amo_0 = io_wb_resps_1_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_eret_0 = io_wb_resps_1_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_sys_pc2epc_0 = io_wb_resps_1_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_rocc_0 = io_wb_resps_1_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_mov_0 = io_wb_resps_1_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_uop_ftq_idx_0 = io_wb_resps_1_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_edge_inst_0 = io_wb_resps_1_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_pc_lob_0 = io_wb_resps_1_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_taken_0 = io_wb_resps_1_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_imm_rename_0 = io_wb_resps_1_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_imm_sel_0 = io_wb_resps_1_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_uop_pimm_0 = io_wb_resps_1_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_1_bits_uop_imm_packed_0 = io_wb_resps_1_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_op1_sel_0 = io_wb_resps_1_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_op2_sel_0 = io_wb_resps_1_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_1_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_wen_0 = io_wb_resps_1_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_1_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_1_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_1_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_1_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_1_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_1_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_1_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_1_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_toint_0 = io_wb_resps_1_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_1_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_fma_0 = io_wb_resps_1_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_div_0 = io_wb_resps_1_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_1_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_1_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_ctrl_vec_0 = io_wb_resps_1_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_rob_idx_0 = io_wb_resps_1_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_1_bits_uop_ldq_idx_0 = io_wb_resps_1_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_1_bits_uop_stq_idx_0 = io_wb_resps_1_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_rxq_idx_0 = io_wb_resps_1_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_1_bits_uop_pdst_0 = io_wb_resps_1_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_1_bits_uop_prs1_0 = io_wb_resps_1_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_1_bits_uop_prs2_0 = io_wb_resps_1_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_1_bits_uop_prs3_0 = io_wb_resps_1_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_uop_ppred_0 = io_wb_resps_1_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_prs1_busy_0 = io_wb_resps_1_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_prs2_busy_0 = io_wb_resps_1_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_prs3_busy_0 = io_wb_resps_1_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_ppred_busy_0 = io_wb_resps_1_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_1_bits_uop_stale_pdst_0 = io_wb_resps_1_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_exception_0 = io_wb_resps_1_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_1_bits_uop_exc_cause_0 = io_wb_resps_1_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_uop_mem_cmd_0 = io_wb_resps_1_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_mem_size_0 = io_wb_resps_1_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_mem_signed_0 = io_wb_resps_1_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_uses_ldq_0 = io_wb_resps_1_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_uses_stq_0 = io_wb_resps_1_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_is_unique_0 = io_wb_resps_1_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_flush_on_commit_0 = io_wb_resps_1_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_csr_cmd_0 = io_wb_resps_1_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_ldst_is_rs1_0 = io_wb_resps_1_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_ldst_0 = io_wb_resps_1_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs1_0 = io_wb_resps_1_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs2_0 = io_wb_resps_1_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_1_bits_uop_lrs3_0 = io_wb_resps_1_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_dst_rtype_0 = io_wb_resps_1_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs1_rtype_0 = io_wb_resps_1_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_lrs2_rtype_0 = io_wb_resps_1_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_frs3_en_0 = io_wb_resps_1_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fcn_dw_0 = io_wb_resps_1_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_uop_fcn_op_0 = io_wb_resps_1_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_fp_val_0 = io_wb_resps_1_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_fp_rm_0 = io_wb_resps_1_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_1_bits_uop_fp_typ_0 = io_wb_resps_1_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_xcpt_pf_if_0 = io_wb_resps_1_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_xcpt_ae_if_0 = io_wb_resps_1_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_xcpt_ma_if_0 = io_wb_resps_1_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_bp_debug_if_0 = io_wb_resps_1_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_uop_bp_xcpt_if_0 = io_wb_resps_1_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_debug_fsrc_0 = io_wb_resps_1_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_1_bits_uop_debug_tsrc_0 = io_wb_resps_1_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_1_bits_data_0 = io_wb_resps_1_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_predicated_0 = io_wb_resps_1_bits_predicated; // @[rob.scala:199:7]
wire io_wb_resps_1_bits_fflags_valid_0 = io_wb_resps_1_bits_fflags_valid; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_1_bits_fflags_bits_0 = io_wb_resps_1_bits_fflags_bits; // @[rob.scala:199:7]
wire io_wb_resps_2_valid_0 = io_wb_resps_2_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_2_bits_uop_inst_0 = io_wb_resps_2_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_2_bits_uop_debug_inst_0 = io_wb_resps_2_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_rvc_0 = io_wb_resps_2_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_2_bits_uop_debug_pc_0 = io_wb_resps_2_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iq_type_0_0 = io_wb_resps_2_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iq_type_1_0 = io_wb_resps_2_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iq_type_2_0 = io_wb_resps_2_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iq_type_3_0 = io_wb_resps_2_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_0_0 = io_wb_resps_2_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_1_0 = io_wb_resps_2_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_2_0 = io_wb_resps_2_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_3_0 = io_wb_resps_2_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_4_0 = io_wb_resps_2_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_5_0 = io_wb_resps_2_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_6_0 = io_wb_resps_2_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_7_0 = io_wb_resps_2_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_8_0 = io_wb_resps_2_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fu_code_9_0 = io_wb_resps_2_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_issued_0 = io_wb_resps_2_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_2_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_2_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_2_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_2_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_2_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_2_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_2_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_dis_col_sel_0 = io_wb_resps_2_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_2_bits_uop_br_mask_0 = io_wb_resps_2_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_2_bits_uop_br_tag_0 = io_wb_resps_2_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_2_bits_uop_br_type_0 = io_wb_resps_2_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_sfb_0 = io_wb_resps_2_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_fence_0 = io_wb_resps_2_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_fencei_0 = io_wb_resps_2_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_sfence_0 = io_wb_resps_2_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_amo_0 = io_wb_resps_2_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_eret_0 = io_wb_resps_2_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_sys_pc2epc_0 = io_wb_resps_2_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_rocc_0 = io_wb_resps_2_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_mov_0 = io_wb_resps_2_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_2_bits_uop_ftq_idx_0 = io_wb_resps_2_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_edge_inst_0 = io_wb_resps_2_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_pc_lob_0 = io_wb_resps_2_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_taken_0 = io_wb_resps_2_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_imm_rename_0 = io_wb_resps_2_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_imm_sel_0 = io_wb_resps_2_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_2_bits_uop_pimm_0 = io_wb_resps_2_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_2_bits_uop_imm_packed_0 = io_wb_resps_2_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_op1_sel_0 = io_wb_resps_2_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_op2_sel_0 = io_wb_resps_2_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_2_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_wen_0 = io_wb_resps_2_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_2_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_2_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_2_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_2_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_2_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_2_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_2_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_2_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_toint_0 = io_wb_resps_2_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_2_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_fma_0 = io_wb_resps_2_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_div_0 = io_wb_resps_2_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_2_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_2_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_ctrl_vec_0 = io_wb_resps_2_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_rob_idx_0 = io_wb_resps_2_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_2_bits_uop_ldq_idx_0 = io_wb_resps_2_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_2_bits_uop_stq_idx_0 = io_wb_resps_2_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_rxq_idx_0 = io_wb_resps_2_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_2_bits_uop_pdst_0 = io_wb_resps_2_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_2_bits_uop_prs1_0 = io_wb_resps_2_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_2_bits_uop_prs2_0 = io_wb_resps_2_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_2_bits_uop_prs3_0 = io_wb_resps_2_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_2_bits_uop_ppred_0 = io_wb_resps_2_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_prs1_busy_0 = io_wb_resps_2_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_prs2_busy_0 = io_wb_resps_2_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_prs3_busy_0 = io_wb_resps_2_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_ppred_busy_0 = io_wb_resps_2_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_2_bits_uop_stale_pdst_0 = io_wb_resps_2_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_exception_0 = io_wb_resps_2_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_2_bits_uop_exc_cause_0 = io_wb_resps_2_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_2_bits_uop_mem_cmd_0 = io_wb_resps_2_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_mem_size_0 = io_wb_resps_2_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_mem_signed_0 = io_wb_resps_2_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_uses_ldq_0 = io_wb_resps_2_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_uses_stq_0 = io_wb_resps_2_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_is_unique_0 = io_wb_resps_2_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_flush_on_commit_0 = io_wb_resps_2_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_csr_cmd_0 = io_wb_resps_2_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_ldst_is_rs1_0 = io_wb_resps_2_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_ldst_0 = io_wb_resps_2_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs1_0 = io_wb_resps_2_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs2_0 = io_wb_resps_2_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_2_bits_uop_lrs3_0 = io_wb_resps_2_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_dst_rtype_0 = io_wb_resps_2_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs1_rtype_0 = io_wb_resps_2_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_lrs2_rtype_0 = io_wb_resps_2_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_frs3_en_0 = io_wb_resps_2_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fcn_dw_0 = io_wb_resps_2_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_2_bits_uop_fcn_op_0 = io_wb_resps_2_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_fp_val_0 = io_wb_resps_2_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_fp_rm_0 = io_wb_resps_2_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_2_bits_uop_fp_typ_0 = io_wb_resps_2_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_xcpt_pf_if_0 = io_wb_resps_2_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_xcpt_ae_if_0 = io_wb_resps_2_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_xcpt_ma_if_0 = io_wb_resps_2_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_bp_debug_if_0 = io_wb_resps_2_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_uop_bp_xcpt_if_0 = io_wb_resps_2_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_debug_fsrc_0 = io_wb_resps_2_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_2_bits_uop_debug_tsrc_0 = io_wb_resps_2_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_2_bits_data_0 = io_wb_resps_2_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_2_bits_predicated_0 = io_wb_resps_2_bits_predicated; // @[rob.scala:199:7]
wire io_wb_resps_3_valid_0 = io_wb_resps_3_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_3_bits_uop_inst_0 = io_wb_resps_3_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_3_bits_uop_debug_inst_0 = io_wb_resps_3_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_rvc_0 = io_wb_resps_3_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_3_bits_uop_debug_pc_0 = io_wb_resps_3_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iq_type_0_0 = io_wb_resps_3_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iq_type_1_0 = io_wb_resps_3_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iq_type_2_0 = io_wb_resps_3_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iq_type_3_0 = io_wb_resps_3_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_0_0 = io_wb_resps_3_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_1_0 = io_wb_resps_3_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_2_0 = io_wb_resps_3_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_3_0 = io_wb_resps_3_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_4_0 = io_wb_resps_3_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_5_0 = io_wb_resps_3_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_6_0 = io_wb_resps_3_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_7_0 = io_wb_resps_3_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_8_0 = io_wb_resps_3_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fu_code_9_0 = io_wb_resps_3_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_issued_0 = io_wb_resps_3_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_3_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_3_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_3_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_3_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_3_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_3_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_3_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_dis_col_sel_0 = io_wb_resps_3_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_3_bits_uop_br_mask_0 = io_wb_resps_3_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_3_bits_uop_br_tag_0 = io_wb_resps_3_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_3_bits_uop_br_type_0 = io_wb_resps_3_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_sfb_0 = io_wb_resps_3_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_fence_0 = io_wb_resps_3_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_fencei_0 = io_wb_resps_3_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_sfence_0 = io_wb_resps_3_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_amo_0 = io_wb_resps_3_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_eret_0 = io_wb_resps_3_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_sys_pc2epc_0 = io_wb_resps_3_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_rocc_0 = io_wb_resps_3_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_mov_0 = io_wb_resps_3_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_uop_ftq_idx_0 = io_wb_resps_3_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_edge_inst_0 = io_wb_resps_3_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_pc_lob_0 = io_wb_resps_3_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_taken_0 = io_wb_resps_3_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_imm_rename_0 = io_wb_resps_3_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_imm_sel_0 = io_wb_resps_3_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_uop_pimm_0 = io_wb_resps_3_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_3_bits_uop_imm_packed_0 = io_wb_resps_3_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_op1_sel_0 = io_wb_resps_3_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_op2_sel_0 = io_wb_resps_3_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_3_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_wen_0 = io_wb_resps_3_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_3_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_3_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_3_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_3_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_3_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_3_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_3_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_3_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_toint_0 = io_wb_resps_3_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_3_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_fma_0 = io_wb_resps_3_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_div_0 = io_wb_resps_3_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_3_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_3_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_ctrl_vec_0 = io_wb_resps_3_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_rob_idx_0 = io_wb_resps_3_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_3_bits_uop_ldq_idx_0 = io_wb_resps_3_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_3_bits_uop_stq_idx_0 = io_wb_resps_3_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_rxq_idx_0 = io_wb_resps_3_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_3_bits_uop_pdst_0 = io_wb_resps_3_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_3_bits_uop_prs1_0 = io_wb_resps_3_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_3_bits_uop_prs2_0 = io_wb_resps_3_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_3_bits_uop_prs3_0 = io_wb_resps_3_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_uop_ppred_0 = io_wb_resps_3_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_prs1_busy_0 = io_wb_resps_3_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_prs2_busy_0 = io_wb_resps_3_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_prs3_busy_0 = io_wb_resps_3_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_ppred_busy_0 = io_wb_resps_3_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_3_bits_uop_stale_pdst_0 = io_wb_resps_3_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_exception_0 = io_wb_resps_3_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_3_bits_uop_exc_cause_0 = io_wb_resps_3_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_uop_mem_cmd_0 = io_wb_resps_3_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_mem_size_0 = io_wb_resps_3_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_mem_signed_0 = io_wb_resps_3_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_uses_ldq_0 = io_wb_resps_3_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_uses_stq_0 = io_wb_resps_3_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_is_unique_0 = io_wb_resps_3_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_flush_on_commit_0 = io_wb_resps_3_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_csr_cmd_0 = io_wb_resps_3_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_ldst_is_rs1_0 = io_wb_resps_3_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_ldst_0 = io_wb_resps_3_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs1_0 = io_wb_resps_3_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs2_0 = io_wb_resps_3_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_3_bits_uop_lrs3_0 = io_wb_resps_3_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_dst_rtype_0 = io_wb_resps_3_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs1_rtype_0 = io_wb_resps_3_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_lrs2_rtype_0 = io_wb_resps_3_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_frs3_en_0 = io_wb_resps_3_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fcn_dw_0 = io_wb_resps_3_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_uop_fcn_op_0 = io_wb_resps_3_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_fp_val_0 = io_wb_resps_3_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_fp_rm_0 = io_wb_resps_3_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_3_bits_uop_fp_typ_0 = io_wb_resps_3_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_xcpt_pf_if_0 = io_wb_resps_3_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_xcpt_ae_if_0 = io_wb_resps_3_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_xcpt_ma_if_0 = io_wb_resps_3_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_bp_debug_if_0 = io_wb_resps_3_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_uop_bp_xcpt_if_0 = io_wb_resps_3_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_debug_fsrc_0 = io_wb_resps_3_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_3_bits_uop_debug_tsrc_0 = io_wb_resps_3_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_3_bits_data_0 = io_wb_resps_3_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_predicated_0 = io_wb_resps_3_bits_predicated; // @[rob.scala:199:7]
wire io_wb_resps_4_valid_0 = io_wb_resps_4_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_4_bits_uop_inst_0 = io_wb_resps_4_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_4_bits_uop_debug_inst_0 = io_wb_resps_4_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_rvc_0 = io_wb_resps_4_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_4_bits_uop_debug_pc_0 = io_wb_resps_4_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iq_type_0_0 = io_wb_resps_4_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iq_type_1_0 = io_wb_resps_4_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iq_type_2_0 = io_wb_resps_4_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iq_type_3_0 = io_wb_resps_4_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_0_0 = io_wb_resps_4_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_1_0 = io_wb_resps_4_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_2_0 = io_wb_resps_4_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_3_0 = io_wb_resps_4_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_4_0 = io_wb_resps_4_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_5_0 = io_wb_resps_4_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_6_0 = io_wb_resps_4_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_7_0 = io_wb_resps_4_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_8_0 = io_wb_resps_4_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fu_code_9_0 = io_wb_resps_4_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_issued_0 = io_wb_resps_4_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_4_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_4_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_4_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_4_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_4_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_4_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_4_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_dis_col_sel_0 = io_wb_resps_4_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_4_bits_uop_br_mask_0 = io_wb_resps_4_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_4_bits_uop_br_tag_0 = io_wb_resps_4_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_4_bits_uop_br_type_0 = io_wb_resps_4_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_sfb_0 = io_wb_resps_4_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_fence_0 = io_wb_resps_4_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_fencei_0 = io_wb_resps_4_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_sfence_0 = io_wb_resps_4_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_amo_0 = io_wb_resps_4_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_eret_0 = io_wb_resps_4_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_sys_pc2epc_0 = io_wb_resps_4_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_rocc_0 = io_wb_resps_4_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_mov_0 = io_wb_resps_4_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_uop_ftq_idx_0 = io_wb_resps_4_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_edge_inst_0 = io_wb_resps_4_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_pc_lob_0 = io_wb_resps_4_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_taken_0 = io_wb_resps_4_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_imm_rename_0 = io_wb_resps_4_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_imm_sel_0 = io_wb_resps_4_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_uop_pimm_0 = io_wb_resps_4_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_4_bits_uop_imm_packed_0 = io_wb_resps_4_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_op1_sel_0 = io_wb_resps_4_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_op2_sel_0 = io_wb_resps_4_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_4_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_wen_0 = io_wb_resps_4_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_4_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_4_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_4_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_4_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_4_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_4_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_4_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_4_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_toint_0 = io_wb_resps_4_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_4_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_fma_0 = io_wb_resps_4_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_div_0 = io_wb_resps_4_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_4_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_4_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_ctrl_vec_0 = io_wb_resps_4_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_rob_idx_0 = io_wb_resps_4_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_4_bits_uop_ldq_idx_0 = io_wb_resps_4_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_4_bits_uop_stq_idx_0 = io_wb_resps_4_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_rxq_idx_0 = io_wb_resps_4_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_4_bits_uop_pdst_0 = io_wb_resps_4_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_4_bits_uop_prs1_0 = io_wb_resps_4_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_4_bits_uop_prs2_0 = io_wb_resps_4_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_4_bits_uop_prs3_0 = io_wb_resps_4_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_uop_ppred_0 = io_wb_resps_4_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_prs1_busy_0 = io_wb_resps_4_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_prs2_busy_0 = io_wb_resps_4_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_prs3_busy_0 = io_wb_resps_4_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_ppred_busy_0 = io_wb_resps_4_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_4_bits_uop_stale_pdst_0 = io_wb_resps_4_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_exception_0 = io_wb_resps_4_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_4_bits_uop_exc_cause_0 = io_wb_resps_4_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_uop_mem_cmd_0 = io_wb_resps_4_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_mem_size_0 = io_wb_resps_4_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_mem_signed_0 = io_wb_resps_4_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_uses_ldq_0 = io_wb_resps_4_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_uses_stq_0 = io_wb_resps_4_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_is_unique_0 = io_wb_resps_4_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_flush_on_commit_0 = io_wb_resps_4_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_csr_cmd_0 = io_wb_resps_4_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_ldst_is_rs1_0 = io_wb_resps_4_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_ldst_0 = io_wb_resps_4_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs1_0 = io_wb_resps_4_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs2_0 = io_wb_resps_4_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_4_bits_uop_lrs3_0 = io_wb_resps_4_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_dst_rtype_0 = io_wb_resps_4_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_lrs1_rtype_0 = io_wb_resps_4_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_lrs2_rtype_0 = io_wb_resps_4_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_frs3_en_0 = io_wb_resps_4_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fcn_dw_0 = io_wb_resps_4_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_uop_fcn_op_0 = io_wb_resps_4_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_fp_val_0 = io_wb_resps_4_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_fp_rm_0 = io_wb_resps_4_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_4_bits_uop_fp_typ_0 = io_wb_resps_4_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_xcpt_pf_if_0 = io_wb_resps_4_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_xcpt_ae_if_0 = io_wb_resps_4_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_xcpt_ma_if_0 = io_wb_resps_4_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_bp_debug_if_0 = io_wb_resps_4_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_uop_bp_xcpt_if_0 = io_wb_resps_4_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_debug_fsrc_0 = io_wb_resps_4_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_4_bits_uop_debug_tsrc_0 = io_wb_resps_4_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_4_bits_data_0 = io_wb_resps_4_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_fflags_valid_0 = io_wb_resps_4_bits_fflags_valid; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_4_bits_fflags_bits_0 = io_wb_resps_4_bits_fflags_bits; // @[rob.scala:199:7]
wire io_wb_resps_5_valid_0 = io_wb_resps_5_valid; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_5_bits_uop_inst_0 = io_wb_resps_5_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_wb_resps_5_bits_uop_debug_inst_0 = io_wb_resps_5_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_rvc_0 = io_wb_resps_5_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_wb_resps_5_bits_uop_debug_pc_0 = io_wb_resps_5_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iq_type_0_0 = io_wb_resps_5_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iq_type_1_0 = io_wb_resps_5_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iq_type_2_0 = io_wb_resps_5_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iq_type_3_0 = io_wb_resps_5_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_0_0 = io_wb_resps_5_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_1_0 = io_wb_resps_5_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_2_0 = io_wb_resps_5_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_3_0 = io_wb_resps_5_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_4_0 = io_wb_resps_5_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_5_0 = io_wb_resps_5_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_6_0 = io_wb_resps_5_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_7_0 = io_wb_resps_5_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_8_0 = io_wb_resps_5_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fu_code_9_0 = io_wb_resps_5_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_issued_0 = io_wb_resps_5_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_issued_partial_agen_0 = io_wb_resps_5_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_issued_partial_dgen_0 = io_wb_resps_5_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_iw_p1_speculative_child_0 = io_wb_resps_5_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_iw_p2_speculative_child_0 = io_wb_resps_5_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_p1_bypass_hint_0 = io_wb_resps_5_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_p2_bypass_hint_0 = io_wb_resps_5_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_iw_p3_bypass_hint_0 = io_wb_resps_5_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_dis_col_sel_0 = io_wb_resps_5_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_wb_resps_5_bits_uop_br_mask_0 = io_wb_resps_5_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_5_bits_uop_br_tag_0 = io_wb_resps_5_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_5_bits_uop_br_type_0 = io_wb_resps_5_bits_uop_br_type; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_sfb_0 = io_wb_resps_5_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_fence_0 = io_wb_resps_5_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_fencei_0 = io_wb_resps_5_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_sfence_0 = io_wb_resps_5_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_amo_0 = io_wb_resps_5_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_eret_0 = io_wb_resps_5_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_sys_pc2epc_0 = io_wb_resps_5_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_rocc_0 = io_wb_resps_5_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_mov_0 = io_wb_resps_5_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_uop_ftq_idx_0 = io_wb_resps_5_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_edge_inst_0 = io_wb_resps_5_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_pc_lob_0 = io_wb_resps_5_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_taken_0 = io_wb_resps_5_bits_uop_taken; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_imm_rename_0 = io_wb_resps_5_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_imm_sel_0 = io_wb_resps_5_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_uop_pimm_0 = io_wb_resps_5_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_wb_resps_5_bits_uop_imm_packed_0 = io_wb_resps_5_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_op1_sel_0 = io_wb_resps_5_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_op2_sel_0 = io_wb_resps_5_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_ldst_0 = io_wb_resps_5_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_wen_0 = io_wb_resps_5_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_ren1_0 = io_wb_resps_5_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_ren2_0 = io_wb_resps_5_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_ren3_0 = io_wb_resps_5_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_swap12_0 = io_wb_resps_5_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_swap23_0 = io_wb_resps_5_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_fp_ctrl_typeTagIn_0 = io_wb_resps_5_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_fp_ctrl_typeTagOut_0 = io_wb_resps_5_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_fromint_0 = io_wb_resps_5_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_toint_0 = io_wb_resps_5_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_fastpipe_0 = io_wb_resps_5_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_fma_0 = io_wb_resps_5_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_div_0 = io_wb_resps_5_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_sqrt_0 = io_wb_resps_5_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_wflags_0 = io_wb_resps_5_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_ctrl_vec_0 = io_wb_resps_5_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_rob_idx_0 = io_wb_resps_5_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_5_bits_uop_ldq_idx_0 = io_wb_resps_5_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_wb_resps_5_bits_uop_stq_idx_0 = io_wb_resps_5_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_rxq_idx_0 = io_wb_resps_5_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_5_bits_uop_pdst_0 = io_wb_resps_5_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_5_bits_uop_prs1_0 = io_wb_resps_5_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_5_bits_uop_prs2_0 = io_wb_resps_5_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_5_bits_uop_prs3_0 = io_wb_resps_5_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_uop_ppred_0 = io_wb_resps_5_bits_uop_ppred; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_prs1_busy_0 = io_wb_resps_5_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_prs2_busy_0 = io_wb_resps_5_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_prs3_busy_0 = io_wb_resps_5_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_ppred_busy_0 = io_wb_resps_5_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_wb_resps_5_bits_uop_stale_pdst_0 = io_wb_resps_5_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_exception_0 = io_wb_resps_5_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_wb_resps_5_bits_uop_exc_cause_0 = io_wb_resps_5_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_uop_mem_cmd_0 = io_wb_resps_5_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_mem_size_0 = io_wb_resps_5_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_mem_signed_0 = io_wb_resps_5_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_uses_ldq_0 = io_wb_resps_5_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_uses_stq_0 = io_wb_resps_5_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_is_unique_0 = io_wb_resps_5_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_flush_on_commit_0 = io_wb_resps_5_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_csr_cmd_0 = io_wb_resps_5_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_ldst_is_rs1_0 = io_wb_resps_5_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_ldst_0 = io_wb_resps_5_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs1_0 = io_wb_resps_5_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs2_0 = io_wb_resps_5_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_wb_resps_5_bits_uop_lrs3_0 = io_wb_resps_5_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_dst_rtype_0 = io_wb_resps_5_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_lrs1_rtype_0 = io_wb_resps_5_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_lrs2_rtype_0 = io_wb_resps_5_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_frs3_en_0 = io_wb_resps_5_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fcn_dw_0 = io_wb_resps_5_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_uop_fcn_op_0 = io_wb_resps_5_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_fp_val_0 = io_wb_resps_5_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_fp_rm_0 = io_wb_resps_5_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_wb_resps_5_bits_uop_fp_typ_0 = io_wb_resps_5_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_xcpt_pf_if_0 = io_wb_resps_5_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_xcpt_ae_if_0 = io_wb_resps_5_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_xcpt_ma_if_0 = io_wb_resps_5_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_bp_debug_if_0 = io_wb_resps_5_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_uop_bp_xcpt_if_0 = io_wb_resps_5_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_debug_fsrc_0 = io_wb_resps_5_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_wb_resps_5_bits_uop_debug_tsrc_0 = io_wb_resps_5_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [64:0] io_wb_resps_5_bits_data_0 = io_wb_resps_5_bits_data; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_predicated_0 = io_wb_resps_5_bits_predicated; // @[rob.scala:199:7]
wire io_wb_resps_5_bits_fflags_valid_0 = io_wb_resps_5_bits_fflags_valid; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_5_bits_fflags_bits_0 = io_wb_resps_5_bits_fflags_bits; // @[rob.scala:199:7]
wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[rob.scala:199:7]
wire [5:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[rob.scala:199:7]
wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[rob.scala:199:7]
wire [5:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[rob.scala:199:7]
wire io_lsu_clr_unsafe_0_valid_0 = io_lsu_clr_unsafe_0_valid; // @[rob.scala:199:7]
wire [5:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[rob.scala:199:7]
wire io_lxcpt_valid_0 = io_lxcpt_valid; // @[rob.scala:199:7]
wire [31:0] io_lxcpt_bits_uop_inst_0 = io_lxcpt_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_lxcpt_bits_uop_debug_inst_0 = io_lxcpt_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_rvc_0 = io_lxcpt_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_lxcpt_bits_uop_debug_pc_0 = io_lxcpt_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iq_type_0_0 = io_lxcpt_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iq_type_1_0 = io_lxcpt_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iq_type_2_0 = io_lxcpt_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iq_type_3_0 = io_lxcpt_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_0_0 = io_lxcpt_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_1_0 = io_lxcpt_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_2_0 = io_lxcpt_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_3_0 = io_lxcpt_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_4_0 = io_lxcpt_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_5_0 = io_lxcpt_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_6_0 = io_lxcpt_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_7_0 = io_lxcpt_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_8_0 = io_lxcpt_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fu_code_9_0 = io_lxcpt_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_issued_0 = io_lxcpt_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_issued_partial_agen_0 = io_lxcpt_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_issued_partial_dgen_0 = io_lxcpt_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_iw_p1_speculative_child_0 = io_lxcpt_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_iw_p2_speculative_child_0 = io_lxcpt_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_p1_bypass_hint_0 = io_lxcpt_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_p2_bypass_hint_0 = io_lxcpt_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_iw_p3_bypass_hint_0 = io_lxcpt_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_dis_col_sel_0 = io_lxcpt_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_lxcpt_bits_uop_br_mask_0 = io_lxcpt_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_lxcpt_bits_uop_br_tag_0 = io_lxcpt_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_lxcpt_bits_uop_br_type_0 = io_lxcpt_bits_uop_br_type; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_sfb_0 = io_lxcpt_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_fence_0 = io_lxcpt_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_fencei_0 = io_lxcpt_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_sfence_0 = io_lxcpt_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_amo_0 = io_lxcpt_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_eret_0 = io_lxcpt_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lxcpt_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_rocc_0 = io_lxcpt_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_mov_0 = io_lxcpt_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_uop_ftq_idx_0 = io_lxcpt_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_edge_inst_0 = io_lxcpt_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_pc_lob_0 = io_lxcpt_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_taken_0 = io_lxcpt_bits_uop_taken; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_imm_rename_0 = io_lxcpt_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_imm_sel_0 = io_lxcpt_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_uop_pimm_0 = io_lxcpt_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_lxcpt_bits_uop_imm_packed_0 = io_lxcpt_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_op1_sel_0 = io_lxcpt_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_op2_sel_0 = io_lxcpt_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_ldst_0 = io_lxcpt_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_wen_0 = io_lxcpt_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_ren1_0 = io_lxcpt_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_ren2_0 = io_lxcpt_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_ren3_0 = io_lxcpt_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_swap12_0 = io_lxcpt_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_swap23_0 = io_lxcpt_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = io_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = io_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_fromint_0 = io_lxcpt_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_toint_0 = io_lxcpt_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = io_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_fma_0 = io_lxcpt_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_div_0 = io_lxcpt_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_sqrt_0 = io_lxcpt_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_wflags_0 = io_lxcpt_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_ctrl_vec_0 = io_lxcpt_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_rob_idx_0 = io_lxcpt_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_lxcpt_bits_uop_ldq_idx_0 = io_lxcpt_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_lxcpt_bits_uop_stq_idx_0 = io_lxcpt_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_rxq_idx_0 = io_lxcpt_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_lxcpt_bits_uop_pdst_0 = io_lxcpt_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_lxcpt_bits_uop_prs1_0 = io_lxcpt_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_lxcpt_bits_uop_prs2_0 = io_lxcpt_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_lxcpt_bits_uop_prs3_0 = io_lxcpt_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_uop_ppred_0 = io_lxcpt_bits_uop_ppred; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_prs1_busy_0 = io_lxcpt_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_prs2_busy_0 = io_lxcpt_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_prs3_busy_0 = io_lxcpt_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_ppred_busy_0 = io_lxcpt_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_lxcpt_bits_uop_stale_pdst_0 = io_lxcpt_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_exception_0 = io_lxcpt_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_lxcpt_bits_uop_exc_cause_0 = io_lxcpt_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_uop_mem_cmd_0 = io_lxcpt_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_mem_size_0 = io_lxcpt_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_mem_signed_0 = io_lxcpt_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_uses_ldq_0 = io_lxcpt_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_uses_stq_0 = io_lxcpt_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_is_unique_0 = io_lxcpt_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_flush_on_commit_0 = io_lxcpt_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_csr_cmd_0 = io_lxcpt_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_ldst_is_rs1_0 = io_lxcpt_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_ldst_0 = io_lxcpt_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_lrs1_0 = io_lxcpt_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_lrs2_0 = io_lxcpt_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_lxcpt_bits_uop_lrs3_0 = io_lxcpt_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_dst_rtype_0 = io_lxcpt_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_lrs1_rtype_0 = io_lxcpt_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_lrs2_rtype_0 = io_lxcpt_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_frs3_en_0 = io_lxcpt_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fcn_dw_0 = io_lxcpt_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_uop_fcn_op_0 = io_lxcpt_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_fp_val_0 = io_lxcpt_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_fp_rm_0 = io_lxcpt_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_lxcpt_bits_uop_fp_typ_0 = io_lxcpt_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_xcpt_pf_if_0 = io_lxcpt_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_xcpt_ae_if_0 = io_lxcpt_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_xcpt_ma_if_0 = io_lxcpt_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_bp_debug_if_0 = io_lxcpt_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_lxcpt_bits_uop_bp_xcpt_if_0 = io_lxcpt_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_debug_fsrc_0 = io_lxcpt_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_lxcpt_bits_uop_debug_tsrc_0 = io_lxcpt_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire [4:0] io_lxcpt_bits_cause_0 = io_lxcpt_bits_cause; // @[rob.scala:199:7]
wire [39:0] io_lxcpt_bits_badvaddr_0 = io_lxcpt_bits_badvaddr; // @[rob.scala:199:7]
wire [31:0] io_csr_replay_bits_uop_inst_0 = io_csr_replay_bits_uop_inst; // @[rob.scala:199:7]
wire [31:0] io_csr_replay_bits_uop_debug_inst_0 = io_csr_replay_bits_uop_debug_inst; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_rvc_0 = io_csr_replay_bits_uop_is_rvc; // @[rob.scala:199:7]
wire [39:0] io_csr_replay_bits_uop_debug_pc_0 = io_csr_replay_bits_uop_debug_pc; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iq_type_0_0 = io_csr_replay_bits_uop_iq_type_0; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iq_type_1_0 = io_csr_replay_bits_uop_iq_type_1; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iq_type_2_0 = io_csr_replay_bits_uop_iq_type_2; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iq_type_3_0 = io_csr_replay_bits_uop_iq_type_3; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_0_0 = io_csr_replay_bits_uop_fu_code_0; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_1_0 = io_csr_replay_bits_uop_fu_code_1; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_2_0 = io_csr_replay_bits_uop_fu_code_2; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_3_0 = io_csr_replay_bits_uop_fu_code_3; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_4_0 = io_csr_replay_bits_uop_fu_code_4; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_5_0 = io_csr_replay_bits_uop_fu_code_5; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_6_0 = io_csr_replay_bits_uop_fu_code_6; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_7_0 = io_csr_replay_bits_uop_fu_code_7; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_8_0 = io_csr_replay_bits_uop_fu_code_8; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fu_code_9_0 = io_csr_replay_bits_uop_fu_code_9; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_issued_0 = io_csr_replay_bits_uop_iw_issued; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_issued_partial_agen_0 = io_csr_replay_bits_uop_iw_issued_partial_agen; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_issued_partial_dgen_0 = io_csr_replay_bits_uop_iw_issued_partial_dgen; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_iw_p1_speculative_child_0 = io_csr_replay_bits_uop_iw_p1_speculative_child; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_iw_p2_speculative_child_0 = io_csr_replay_bits_uop_iw_p2_speculative_child; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_p1_bypass_hint_0 = io_csr_replay_bits_uop_iw_p1_bypass_hint; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_p2_bypass_hint_0 = io_csr_replay_bits_uop_iw_p2_bypass_hint; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_iw_p3_bypass_hint_0 = io_csr_replay_bits_uop_iw_p3_bypass_hint; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_dis_col_sel_0 = io_csr_replay_bits_uop_dis_col_sel; // @[rob.scala:199:7]
wire [11:0] io_csr_replay_bits_uop_br_mask_0 = io_csr_replay_bits_uop_br_mask; // @[rob.scala:199:7]
wire [3:0] io_csr_replay_bits_uop_br_tag_0 = io_csr_replay_bits_uop_br_tag; // @[rob.scala:199:7]
wire [3:0] io_csr_replay_bits_uop_br_type_0 = io_csr_replay_bits_uop_br_type; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_sfb_0 = io_csr_replay_bits_uop_is_sfb; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_fence_0 = io_csr_replay_bits_uop_is_fence; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_fencei_0 = io_csr_replay_bits_uop_is_fencei; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_sfence_0 = io_csr_replay_bits_uop_is_sfence; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_amo_0 = io_csr_replay_bits_uop_is_amo; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_eret_0 = io_csr_replay_bits_uop_is_eret; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_sys_pc2epc_0 = io_csr_replay_bits_uop_is_sys_pc2epc; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_rocc_0 = io_csr_replay_bits_uop_is_rocc; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_mov_0 = io_csr_replay_bits_uop_is_mov; // @[rob.scala:199:7]
wire [4:0] io_csr_replay_bits_uop_ftq_idx_0 = io_csr_replay_bits_uop_ftq_idx; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_edge_inst_0 = io_csr_replay_bits_uop_edge_inst; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_pc_lob_0 = io_csr_replay_bits_uop_pc_lob; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_taken_0 = io_csr_replay_bits_uop_taken; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_imm_rename_0 = io_csr_replay_bits_uop_imm_rename; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_imm_sel_0 = io_csr_replay_bits_uop_imm_sel; // @[rob.scala:199:7]
wire [4:0] io_csr_replay_bits_uop_pimm_0 = io_csr_replay_bits_uop_pimm; // @[rob.scala:199:7]
wire [19:0] io_csr_replay_bits_uop_imm_packed_0 = io_csr_replay_bits_uop_imm_packed; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_op1_sel_0 = io_csr_replay_bits_uop_op1_sel; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_op2_sel_0 = io_csr_replay_bits_uop_op2_sel; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_ldst_0 = io_csr_replay_bits_uop_fp_ctrl_ldst; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_wen_0 = io_csr_replay_bits_uop_fp_ctrl_wen; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_ren1_0 = io_csr_replay_bits_uop_fp_ctrl_ren1; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_ren2_0 = io_csr_replay_bits_uop_fp_ctrl_ren2; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_ren3_0 = io_csr_replay_bits_uop_fp_ctrl_ren3; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_swap12_0 = io_csr_replay_bits_uop_fp_ctrl_swap12; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_swap23_0 = io_csr_replay_bits_uop_fp_ctrl_swap23; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_fp_ctrl_typeTagIn_0 = io_csr_replay_bits_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_fp_ctrl_typeTagOut_0 = io_csr_replay_bits_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_fromint_0 = io_csr_replay_bits_uop_fp_ctrl_fromint; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_toint_0 = io_csr_replay_bits_uop_fp_ctrl_toint; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_fastpipe_0 = io_csr_replay_bits_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_fma_0 = io_csr_replay_bits_uop_fp_ctrl_fma; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_div_0 = io_csr_replay_bits_uop_fp_ctrl_div; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_sqrt_0 = io_csr_replay_bits_uop_fp_ctrl_sqrt; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_wflags_0 = io_csr_replay_bits_uop_fp_ctrl_wflags; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_ctrl_vec_0 = io_csr_replay_bits_uop_fp_ctrl_vec; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_rob_idx_0 = io_csr_replay_bits_uop_rob_idx; // @[rob.scala:199:7]
wire [3:0] io_csr_replay_bits_uop_ldq_idx_0 = io_csr_replay_bits_uop_ldq_idx; // @[rob.scala:199:7]
wire [3:0] io_csr_replay_bits_uop_stq_idx_0 = io_csr_replay_bits_uop_stq_idx; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_rxq_idx_0 = io_csr_replay_bits_uop_rxq_idx; // @[rob.scala:199:7]
wire [6:0] io_csr_replay_bits_uop_pdst_0 = io_csr_replay_bits_uop_pdst; // @[rob.scala:199:7]
wire [6:0] io_csr_replay_bits_uop_prs1_0 = io_csr_replay_bits_uop_prs1; // @[rob.scala:199:7]
wire [6:0] io_csr_replay_bits_uop_prs2_0 = io_csr_replay_bits_uop_prs2; // @[rob.scala:199:7]
wire [6:0] io_csr_replay_bits_uop_prs3_0 = io_csr_replay_bits_uop_prs3; // @[rob.scala:199:7]
wire [4:0] io_csr_replay_bits_uop_ppred_0 = io_csr_replay_bits_uop_ppred; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_prs1_busy_0 = io_csr_replay_bits_uop_prs1_busy; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_prs2_busy_0 = io_csr_replay_bits_uop_prs2_busy; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_prs3_busy_0 = io_csr_replay_bits_uop_prs3_busy; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_ppred_busy_0 = io_csr_replay_bits_uop_ppred_busy; // @[rob.scala:199:7]
wire [6:0] io_csr_replay_bits_uop_stale_pdst_0 = io_csr_replay_bits_uop_stale_pdst; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_exception_0 = io_csr_replay_bits_uop_exception; // @[rob.scala:199:7]
wire [63:0] io_csr_replay_bits_uop_exc_cause_0 = io_csr_replay_bits_uop_exc_cause; // @[rob.scala:199:7]
wire [4:0] io_csr_replay_bits_uop_mem_cmd_0 = io_csr_replay_bits_uop_mem_cmd; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_mem_size_0 = io_csr_replay_bits_uop_mem_size; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_mem_signed_0 = io_csr_replay_bits_uop_mem_signed; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_uses_ldq_0 = io_csr_replay_bits_uop_uses_ldq; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_uses_stq_0 = io_csr_replay_bits_uop_uses_stq; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_is_unique_0 = io_csr_replay_bits_uop_is_unique; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_flush_on_commit_0 = io_csr_replay_bits_uop_flush_on_commit; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_csr_cmd_0 = io_csr_replay_bits_uop_csr_cmd; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_ldst_is_rs1_0 = io_csr_replay_bits_uop_ldst_is_rs1; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_ldst_0 = io_csr_replay_bits_uop_ldst; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_lrs1_0 = io_csr_replay_bits_uop_lrs1; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_lrs2_0 = io_csr_replay_bits_uop_lrs2; // @[rob.scala:199:7]
wire [5:0] io_csr_replay_bits_uop_lrs3_0 = io_csr_replay_bits_uop_lrs3; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_dst_rtype_0 = io_csr_replay_bits_uop_dst_rtype; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_lrs1_rtype_0 = io_csr_replay_bits_uop_lrs1_rtype; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_lrs2_rtype_0 = io_csr_replay_bits_uop_lrs2_rtype; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_frs3_en_0 = io_csr_replay_bits_uop_frs3_en; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fcn_dw_0 = io_csr_replay_bits_uop_fcn_dw; // @[rob.scala:199:7]
wire [4:0] io_csr_replay_bits_uop_fcn_op_0 = io_csr_replay_bits_uop_fcn_op; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_fp_val_0 = io_csr_replay_bits_uop_fp_val; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_fp_rm_0 = io_csr_replay_bits_uop_fp_rm; // @[rob.scala:199:7]
wire [1:0] io_csr_replay_bits_uop_fp_typ_0 = io_csr_replay_bits_uop_fp_typ; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_xcpt_pf_if_0 = io_csr_replay_bits_uop_xcpt_pf_if; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_xcpt_ae_if_0 = io_csr_replay_bits_uop_xcpt_ae_if; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_xcpt_ma_if_0 = io_csr_replay_bits_uop_xcpt_ma_if; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_bp_debug_if_0 = io_csr_replay_bits_uop_bp_debug_if; // @[rob.scala:199:7]
wire io_csr_replay_bits_uop_bp_xcpt_if_0 = io_csr_replay_bits_uop_bp_xcpt_if; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_debug_fsrc_0 = io_csr_replay_bits_uop_debug_fsrc; // @[rob.scala:199:7]
wire [2:0] io_csr_replay_bits_uop_debug_tsrc_0 = io_csr_replay_bits_uop_debug_tsrc; // @[rob.scala:199:7]
wire io_csr_stall_0 = io_csr_stall; // @[rob.scala:199:7]
wire [63:0] io_debug_tsc_0 = io_debug_tsc; // @[rob.scala:199:7]
wire _lxcpt_older_T = 1'h1; // @[rob.scala:667:23]
wire lxcpt_older = 1'h1; // @[rob.scala:667:44]
wire io_wb_resps_2_bits_fflags_valid = 1'h0; // @[rob.scala:199:7]
wire io_wb_resps_3_bits_fflags_valid = 1'h0; // @[rob.scala:199:7]
wire io_wb_resps_4_bits_predicated = 1'h0; // @[rob.scala:199:7]
wire io_csr_replay_valid = 1'h0; // @[rob.scala:199:7]
wire debug_entry_0_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_0_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_1_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_2_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_3_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_4_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_5_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_6_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_7_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_8_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_9_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_10_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_11_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_12_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_13_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_14_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_15_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_16_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_17_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_18_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_19_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_20_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_21_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_22_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_23_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_24_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_25_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_26_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_27_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_28_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_29_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_30_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_31_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_32_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_33_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_34_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_35_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_36_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_37_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_38_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_39_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_40_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_41_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_42_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_43_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_44_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_45_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_46_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_47_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_48_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_49_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_50_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_51_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_52_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_53_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_54_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_55_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_56_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_57_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_58_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_59_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_60_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_61_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_62_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_valid = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_unsafe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_rvc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iq_type_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iq_type_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iq_type_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iq_type_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_0 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_4 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_5 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_6 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_7 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_8 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fu_code_9 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_issued = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_issued_partial_agen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_issued_partial_dgen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_p1_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_p2_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_iw_p3_bypass_hint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_sfb = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_fence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_fencei = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_sfence = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_amo = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_eret = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_sys_pc2epc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_rocc = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_mov = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_edge_inst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_taken = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_imm_rename = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_ldst = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_wen = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_ren1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_ren2 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_ren3 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_swap12 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_swap23 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_fromint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_toint = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_fastpipe = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_fma = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_div = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_sqrt = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_wflags = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_ctrl_vec = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_prs1_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_prs2_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_prs3_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_ppred_busy = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_exception = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_mem_signed = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_uses_ldq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_uses_stq = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_is_unique = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_flush_on_commit = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_ldst_is_rs1 = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_frs3_en = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fcn_dw = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_fp_val = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_xcpt_pf_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_xcpt_ae_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_xcpt_ma_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_bp_debug_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_uop_bp_xcpt_if = 1'h0; // @[rob.scala:272:25]
wire debug_entry_63_exception = 1'h0; // @[rob.scala:272:25]
wire _rob_unsafe_masked_WIRE_0 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_1 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_2 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_3 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_4 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_5 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_6 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_7 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_8 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_9 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_10 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_11 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_12 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_13 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_14 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_15 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_16 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_17 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_18 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_19 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_20 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_21 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_22 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_23 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_24 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_25 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_26 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_27 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_28 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_29 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_30 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_31 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_32 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_33 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_34 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_35 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_36 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_37 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_38 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_39 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_40 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_41 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_42 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_43 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_44 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_45 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_46 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_47 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_48 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_49 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_50 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_51 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_52 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_53 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_54 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_55 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_56 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_57 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_58 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_59 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_60 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_61 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_62 = 1'h0; // @[rob.scala:280:43]
wire _rob_unsafe_masked_WIRE_63 = 1'h0; // @[rob.scala:280:43]
wire _rob_debug_inst_wmask_WIRE_0 = 1'h0; // @[rob.scala:283:46]
wire _rob_debug_inst_wmask_WIRE_1 = 1'h0; // @[rob.scala:283:46]
wire _rob_val_WIRE_0 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_2 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_3 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_4 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_5 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_6 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_7 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_8 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_9 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_10 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_11 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_12 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_13 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_14 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_15 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_16 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_17 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_18 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_19 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_20 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_21 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_22 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_23 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_24 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_25 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_26 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_27 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_28 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_29 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_30 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_31 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_0 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_1 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_2 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_3 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_4 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_5 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_6 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_7 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_8 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_9 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_10 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_11 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_12 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_13 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_14 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_15 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_16 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_17 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_18 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_19 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_20 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_21 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_22 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_23 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_24 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_25 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_26 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_27 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_28 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_29 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_30 = 1'h0; // @[rob.scala:358:40]
wire _rob_val_WIRE_1_31 = 1'h0; // @[rob.scala:358:40]
wire [4:0] io_wb_resps_2_bits_fflags_bits = 5'h0; // @[rob.scala:199:7]
wire [4:0] io_wb_resps_3_bits_fflags_bits = 5'h0; // @[rob.scala:199:7]
wire [4:0] debug_entry_0_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_0_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_0_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_0_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_0_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_1_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_1_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_1_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_1_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_1_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_2_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_2_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_2_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_2_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_2_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_3_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_3_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_3_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_3_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_3_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_4_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_4_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_4_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_4_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_4_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_5_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_5_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_5_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_5_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_5_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_6_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_6_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_6_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_6_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_6_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_7_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_7_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_7_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_7_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_7_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_8_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_8_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_8_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_8_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_8_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_9_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_9_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_9_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_9_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_9_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_10_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_10_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_10_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_10_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_10_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_11_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_11_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_11_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_11_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_11_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_12_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_12_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_12_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_12_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_12_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_13_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_13_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_13_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_13_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_13_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_14_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_14_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_14_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_14_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_14_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_15_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_15_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_15_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_15_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_15_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_16_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_16_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_16_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_16_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_16_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_17_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_17_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_17_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_17_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_17_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_18_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_18_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_18_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_18_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_18_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_19_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_19_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_19_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_19_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_19_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_20_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_20_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_20_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_20_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_20_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_21_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_21_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_21_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_21_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_21_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_22_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_22_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_22_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_22_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_22_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_23_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_23_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_23_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_23_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_23_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_24_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_24_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_24_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_24_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_24_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_25_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_25_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_25_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_25_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_25_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_26_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_26_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_26_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_26_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_26_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_27_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_27_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_27_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_27_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_27_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_28_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_28_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_28_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_28_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_28_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_29_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_29_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_29_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_29_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_29_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_30_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_30_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_30_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_30_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_30_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_31_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_31_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_31_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_31_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_31_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_32_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_32_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_32_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_32_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_32_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_33_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_33_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_33_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_33_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_33_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_34_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_34_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_34_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_34_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_34_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_35_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_35_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_35_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_35_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_35_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_36_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_36_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_36_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_36_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_36_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_37_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_37_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_37_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_37_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_37_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_38_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_38_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_38_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_38_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_38_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_39_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_39_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_39_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_39_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_39_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_40_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_40_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_40_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_40_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_40_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_41_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_41_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_41_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_41_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_41_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_42_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_42_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_42_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_42_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_42_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_43_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_43_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_43_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_43_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_43_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_44_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_44_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_44_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_44_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_44_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_45_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_45_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_45_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_45_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_45_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_46_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_46_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_46_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_46_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_46_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_47_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_47_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_47_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_47_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_47_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_48_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_48_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_48_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_48_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_48_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_49_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_49_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_49_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_49_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_49_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_50_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_50_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_50_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_50_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_50_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_51_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_51_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_51_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_51_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_51_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_52_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_52_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_52_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_52_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_52_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_53_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_53_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_53_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_53_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_53_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_54_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_54_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_54_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_54_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_54_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_55_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_55_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_55_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_55_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_55_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_56_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_56_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_56_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_56_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_56_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_57_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_57_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_57_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_57_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_57_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_58_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_58_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_58_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_58_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_58_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_59_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_59_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_59_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_59_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_59_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_60_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_60_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_60_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_60_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_60_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_61_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_61_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_61_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_61_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_61_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_62_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_62_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_62_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_62_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_62_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_63_uop_ftq_idx = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_63_uop_pimm = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_63_uop_ppred = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_63_uop_mem_cmd = 5'h0; // @[rob.scala:272:25]
wire [4:0] debug_entry_63_uop_fcn_op = 5'h0; // @[rob.scala:272:25]
wire [4:0] io_csr_replay_bits_cause = 5'h11; // @[rob.scala:199:7]
wire [39:0] io_csr_replay_bits_badvaddr = 40'h0; // @[rob.scala:199:7]
wire [39:0] debug_entry_0_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_1_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_2_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_3_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_4_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_5_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_6_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_7_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_8_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_9_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_10_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_11_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_12_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_13_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_14_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_15_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_16_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_17_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_18_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_19_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_20_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_21_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_22_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_23_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_24_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_25_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_26_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_27_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_28_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_29_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_30_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_31_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_32_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_33_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_34_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_35_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_36_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_37_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_38_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_39_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_40_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_41_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_42_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_43_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_44_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_45_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_46_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_47_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_48_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_49_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_50_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_51_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_52_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_53_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_54_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_55_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_56_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_57_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_58_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_59_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_60_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_61_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_62_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [39:0] debug_entry_63_uop_debug_pc = 40'h0; // @[rob.scala:272:25]
wire [31:0] io_commit_debug_insts_0 = 32'h0; // @[rob.scala:199:7]
wire [31:0] io_commit_debug_insts_1 = 32'h0; // @[rob.scala:199:7]
wire [31:0] debug_entry_0_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_0_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_1_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_1_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_2_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_2_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_3_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_3_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_4_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_4_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_5_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_5_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_6_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_6_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_7_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_7_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_8_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_8_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_9_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_9_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_10_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_10_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_11_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_11_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_12_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_12_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_13_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_13_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_14_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_14_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_15_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_15_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_16_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_16_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_17_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_17_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_18_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_18_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_19_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_19_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_20_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_20_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_21_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_21_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_22_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_22_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_23_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_23_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_24_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_24_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_25_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_25_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_26_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_26_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_27_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_27_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_28_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_28_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_29_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_29_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_30_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_30_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_31_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_31_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_32_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_32_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_33_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_33_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_34_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_34_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_35_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_35_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_36_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_36_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_37_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_37_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_38_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_38_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_39_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_39_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_40_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_40_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_41_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_41_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_42_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_42_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_43_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_43_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_44_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_44_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_45_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_45_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_46_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_46_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_47_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_47_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_48_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_48_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_49_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_49_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_50_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_50_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_51_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_51_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_52_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_52_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_53_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_53_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_54_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_54_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_55_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_55_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_56_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_56_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_57_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_57_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_58_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_58_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_59_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_59_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_60_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_60_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_61_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_61_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_62_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_62_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_63_uop_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] debug_entry_63_uop_debug_inst = 32'h0; // @[rob.scala:272:25]
wire [31:0] rob_debug_inst_rdata_0 = 32'h0; // @[rob.scala:282:34]
wire [31:0] rob_debug_inst_rdata_1 = 32'h0; // @[rob.scala:282:34]
wire [2:0] io_com_xcpt_bits_flush_typ = 3'h0; // @[rob.scala:199:7]
wire [2:0] debug_entry_0_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_0_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_0_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_0_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_0_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_0_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_1_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_2_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_3_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_4_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_5_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_6_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_7_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_8_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_9_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_10_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_11_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_12_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_13_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_14_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_15_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_16_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_17_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_18_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_19_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_20_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_21_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_22_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_23_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_24_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_25_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_26_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_27_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_28_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_29_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_30_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_31_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_32_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_33_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_34_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_35_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_36_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_37_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_38_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_39_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_40_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_41_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_42_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_43_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_44_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_45_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_46_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_47_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_48_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_49_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_50_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_51_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_52_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_53_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_54_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_55_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_56_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_57_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_58_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_59_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_60_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_61_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_62_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_imm_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_op2_sel = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_csr_cmd = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_fp_rm = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_debug_fsrc = 3'h0; // @[rob.scala:272:25]
wire [2:0] debug_entry_63_uop_debug_tsrc = 3'h0; // @[rob.scala:272:25]
wire [63:0] io_flush_bits_cause = 64'h0; // @[rob.scala:199:7]
wire [63:0] io_flush_bits_badvaddr = 64'h0; // @[rob.scala:199:7]
wire [63:0] debug_entry_0_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_1_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_2_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_3_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_4_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_5_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_6_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_7_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_8_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_9_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_10_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_11_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_12_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_13_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_14_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_15_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_16_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_17_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_18_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_19_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_20_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_21_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_22_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_23_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_24_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_25_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_26_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_27_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_28_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_29_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_30_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_31_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_32_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_33_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_34_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_35_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_36_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_37_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_38_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_39_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_40_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_41_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_42_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_43_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_44_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_45_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_46_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_47_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_48_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_49_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_50_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_51_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_52_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_53_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_54_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_55_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_56_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_57_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_58_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_59_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_60_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_61_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_62_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [63:0] debug_entry_63_uop_exc_cause = 64'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_0_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_1_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_2_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_3_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_4_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_5_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_6_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_7_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_8_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_9_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_10_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_11_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_12_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_13_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_14_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_15_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_16_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_17_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_18_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_19_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_20_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_21_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_22_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_23_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_24_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_25_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_26_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_27_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_28_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_29_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_30_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_31_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_32_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_33_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_34_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_35_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_36_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_37_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_38_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_39_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_40_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_41_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_42_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_43_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_44_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_45_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_46_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_47_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_48_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_49_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_50_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_51_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_52_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_53_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_54_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_55_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_56_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_57_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_58_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_59_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_60_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_61_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_62_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_iw_p1_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_iw_p2_speculative_child = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_dis_col_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_op1_sel = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_fp_ctrl_typeTagIn = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_fp_ctrl_typeTagOut = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_rxq_idx = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_mem_size = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_dst_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_lrs1_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_lrs2_rtype = 2'h0; // @[rob.scala:272:25]
wire [1:0] debug_entry_63_uop_fp_typ = 2'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_0_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_1_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_2_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_3_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_4_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_5_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_6_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_7_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_8_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_9_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_10_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_11_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_12_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_13_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_14_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_15_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_16_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_17_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_18_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_19_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_20_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_21_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_22_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_23_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_24_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_25_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_26_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_27_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_28_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_29_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_30_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_31_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_32_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_33_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_34_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_35_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_36_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_37_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_38_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_39_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_40_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_41_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_42_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_43_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_44_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_45_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_46_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_47_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_48_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_49_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_50_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_51_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_52_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_53_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_54_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_55_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_56_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_57_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_58_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_59_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_60_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_61_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_62_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_pc_lob = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_rob_idx = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_ldst = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_lrs1 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_lrs2 = 6'h0; // @[rob.scala:272:25]
wire [5:0] debug_entry_63_uop_lrs3 = 6'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_0_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_0_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_0_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_0_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_0_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_1_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_1_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_1_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_1_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_1_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_2_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_2_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_2_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_2_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_2_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_3_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_3_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_3_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_3_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_3_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_4_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_4_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_4_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_4_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_4_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_5_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_5_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_5_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_5_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_5_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_6_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_6_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_6_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_6_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_6_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_7_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_7_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_7_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_7_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_7_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_8_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_8_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_8_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_8_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_8_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_9_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_9_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_9_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_9_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_9_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_10_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_10_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_10_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_10_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_10_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_11_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_11_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_11_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_11_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_11_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_12_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_12_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_12_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_12_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_12_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_13_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_13_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_13_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_13_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_13_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_14_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_14_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_14_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_14_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_14_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_15_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_15_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_15_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_15_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_15_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_16_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_16_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_16_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_16_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_16_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_17_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_17_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_17_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_17_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_17_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_18_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_18_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_18_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_18_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_18_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_19_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_19_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_19_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_19_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_19_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_20_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_20_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_20_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_20_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_20_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_21_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_21_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_21_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_21_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_21_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_22_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_22_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_22_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_22_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_22_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_23_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_23_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_23_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_23_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_23_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_24_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_24_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_24_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_24_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_24_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_25_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_25_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_25_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_25_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_25_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_26_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_26_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_26_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_26_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_26_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_27_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_27_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_27_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_27_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_27_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_28_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_28_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_28_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_28_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_28_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_29_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_29_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_29_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_29_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_29_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_30_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_30_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_30_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_30_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_30_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_31_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_31_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_31_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_31_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_31_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_32_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_32_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_32_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_32_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_32_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_33_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_33_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_33_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_33_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_33_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_34_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_34_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_34_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_34_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_34_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_35_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_35_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_35_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_35_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_35_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_36_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_36_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_36_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_36_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_36_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_37_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_37_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_37_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_37_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_37_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_38_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_38_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_38_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_38_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_38_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_39_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_39_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_39_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_39_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_39_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_40_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_40_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_40_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_40_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_40_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_41_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_41_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_41_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_41_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_41_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_42_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_42_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_42_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_42_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_42_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_43_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_43_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_43_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_43_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_43_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_44_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_44_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_44_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_44_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_44_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_45_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_45_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_45_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_45_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_45_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_46_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_46_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_46_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_46_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_46_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_47_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_47_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_47_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_47_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_47_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_48_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_48_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_48_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_48_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_48_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_49_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_49_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_49_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_49_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_49_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_50_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_50_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_50_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_50_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_50_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_51_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_51_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_51_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_51_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_51_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_52_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_52_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_52_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_52_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_52_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_53_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_53_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_53_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_53_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_53_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_54_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_54_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_54_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_54_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_54_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_55_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_55_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_55_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_55_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_55_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_56_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_56_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_56_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_56_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_56_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_57_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_57_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_57_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_57_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_57_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_58_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_58_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_58_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_58_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_58_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_59_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_59_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_59_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_59_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_59_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_60_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_60_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_60_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_60_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_60_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_61_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_61_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_61_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_61_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_61_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_62_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_62_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_62_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_62_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_62_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_63_uop_pdst = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_63_uop_prs1 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_63_uop_prs2 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_63_uop_prs3 = 7'h0; // @[rob.scala:272:25]
wire [6:0] debug_entry_63_uop_stale_pdst = 7'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_0_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_0_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_0_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_0_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_1_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_1_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_1_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_1_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_2_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_2_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_2_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_2_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_3_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_3_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_3_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_3_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_4_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_4_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_4_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_4_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_5_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_5_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_5_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_5_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_6_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_6_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_6_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_6_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_7_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_7_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_7_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_7_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_8_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_8_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_8_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_8_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_9_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_9_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_9_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_9_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_10_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_10_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_10_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_10_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_11_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_11_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_11_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_11_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_12_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_12_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_12_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_12_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_13_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_13_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_13_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_13_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_14_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_14_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_14_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_14_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_15_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_15_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_15_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_15_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_16_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_16_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_16_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_16_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_17_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_17_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_17_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_17_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_18_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_18_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_18_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_18_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_19_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_19_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_19_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_19_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_20_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_20_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_20_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_20_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_21_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_21_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_21_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_21_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_22_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_22_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_22_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_22_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_23_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_23_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_23_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_23_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_24_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_24_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_24_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_24_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_25_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_25_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_25_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_25_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_26_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_26_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_26_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_26_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_27_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_27_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_27_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_27_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_28_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_28_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_28_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_28_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_29_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_29_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_29_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_29_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_30_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_30_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_30_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_30_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_31_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_31_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_31_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_31_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_32_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_32_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_32_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_32_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_33_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_33_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_33_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_33_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_34_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_34_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_34_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_34_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_35_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_35_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_35_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_35_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_36_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_36_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_36_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_36_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_37_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_37_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_37_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_37_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_38_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_38_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_38_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_38_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_39_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_39_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_39_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_39_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_40_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_40_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_40_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_40_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_41_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_41_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_41_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_41_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_42_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_42_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_42_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_42_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_43_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_43_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_43_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_43_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_44_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_44_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_44_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_44_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_45_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_45_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_45_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_45_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_46_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_46_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_46_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_46_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_47_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_47_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_47_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_47_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_48_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_48_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_48_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_48_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_49_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_49_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_49_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_49_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_50_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_50_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_50_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_50_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_51_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_51_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_51_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_51_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_52_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_52_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_52_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_52_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_53_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_53_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_53_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_53_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_54_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_54_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_54_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_54_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_55_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_55_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_55_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_55_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_56_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_56_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_56_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_56_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_57_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_57_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_57_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_57_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_58_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_58_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_58_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_58_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_59_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_59_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_59_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_59_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_60_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_60_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_60_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_60_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_61_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_61_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_61_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_61_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_62_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_62_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_62_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_62_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_63_uop_br_tag = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_63_uop_br_type = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_63_uop_ldq_idx = 4'h0; // @[rob.scala:272:25]
wire [3:0] debug_entry_63_uop_stq_idx = 4'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_0_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_1_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_2_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_3_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_4_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_5_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_6_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_7_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_8_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_9_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_10_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_11_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_12_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_13_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_14_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_15_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_16_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_17_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_18_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_19_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_20_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_21_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_22_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_23_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_24_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_25_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_26_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_27_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_28_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_29_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_30_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_31_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_32_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_33_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_34_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_35_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_36_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_37_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_38_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_39_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_40_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_41_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_42_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_43_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_44_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_45_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_46_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_47_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_48_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_49_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_50_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_51_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_52_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_53_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_54_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_55_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_56_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_57_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_58_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_59_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_60_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_61_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_62_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [19:0] debug_entry_63_uop_imm_packed = 20'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_0_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_1_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_2_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_3_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_4_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_5_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_6_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_7_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_8_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_9_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_10_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_11_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_12_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_13_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_14_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_15_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_16_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_17_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_18_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_19_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_20_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_21_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_22_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_23_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_24_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_25_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_26_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_27_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_28_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_29_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_30_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_31_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_32_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_33_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_34_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_35_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_36_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_37_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_38_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_39_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_40_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_41_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_42_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_43_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_44_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_45_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_46_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_47_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_48_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_49_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_50_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_51_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_52_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_53_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_54_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_55_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_56_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_57_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_58_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_59_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_60_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_61_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_62_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire [11:0] debug_entry_63_uop_br_mask = 12'h0; // @[rob.scala:272:25]
wire rob_debug_inst_wmask_0 = io_enq_valids_0_0; // @[rob.scala:199:7, :283:38]
wire rob_debug_inst_wmask_1 = io_enq_valids_1_0; // @[rob.scala:199:7, :283:38]
wire [31:0] rob_debug_inst_wdata_0 = io_enq_uops_0_debug_inst_0; // @[rob.scala:199:7, :284:34]
wire rob_compact_uop_wdata_out_is_fencei = io_enq_uops_0_is_fencei_0; // @[rob.scala:199:7, :325:19]
wire [4:0] rob_compact_uop_wdata_out_ftq_idx = io_enq_uops_0_ftq_idx_0; // @[rob.scala:199:7, :325:19]
wire [6:0] rob_compact_uop_wdata_out_pdst = io_enq_uops_0_pdst_0; // @[rob.scala:199:7, :325:19]
wire [6:0] rob_compact_uop_wdata_out_stale_pdst = io_enq_uops_0_stale_pdst_0; // @[rob.scala:199:7, :325:19]
wire rob_compact_uop_wdata_out_uses_ldq = io_enq_uops_0_uses_ldq_0; // @[rob.scala:199:7, :325:19]
wire rob_compact_uop_wdata_out_uses_stq = io_enq_uops_0_uses_stq_0; // @[rob.scala:199:7, :325:19]
wire [5:0] rob_compact_uop_wdata_out_ldst = io_enq_uops_0_ldst_0; // @[rob.scala:199:7, :325:19]
wire [1:0] rob_compact_uop_wdata_out_dst_rtype = io_enq_uops_0_dst_rtype_0; // @[rob.scala:199:7, :325:19]
wire [31:0] rob_debug_inst_wdata_1 = io_enq_uops_1_debug_inst_0; // @[rob.scala:199:7, :284:34]
wire rob_compact_uop_wdata_out_1_is_fencei = io_enq_uops_1_is_fencei_0; // @[rob.scala:199:7, :325:19]
wire [4:0] rob_compact_uop_wdata_out_1_ftq_idx = io_enq_uops_1_ftq_idx_0; // @[rob.scala:199:7, :325:19]
wire [6:0] rob_compact_uop_wdata_out_1_pdst = io_enq_uops_1_pdst_0; // @[rob.scala:199:7, :325:19]
wire [6:0] rob_compact_uop_wdata_out_1_stale_pdst = io_enq_uops_1_stale_pdst_0; // @[rob.scala:199:7, :325:19]
wire rob_compact_uop_wdata_out_1_uses_ldq = io_enq_uops_1_uses_ldq_0; // @[rob.scala:199:7, :325:19]
wire rob_compact_uop_wdata_out_1_uses_stq = io_enq_uops_1_uses_stq_0; // @[rob.scala:199:7, :325:19]
wire [5:0] rob_compact_uop_wdata_out_1_ldst = io_enq_uops_1_ldst_0; // @[rob.scala:199:7, :325:19]
wire [1:0] rob_compact_uop_wdata_out_1_dst_rtype = io_enq_uops_1_dst_rtype_0; // @[rob.scala:199:7, :325:19]
wire [5:0] rob_tail_idx; // @[rob.scala:216:59]
wire [5:0] rob_pnr_idx; // @[rob.scala:220:59]
wire [5:0] rob_head_idx; // @[rob.scala:212:59]
wire new_xcpt_valid = io_lxcpt_valid_0; // @[rob.scala:199:7, :665:41]
wire [31:0] new_xcpt_uop_inst = io_lxcpt_bits_uop_inst_0; // @[rob.scala:199:7, :668:23]
wire [31:0] new_xcpt_uop_debug_inst = io_lxcpt_bits_uop_debug_inst_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_rvc = io_lxcpt_bits_uop_is_rvc_0; // @[rob.scala:199:7, :668:23]
wire [39:0] new_xcpt_uop_debug_pc = io_lxcpt_bits_uop_debug_pc_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iq_type_0 = io_lxcpt_bits_uop_iq_type_0_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iq_type_1 = io_lxcpt_bits_uop_iq_type_1_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iq_type_2 = io_lxcpt_bits_uop_iq_type_2_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iq_type_3 = io_lxcpt_bits_uop_iq_type_3_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_0 = io_lxcpt_bits_uop_fu_code_0_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_1 = io_lxcpt_bits_uop_fu_code_1_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_2 = io_lxcpt_bits_uop_fu_code_2_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_3 = io_lxcpt_bits_uop_fu_code_3_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_4 = io_lxcpt_bits_uop_fu_code_4_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_5 = io_lxcpt_bits_uop_fu_code_5_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_6 = io_lxcpt_bits_uop_fu_code_6_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_7 = io_lxcpt_bits_uop_fu_code_7_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_8 = io_lxcpt_bits_uop_fu_code_8_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fu_code_9 = io_lxcpt_bits_uop_fu_code_9_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_issued = io_lxcpt_bits_uop_iw_issued_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_issued_partial_agen = io_lxcpt_bits_uop_iw_issued_partial_agen_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_issued_partial_dgen = io_lxcpt_bits_uop_iw_issued_partial_dgen_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_iw_p1_speculative_child = io_lxcpt_bits_uop_iw_p1_speculative_child_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_iw_p2_speculative_child = io_lxcpt_bits_uop_iw_p2_speculative_child_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_p1_bypass_hint = io_lxcpt_bits_uop_iw_p1_bypass_hint_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_p2_bypass_hint = io_lxcpt_bits_uop_iw_p2_bypass_hint_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_iw_p3_bypass_hint = io_lxcpt_bits_uop_iw_p3_bypass_hint_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_dis_col_sel = io_lxcpt_bits_uop_dis_col_sel_0; // @[rob.scala:199:7, :668:23]
wire [11:0] new_xcpt_uop_br_mask = io_lxcpt_bits_uop_br_mask_0; // @[rob.scala:199:7, :668:23]
wire [3:0] new_xcpt_uop_br_tag = io_lxcpt_bits_uop_br_tag_0; // @[rob.scala:199:7, :668:23]
wire [3:0] new_xcpt_uop_br_type = io_lxcpt_bits_uop_br_type_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_sfb = io_lxcpt_bits_uop_is_sfb_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_fence = io_lxcpt_bits_uop_is_fence_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_fencei = io_lxcpt_bits_uop_is_fencei_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_sfence = io_lxcpt_bits_uop_is_sfence_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_amo = io_lxcpt_bits_uop_is_amo_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_eret = io_lxcpt_bits_uop_is_eret_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_sys_pc2epc = io_lxcpt_bits_uop_is_sys_pc2epc_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_rocc = io_lxcpt_bits_uop_is_rocc_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_mov = io_lxcpt_bits_uop_is_mov_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_uop_ftq_idx = io_lxcpt_bits_uop_ftq_idx_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_edge_inst = io_lxcpt_bits_uop_edge_inst_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_pc_lob = io_lxcpt_bits_uop_pc_lob_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_taken = io_lxcpt_bits_uop_taken_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_imm_rename = io_lxcpt_bits_uop_imm_rename_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_imm_sel = io_lxcpt_bits_uop_imm_sel_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_uop_pimm = io_lxcpt_bits_uop_pimm_0; // @[rob.scala:199:7, :668:23]
wire [19:0] new_xcpt_uop_imm_packed = io_lxcpt_bits_uop_imm_packed_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_op1_sel = io_lxcpt_bits_uop_op1_sel_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_op2_sel = io_lxcpt_bits_uop_op2_sel_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_ldst = io_lxcpt_bits_uop_fp_ctrl_ldst_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_wen = io_lxcpt_bits_uop_fp_ctrl_wen_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_ren1 = io_lxcpt_bits_uop_fp_ctrl_ren1_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_ren2 = io_lxcpt_bits_uop_fp_ctrl_ren2_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_ren3 = io_lxcpt_bits_uop_fp_ctrl_ren3_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_swap12 = io_lxcpt_bits_uop_fp_ctrl_swap12_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_swap23 = io_lxcpt_bits_uop_fp_ctrl_swap23_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_fp_ctrl_typeTagIn = io_lxcpt_bits_uop_fp_ctrl_typeTagIn_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_fp_ctrl_typeTagOut = io_lxcpt_bits_uop_fp_ctrl_typeTagOut_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_fromint = io_lxcpt_bits_uop_fp_ctrl_fromint_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_toint = io_lxcpt_bits_uop_fp_ctrl_toint_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_fastpipe = io_lxcpt_bits_uop_fp_ctrl_fastpipe_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_fma = io_lxcpt_bits_uop_fp_ctrl_fma_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_div = io_lxcpt_bits_uop_fp_ctrl_div_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_sqrt = io_lxcpt_bits_uop_fp_ctrl_sqrt_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_wflags = io_lxcpt_bits_uop_fp_ctrl_wflags_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_ctrl_vec = io_lxcpt_bits_uop_fp_ctrl_vec_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_rob_idx = io_lxcpt_bits_uop_rob_idx_0; // @[rob.scala:199:7, :668:23]
wire [3:0] new_xcpt_uop_ldq_idx = io_lxcpt_bits_uop_ldq_idx_0; // @[rob.scala:199:7, :668:23]
wire [3:0] new_xcpt_uop_stq_idx = io_lxcpt_bits_uop_stq_idx_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_rxq_idx = io_lxcpt_bits_uop_rxq_idx_0; // @[rob.scala:199:7, :668:23]
wire [6:0] new_xcpt_uop_pdst = io_lxcpt_bits_uop_pdst_0; // @[rob.scala:199:7, :668:23]
wire [6:0] new_xcpt_uop_prs1 = io_lxcpt_bits_uop_prs1_0; // @[rob.scala:199:7, :668:23]
wire [6:0] new_xcpt_uop_prs2 = io_lxcpt_bits_uop_prs2_0; // @[rob.scala:199:7, :668:23]
wire [6:0] new_xcpt_uop_prs3 = io_lxcpt_bits_uop_prs3_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_uop_ppred = io_lxcpt_bits_uop_ppred_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_prs1_busy = io_lxcpt_bits_uop_prs1_busy_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_prs2_busy = io_lxcpt_bits_uop_prs2_busy_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_prs3_busy = io_lxcpt_bits_uop_prs3_busy_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_ppred_busy = io_lxcpt_bits_uop_ppred_busy_0; // @[rob.scala:199:7, :668:23]
wire [6:0] new_xcpt_uop_stale_pdst = io_lxcpt_bits_uop_stale_pdst_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_exception = io_lxcpt_bits_uop_exception_0; // @[rob.scala:199:7, :668:23]
wire [63:0] new_xcpt_uop_exc_cause = io_lxcpt_bits_uop_exc_cause_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_uop_mem_cmd = io_lxcpt_bits_uop_mem_cmd_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_mem_size = io_lxcpt_bits_uop_mem_size_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_mem_signed = io_lxcpt_bits_uop_mem_signed_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_uses_ldq = io_lxcpt_bits_uop_uses_ldq_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_uses_stq = io_lxcpt_bits_uop_uses_stq_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_is_unique = io_lxcpt_bits_uop_is_unique_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_flush_on_commit = io_lxcpt_bits_uop_flush_on_commit_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_csr_cmd = io_lxcpt_bits_uop_csr_cmd_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_ldst_is_rs1 = io_lxcpt_bits_uop_ldst_is_rs1_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_ldst = io_lxcpt_bits_uop_ldst_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_lrs1 = io_lxcpt_bits_uop_lrs1_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_lrs2 = io_lxcpt_bits_uop_lrs2_0; // @[rob.scala:199:7, :668:23]
wire [5:0] new_xcpt_uop_lrs3 = io_lxcpt_bits_uop_lrs3_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_dst_rtype = io_lxcpt_bits_uop_dst_rtype_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_lrs1_rtype = io_lxcpt_bits_uop_lrs1_rtype_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_lrs2_rtype = io_lxcpt_bits_uop_lrs2_rtype_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_frs3_en = io_lxcpt_bits_uop_frs3_en_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fcn_dw = io_lxcpt_bits_uop_fcn_dw_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_uop_fcn_op = io_lxcpt_bits_uop_fcn_op_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_fp_val = io_lxcpt_bits_uop_fp_val_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_fp_rm = io_lxcpt_bits_uop_fp_rm_0; // @[rob.scala:199:7, :668:23]
wire [1:0] new_xcpt_uop_fp_typ = io_lxcpt_bits_uop_fp_typ_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_xcpt_pf_if = io_lxcpt_bits_uop_xcpt_pf_if_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_xcpt_ae_if = io_lxcpt_bits_uop_xcpt_ae_if_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_xcpt_ma_if = io_lxcpt_bits_uop_xcpt_ma_if_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_bp_debug_if = io_lxcpt_bits_uop_bp_debug_if_0; // @[rob.scala:199:7, :668:23]
wire new_xcpt_uop_bp_xcpt_if = io_lxcpt_bits_uop_bp_xcpt_if_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_debug_fsrc = io_lxcpt_bits_uop_debug_fsrc_0; // @[rob.scala:199:7, :668:23]
wire [2:0] new_xcpt_uop_debug_tsrc = io_lxcpt_bits_uop_debug_tsrc_0; // @[rob.scala:199:7, :668:23]
wire [4:0] new_xcpt_cause = io_lxcpt_bits_cause_0; // @[rob.scala:199:7, :668:23]
wire [39:0] new_xcpt_badvaddr = io_lxcpt_bits_badvaddr_0; // @[rob.scala:199:7, :668:23]
wire will_commit_0; // @[rob.scala:229:33]
wire will_commit_1; // @[rob.scala:229:33]
wire _io_commit_arch_valids_0_T_1; // @[rob.scala:457:48]
wire _io_commit_arch_valids_1_T_1; // @[rob.scala:457:48]
wire [31:0] io_commit_uops_0_out_inst; // @[rob.scala:313:23]
wire [31:0] io_commit_uops_0_out_debug_inst; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_rvc; // @[rob.scala:313:23]
wire [39:0] io_commit_uops_0_out_debug_pc; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iq_type_0; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iq_type_1; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iq_type_2; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iq_type_3; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_0; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_1; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_2; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_3; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_4; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_5; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_6; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_7; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_8; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fu_code_9; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_issued; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_issued_partial_agen; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_issued_partial_dgen; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_iw_p1_speculative_child; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_iw_p2_speculative_child; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_p1_bypass_hint; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_p2_bypass_hint; // @[rob.scala:313:23]
wire io_commit_uops_0_out_iw_p3_bypass_hint; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_dis_col_sel; // @[rob.scala:313:23]
wire [11:0] io_commit_uops_0_out_br_mask; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_0_out_br_tag; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_0_out_br_type; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_sfb; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_fence; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_fencei; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_sfence; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_amo; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_eret; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_sys_pc2epc; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_rocc; // @[rob.scala:313:23]
wire io_commit_uops_0_out_is_mov; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_0_out_ftq_idx; // @[rob.scala:313:23]
wire io_commit_uops_0_out_edge_inst; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_pc_lob; // @[rob.scala:313:23]
wire io_commit_uops_0_out_imm_rename; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_imm_sel; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_0_out_pimm; // @[rob.scala:313:23]
wire [19:0] io_commit_uops_0_out_imm_packed; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_op1_sel; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_op2_sel; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_ldst; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_wen; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_ren1; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_ren2; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_ren3; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_swap12; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_swap23; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_fp_ctrl_typeTagIn; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_fp_ctrl_typeTagOut; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_fromint; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_toint; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_fastpipe; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_fma; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_div; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_sqrt; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_wflags; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_ctrl_vec; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_rob_idx; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_0_out_ldq_idx; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_0_out_stq_idx; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_rxq_idx; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_0_out_pdst; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_0_out_prs1; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_0_out_prs2; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_0_out_prs3; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_0_out_ppred; // @[rob.scala:313:23]
wire io_commit_uops_0_out_prs1_busy; // @[rob.scala:313:23]
wire io_commit_uops_0_out_prs2_busy; // @[rob.scala:313:23]
wire io_commit_uops_0_out_prs3_busy; // @[rob.scala:313:23]
wire io_commit_uops_0_out_ppred_busy; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_0_out_stale_pdst; // @[rob.scala:313:23]
wire io_commit_uops_0_out_exception; // @[rob.scala:313:23]
wire [63:0] io_commit_uops_0_out_exc_cause; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_0_out_mem_cmd; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_mem_size; // @[rob.scala:313:23]
wire io_commit_uops_0_out_mem_signed; // @[rob.scala:313:23]
wire io_commit_uops_0_out_uses_ldq; // @[rob.scala:313:23]
wire rob_head_uses_ldq_0 = io_commit_uops_0_uses_ldq_0; // @[rob.scala:199:7, :237:33]
wire io_commit_uops_0_out_uses_stq; // @[rob.scala:313:23]
wire rob_head_uses_stq_0 = io_commit_uops_0_uses_stq_0; // @[rob.scala:199:7, :236:33]
wire io_commit_uops_0_out_is_unique; // @[rob.scala:313:23]
wire io_commit_uops_0_out_flush_on_commit; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_csr_cmd; // @[rob.scala:313:23]
wire io_commit_uops_0_out_ldst_is_rs1; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_ldst; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_lrs1; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_lrs2; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_0_out_lrs3; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_dst_rtype; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_lrs1_rtype; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_lrs2_rtype; // @[rob.scala:313:23]
wire io_commit_uops_0_out_frs3_en; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fcn_dw; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_0_out_fcn_op; // @[rob.scala:313:23]
wire io_commit_uops_0_out_fp_val; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_fp_rm; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_0_out_fp_typ; // @[rob.scala:313:23]
wire io_commit_uops_0_out_xcpt_pf_if; // @[rob.scala:313:23]
wire io_commit_uops_0_out_xcpt_ae_if; // @[rob.scala:313:23]
wire io_commit_uops_0_out_xcpt_ma_if; // @[rob.scala:313:23]
wire io_commit_uops_0_out_bp_debug_if; // @[rob.scala:313:23]
wire io_commit_uops_0_out_bp_xcpt_if; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_debug_tsrc; // @[rob.scala:313:23]
wire [31:0] io_commit_uops_1_out_inst; // @[rob.scala:313:23]
wire [31:0] io_commit_uops_1_out_debug_inst; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_rvc; // @[rob.scala:313:23]
wire [39:0] io_commit_uops_1_out_debug_pc; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iq_type_0; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iq_type_1; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iq_type_2; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iq_type_3; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_0; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_1; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_2; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_3; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_4; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_5; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_6; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_7; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_8; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fu_code_9; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_issued; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_issued_partial_agen; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_issued_partial_dgen; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_iw_p1_speculative_child; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_iw_p2_speculative_child; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_p1_bypass_hint; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_p2_bypass_hint; // @[rob.scala:313:23]
wire io_commit_uops_1_out_iw_p3_bypass_hint; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_dis_col_sel; // @[rob.scala:313:23]
wire [11:0] io_commit_uops_1_out_br_mask; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_1_out_br_tag; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_1_out_br_type; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_sfb; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_fence; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_fencei; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_sfence; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_amo; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_eret; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_sys_pc2epc; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_rocc; // @[rob.scala:313:23]
wire io_commit_uops_1_out_is_mov; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_1_out_ftq_idx; // @[rob.scala:313:23]
wire io_commit_uops_1_out_edge_inst; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_pc_lob; // @[rob.scala:313:23]
wire io_commit_uops_1_out_imm_rename; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_imm_sel; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_1_out_pimm; // @[rob.scala:313:23]
wire [19:0] io_commit_uops_1_out_imm_packed; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_op1_sel; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_op2_sel; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_ldst; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_wen; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_ren1; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_ren2; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_ren3; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_swap12; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_swap23; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_fp_ctrl_typeTagIn; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_fp_ctrl_typeTagOut; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_fromint; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_toint; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_fastpipe; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_fma; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_div; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_sqrt; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_wflags; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_ctrl_vec; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_rob_idx; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_1_out_ldq_idx; // @[rob.scala:313:23]
wire [3:0] io_commit_uops_1_out_stq_idx; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_rxq_idx; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_1_out_pdst; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_1_out_prs1; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_1_out_prs2; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_1_out_prs3; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_1_out_ppred; // @[rob.scala:313:23]
wire io_commit_uops_1_out_prs1_busy; // @[rob.scala:313:23]
wire io_commit_uops_1_out_prs2_busy; // @[rob.scala:313:23]
wire io_commit_uops_1_out_prs3_busy; // @[rob.scala:313:23]
wire io_commit_uops_1_out_ppred_busy; // @[rob.scala:313:23]
wire [6:0] io_commit_uops_1_out_stale_pdst; // @[rob.scala:313:23]
wire io_commit_uops_1_out_exception; // @[rob.scala:313:23]
wire [63:0] io_commit_uops_1_out_exc_cause; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_1_out_mem_cmd; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_mem_size; // @[rob.scala:313:23]
wire io_commit_uops_1_out_mem_signed; // @[rob.scala:313:23]
wire io_commit_uops_1_out_uses_ldq; // @[rob.scala:313:23]
wire rob_head_uses_ldq_1 = io_commit_uops_1_uses_ldq_0; // @[rob.scala:199:7, :237:33]
wire io_commit_uops_1_out_uses_stq; // @[rob.scala:313:23]
wire rob_head_uses_stq_1 = io_commit_uops_1_uses_stq_0; // @[rob.scala:199:7, :236:33]
wire io_commit_uops_1_out_is_unique; // @[rob.scala:313:23]
wire io_commit_uops_1_out_flush_on_commit; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_csr_cmd; // @[rob.scala:313:23]
wire io_commit_uops_1_out_ldst_is_rs1; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_ldst; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_lrs1; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_lrs2; // @[rob.scala:313:23]
wire [5:0] io_commit_uops_1_out_lrs3; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_dst_rtype; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_lrs1_rtype; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_lrs2_rtype; // @[rob.scala:313:23]
wire io_commit_uops_1_out_frs3_en; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fcn_dw; // @[rob.scala:313:23]
wire [4:0] io_commit_uops_1_out_fcn_op; // @[rob.scala:313:23]
wire io_commit_uops_1_out_fp_val; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_fp_rm; // @[rob.scala:313:23]
wire [1:0] io_commit_uops_1_out_fp_typ; // @[rob.scala:313:23]
wire io_commit_uops_1_out_xcpt_pf_if; // @[rob.scala:313:23]
wire io_commit_uops_1_out_xcpt_ae_if; // @[rob.scala:313:23]
wire io_commit_uops_1_out_xcpt_ma_if; // @[rob.scala:313:23]
wire io_commit_uops_1_out_bp_debug_if; // @[rob.scala:313:23]
wire io_commit_uops_1_out_bp_xcpt_if; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_debug_tsrc; // @[rob.scala:313:23]
wire _io_commit_fflags_valid_T; // @[rob.scala:650:48]
wire [4:0] _io_commit_fflags_bits_T; // @[rob.scala:651:44]
wire _io_rollback_T; // @[rob.scala:621:28]
wire _io_com_xcpt_valid_T_1; // @[rob.scala:584:41]
wire [4:0] com_xcpt_uop_ftq_idx; // @[Mux.scala:50:70]
wire com_xcpt_uop_edge_inst; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_rvc; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_pc_lob; // @[Mux.scala:50:70]
wire [63:0] _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:269:20]
wire flush_val; // @[rob.scala:601:36]
wire [4:0] flush_uop_ftq_idx; // @[rob.scala:606:22]
wire flush_uop_edge_inst; // @[rob.scala:606:22]
wire flush_uop_is_rvc; // @[rob.scala:606:22]
wire [5:0] flush_uop_pc_lob; // @[rob.scala:606:22]
wire [2:0] io_flush_bits_flush_typ_ret; // @[rob.scala:160:10]
wire empty; // @[rob.scala:227:26]
wire _io_ready_T_4; // @[rob.scala:799:56]
wire io_commit_valids_0_0; // @[rob.scala:199:7]
wire io_commit_valids_1_0; // @[rob.scala:199:7]
wire io_commit_arch_valids_0_0; // @[rob.scala:199:7]
wire io_commit_arch_valids_1_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iq_type_0_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iq_type_1_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iq_type_2_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iq_type_3_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_0_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_1_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_2_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_3_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_4_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_5_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_6_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_7_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_8_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fu_code_9_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_ldst_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_wen_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_ren1_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_ren2_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_ren3_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_swap12_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_swap23_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_fp_ctrl_typeTagIn_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_fp_ctrl_typeTagOut_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_fromint_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_toint_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_fastpipe_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_fma_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_div_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_sqrt_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_wflags_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_ctrl_vec_0; // @[rob.scala:199:7]
wire [31:0] io_commit_uops_0_inst_0; // @[rob.scala:199:7]
wire [31:0] io_commit_uops_0_debug_inst_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_rvc_0; // @[rob.scala:199:7]
wire [39:0] io_commit_uops_0_debug_pc_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_issued_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_issued_partial_agen_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_issued_partial_dgen_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_iw_p1_speculative_child_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_iw_p2_speculative_child_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_p1_bypass_hint_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_p2_bypass_hint_0; // @[rob.scala:199:7]
wire io_commit_uops_0_iw_p3_bypass_hint_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_dis_col_sel_0; // @[rob.scala:199:7]
wire [11:0] io_commit_uops_0_br_mask_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_0_br_tag_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_0_br_type_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_sfb_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_fence_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_fencei_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_sfence_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_amo_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_eret_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_sys_pc2epc_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_rocc_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_mov_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_0_ftq_idx_0; // @[rob.scala:199:7]
wire io_commit_uops_0_edge_inst_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_pc_lob_0; // @[rob.scala:199:7]
wire io_commit_uops_0_taken_0; // @[rob.scala:199:7]
wire io_commit_uops_0_imm_rename_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_imm_sel_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_0_pimm_0; // @[rob.scala:199:7]
wire [19:0] io_commit_uops_0_imm_packed_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_op1_sel_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_op2_sel_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_rob_idx_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_0_ldq_idx_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_0_stq_idx_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_rxq_idx_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_0_pdst_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_0_prs1_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_0_prs2_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_0_prs3_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_0_ppred_0; // @[rob.scala:199:7]
wire io_commit_uops_0_prs1_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_0_prs2_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_0_prs3_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_0_ppred_busy_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_0_stale_pdst_0; // @[rob.scala:199:7]
wire io_commit_uops_0_exception_0; // @[rob.scala:199:7]
wire [63:0] io_commit_uops_0_exc_cause_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_0_mem_cmd_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_mem_size_0; // @[rob.scala:199:7]
wire io_commit_uops_0_mem_signed_0; // @[rob.scala:199:7]
wire io_commit_uops_0_is_unique_0; // @[rob.scala:199:7]
wire io_commit_uops_0_flush_on_commit_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_csr_cmd_0; // @[rob.scala:199:7]
wire io_commit_uops_0_ldst_is_rs1_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_ldst_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_lrs1_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_lrs2_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_0_lrs3_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_dst_rtype_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_lrs1_rtype_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_lrs2_rtype_0; // @[rob.scala:199:7]
wire io_commit_uops_0_frs3_en_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fcn_dw_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_0_fcn_op_0; // @[rob.scala:199:7]
wire io_commit_uops_0_fp_val_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_fp_rm_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_0_fp_typ_0; // @[rob.scala:199:7]
wire io_commit_uops_0_xcpt_pf_if_0; // @[rob.scala:199:7]
wire io_commit_uops_0_xcpt_ae_if_0; // @[rob.scala:199:7]
wire io_commit_uops_0_xcpt_ma_if_0; // @[rob.scala:199:7]
wire io_commit_uops_0_bp_debug_if_0; // @[rob.scala:199:7]
wire io_commit_uops_0_bp_xcpt_if_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_debug_fsrc_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_0_debug_tsrc_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iq_type_0_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iq_type_1_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iq_type_2_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iq_type_3_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_0_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_1_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_2_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_3_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_4_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_5_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_6_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_7_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_8_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fu_code_9_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_ldst_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_wen_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_ren1_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_ren2_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_ren3_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_swap12_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_swap23_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_fp_ctrl_typeTagIn_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_fp_ctrl_typeTagOut_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_fromint_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_toint_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_fastpipe_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_fma_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_div_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_sqrt_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_wflags_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_ctrl_vec_0; // @[rob.scala:199:7]
wire [31:0] io_commit_uops_1_inst_0; // @[rob.scala:199:7]
wire [31:0] io_commit_uops_1_debug_inst_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_rvc_0; // @[rob.scala:199:7]
wire [39:0] io_commit_uops_1_debug_pc_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_issued_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_issued_partial_agen_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_issued_partial_dgen_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_iw_p1_speculative_child_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_iw_p2_speculative_child_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_p1_bypass_hint_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_p2_bypass_hint_0; // @[rob.scala:199:7]
wire io_commit_uops_1_iw_p3_bypass_hint_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_dis_col_sel_0; // @[rob.scala:199:7]
wire [11:0] io_commit_uops_1_br_mask_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_1_br_tag_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_1_br_type_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_sfb_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_fence_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_fencei_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_sfence_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_amo_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_eret_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_sys_pc2epc_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_rocc_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_mov_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_1_ftq_idx_0; // @[rob.scala:199:7]
wire io_commit_uops_1_edge_inst_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_pc_lob_0; // @[rob.scala:199:7]
wire io_commit_uops_1_taken_0; // @[rob.scala:199:7]
wire io_commit_uops_1_imm_rename_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_imm_sel_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_1_pimm_0; // @[rob.scala:199:7]
wire [19:0] io_commit_uops_1_imm_packed_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_op1_sel_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_op2_sel_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_rob_idx_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_1_ldq_idx_0; // @[rob.scala:199:7]
wire [3:0] io_commit_uops_1_stq_idx_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_rxq_idx_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_1_pdst_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_1_prs1_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_1_prs2_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_1_prs3_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_1_ppred_0; // @[rob.scala:199:7]
wire io_commit_uops_1_prs1_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_1_prs2_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_1_prs3_busy_0; // @[rob.scala:199:7]
wire io_commit_uops_1_ppred_busy_0; // @[rob.scala:199:7]
wire [6:0] io_commit_uops_1_stale_pdst_0; // @[rob.scala:199:7]
wire io_commit_uops_1_exception_0; // @[rob.scala:199:7]
wire [63:0] io_commit_uops_1_exc_cause_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_1_mem_cmd_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_mem_size_0; // @[rob.scala:199:7]
wire io_commit_uops_1_mem_signed_0; // @[rob.scala:199:7]
wire io_commit_uops_1_is_unique_0; // @[rob.scala:199:7]
wire io_commit_uops_1_flush_on_commit_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_csr_cmd_0; // @[rob.scala:199:7]
wire io_commit_uops_1_ldst_is_rs1_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_ldst_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_lrs1_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_lrs2_0; // @[rob.scala:199:7]
wire [5:0] io_commit_uops_1_lrs3_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_dst_rtype_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_lrs1_rtype_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_lrs2_rtype_0; // @[rob.scala:199:7]
wire io_commit_uops_1_frs3_en_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fcn_dw_0; // @[rob.scala:199:7]
wire [4:0] io_commit_uops_1_fcn_op_0; // @[rob.scala:199:7]
wire io_commit_uops_1_fp_val_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_fp_rm_0; // @[rob.scala:199:7]
wire [1:0] io_commit_uops_1_fp_typ_0; // @[rob.scala:199:7]
wire io_commit_uops_1_xcpt_pf_if_0; // @[rob.scala:199:7]
wire io_commit_uops_1_xcpt_ae_if_0; // @[rob.scala:199:7]
wire io_commit_uops_1_xcpt_ma_if_0; // @[rob.scala:199:7]
wire io_commit_uops_1_bp_debug_if_0; // @[rob.scala:199:7]
wire io_commit_uops_1_bp_xcpt_if_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_debug_fsrc_0; // @[rob.scala:199:7]
wire [2:0] io_commit_uops_1_debug_tsrc_0; // @[rob.scala:199:7]
wire io_commit_fflags_valid_0; // @[rob.scala:199:7]
wire [4:0] io_commit_fflags_bits_0; // @[rob.scala:199:7]
wire [63:0] io_commit_debug_wdata_0_0; // @[rob.scala:199:7]
wire [63:0] io_commit_debug_wdata_1_0; // @[rob.scala:199:7]
wire [4:0] io_com_xcpt_bits_ftq_idx_0; // @[rob.scala:199:7]
wire io_com_xcpt_bits_edge_inst_0; // @[rob.scala:199:7]
wire io_com_xcpt_bits_is_rvc; // @[rob.scala:199:7]
wire [5:0] io_com_xcpt_bits_pc_lob_0; // @[rob.scala:199:7]
wire [63:0] io_com_xcpt_bits_cause_0; // @[rob.scala:199:7]
wire [63:0] io_com_xcpt_bits_badvaddr_0; // @[rob.scala:199:7]
wire io_com_xcpt_valid_0; // @[rob.scala:199:7]
wire [4:0] io_flush_bits_ftq_idx_0; // @[rob.scala:199:7]
wire io_flush_bits_edge_inst_0; // @[rob.scala:199:7]
wire io_flush_bits_is_rvc_0; // @[rob.scala:199:7]
wire [5:0] io_flush_bits_pc_lob_0; // @[rob.scala:199:7]
wire [2:0] io_flush_bits_flush_typ_0; // @[rob.scala:199:7]
wire io_flush_valid_0; // @[rob.scala:199:7]
wire [5:0] io_rob_tail_idx_0; // @[rob.scala:199:7]
wire [5:0] io_rob_pnr_idx_0; // @[rob.scala:199:7]
wire [5:0] io_rob_head_idx_0; // @[rob.scala:199:7]
wire io_rollback_0; // @[rob.scala:199:7]
wire io_com_load_is_at_rob_head_0; // @[rob.scala:199:7]
wire io_empty_0; // @[rob.scala:199:7]
wire io_ready_0; // @[rob.scala:199:7]
wire io_flush_frontend_0; // @[rob.scala:199:7]
reg [1:0] rob_state; // @[rob.scala:207:26]
reg [4:0] rob_head; // @[rob.scala:210:29]
reg rob_head_lsb; // @[rob.scala:211:29]
assign rob_head_idx = {rob_head, rob_head_lsb}; // @[rob.scala:210:29, :211:29, :212:59]
assign io_rob_head_idx_0 = rob_head_idx; // @[rob.scala:199:7, :212:59]
reg [4:0] rob_tail; // @[rob.scala:214:29]
reg rob_tail_lsb; // @[rob.scala:215:29]
assign rob_tail_idx = {rob_tail, rob_tail_lsb}; // @[rob.scala:214:29, :215:29, :216:59]
assign io_rob_tail_idx_0 = rob_tail_idx; // @[rob.scala:199:7, :216:59]
reg [4:0] rob_pnr; // @[rob.scala:218:29]
reg rob_pnr_lsb; // @[rob.scala:219:29]
assign rob_pnr_idx = {rob_pnr, rob_pnr_lsb}; // @[rob.scala:218:29, :219:29, :220:59]
assign io_rob_pnr_idx_0 = rob_pnr_idx; // @[rob.scala:199:7, :220:59]
wire [4:0] next_rob_head; // @[rob.scala:222:31]
wire [4:0] _rob_compact_uop_rdata_WIRE = next_rob_head; // @[rob.scala:222:31, :340:55]
wire _full_T_3; // @[rob.scala:792:47]
wire full; // @[rob.scala:226:26]
wire _empty_T_3; // @[rob.scala:793:41]
assign io_empty_0 = empty; // @[rob.scala:199:7, :227:26]
wire _will_commit_0_T_3; // @[rob.scala:574:70]
assign io_commit_valids_0_0 = will_commit_0; // @[rob.scala:199:7, :229:33]
wire _will_commit_1_T_3; // @[rob.scala:574:70]
assign io_commit_valids_1_0 = will_commit_1; // @[rob.scala:199:7, :229:33]
wire _can_commit_0_T_5; // @[rob.scala:451:81]
wire _can_commit_1_T_5; // @[rob.scala:451:81]
wire can_commit_0; // @[rob.scala:230:33]
wire can_commit_1; // @[rob.scala:230:33]
wire _can_throw_exception_0_T; // @[rob.scala:444:49]
wire _can_throw_exception_1_T; // @[rob.scala:444:49]
wire can_throw_exception_0; // @[rob.scala:231:33]
wire can_throw_exception_1; // @[rob.scala:231:33]
wire _rob_pnr_unsafe_0_T_1; // @[rob.scala:528:43]
wire _rob_pnr_unsafe_1_T_1; // @[rob.scala:528:43]
wire rob_pnr_unsafe_0; // @[rob.scala:233:33]
wire rob_pnr_unsafe_1; // @[rob.scala:233:33]
wire rob_head_vals_0; // @[rob.scala:234:33]
wire rob_head_vals_1; // @[rob.scala:234:33]
wire rob_tail_vals_0; // @[rob.scala:235:33]
wire rob_tail_vals_1; // @[rob.scala:235:33]
wire rob_head_fflags_0_valid; // @[rob.scala:238:33]
wire [4:0] rob_head_fflags_0_bits; // @[rob.scala:238:33]
wire rob_head_fflags_1_valid; // @[rob.scala:238:33]
wire [4:0] rob_head_fflags_1_bits; // @[rob.scala:238:33]
wire exception_thrown; // @[rob.scala:240:30]
reg r_xcpt_val; // @[rob.scala:244:33]
assign io_flush_frontend_0 = r_xcpt_val; // @[rob.scala:199:7, :244:33]
reg [31:0] r_xcpt_uop_inst; // @[rob.scala:245:29]
reg [31:0] r_xcpt_uop_debug_inst; // @[rob.scala:245:29]
reg r_xcpt_uop_is_rvc; // @[rob.scala:245:29]
reg [39:0] r_xcpt_uop_debug_pc; // @[rob.scala:245:29]
reg r_xcpt_uop_iq_type_0; // @[rob.scala:245:29]
reg r_xcpt_uop_iq_type_1; // @[rob.scala:245:29]
reg r_xcpt_uop_iq_type_2; // @[rob.scala:245:29]
reg r_xcpt_uop_iq_type_3; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_0; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_1; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_2; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_3; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_4; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_5; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_6; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_7; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_8; // @[rob.scala:245:29]
reg r_xcpt_uop_fu_code_9; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_issued; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_issued_partial_agen; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_issued_partial_dgen; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_iw_p1_speculative_child; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_iw_p2_speculative_child; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_p1_bypass_hint; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_p2_bypass_hint; // @[rob.scala:245:29]
reg r_xcpt_uop_iw_p3_bypass_hint; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_dis_col_sel; // @[rob.scala:245:29]
reg [11:0] r_xcpt_uop_br_mask; // @[rob.scala:245:29]
reg [3:0] r_xcpt_uop_br_tag; // @[rob.scala:245:29]
reg [3:0] r_xcpt_uop_br_type; // @[rob.scala:245:29]
reg r_xcpt_uop_is_sfb; // @[rob.scala:245:29]
reg r_xcpt_uop_is_fence; // @[rob.scala:245:29]
reg r_xcpt_uop_is_fencei; // @[rob.scala:245:29]
reg r_xcpt_uop_is_sfence; // @[rob.scala:245:29]
reg r_xcpt_uop_is_amo; // @[rob.scala:245:29]
reg r_xcpt_uop_is_eret; // @[rob.scala:245:29]
reg r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:245:29]
reg r_xcpt_uop_is_rocc; // @[rob.scala:245:29]
reg r_xcpt_uop_is_mov; // @[rob.scala:245:29]
reg [4:0] r_xcpt_uop_ftq_idx; // @[rob.scala:245:29]
reg r_xcpt_uop_edge_inst; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_pc_lob; // @[rob.scala:245:29]
reg r_xcpt_uop_taken; // @[rob.scala:245:29]
reg r_xcpt_uop_imm_rename; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_imm_sel; // @[rob.scala:245:29]
reg [4:0] r_xcpt_uop_pimm; // @[rob.scala:245:29]
reg [19:0] r_xcpt_uop_imm_packed; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_op1_sel; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_op2_sel; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_ldst; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_wen; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_ren1; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_ren2; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_ren3; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_swap12; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_swap23; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_fp_ctrl_typeTagIn; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_fp_ctrl_typeTagOut; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_fromint; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_toint; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_fastpipe; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_fma; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_div; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_sqrt; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_wflags; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_ctrl_vec; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_rob_idx; // @[rob.scala:245:29]
reg [3:0] r_xcpt_uop_ldq_idx; // @[rob.scala:245:29]
reg [3:0] r_xcpt_uop_stq_idx; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_rxq_idx; // @[rob.scala:245:29]
reg [6:0] r_xcpt_uop_pdst; // @[rob.scala:245:29]
reg [6:0] r_xcpt_uop_prs1; // @[rob.scala:245:29]
reg [6:0] r_xcpt_uop_prs2; // @[rob.scala:245:29]
reg [6:0] r_xcpt_uop_prs3; // @[rob.scala:245:29]
reg [4:0] r_xcpt_uop_ppred; // @[rob.scala:245:29]
reg r_xcpt_uop_prs1_busy; // @[rob.scala:245:29]
reg r_xcpt_uop_prs2_busy; // @[rob.scala:245:29]
reg r_xcpt_uop_prs3_busy; // @[rob.scala:245:29]
reg r_xcpt_uop_ppred_busy; // @[rob.scala:245:29]
reg [6:0] r_xcpt_uop_stale_pdst; // @[rob.scala:245:29]
reg r_xcpt_uop_exception; // @[rob.scala:245:29]
reg [63:0] r_xcpt_uop_exc_cause; // @[rob.scala:245:29]
assign io_com_xcpt_bits_cause_0 = r_xcpt_uop_exc_cause; // @[rob.scala:199:7, :245:29]
reg [4:0] r_xcpt_uop_mem_cmd; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_mem_size; // @[rob.scala:245:29]
reg r_xcpt_uop_mem_signed; // @[rob.scala:245:29]
reg r_xcpt_uop_uses_ldq; // @[rob.scala:245:29]
reg r_xcpt_uop_uses_stq; // @[rob.scala:245:29]
reg r_xcpt_uop_is_unique; // @[rob.scala:245:29]
reg r_xcpt_uop_flush_on_commit; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_csr_cmd; // @[rob.scala:245:29]
reg r_xcpt_uop_ldst_is_rs1; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_ldst; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_lrs1; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_lrs2; // @[rob.scala:245:29]
reg [5:0] r_xcpt_uop_lrs3; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_dst_rtype; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_lrs1_rtype; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_lrs2_rtype; // @[rob.scala:245:29]
reg r_xcpt_uop_frs3_en; // @[rob.scala:245:29]
reg r_xcpt_uop_fcn_dw; // @[rob.scala:245:29]
reg [4:0] r_xcpt_uop_fcn_op; // @[rob.scala:245:29]
reg r_xcpt_uop_fp_val; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_fp_rm; // @[rob.scala:245:29]
reg [1:0] r_xcpt_uop_fp_typ; // @[rob.scala:245:29]
reg r_xcpt_uop_xcpt_pf_if; // @[rob.scala:245:29]
reg r_xcpt_uop_xcpt_ae_if; // @[rob.scala:245:29]
reg r_xcpt_uop_xcpt_ma_if; // @[rob.scala:245:29]
reg r_xcpt_uop_bp_debug_if; // @[rob.scala:245:29]
reg r_xcpt_uop_bp_xcpt_if; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_debug_fsrc; // @[rob.scala:245:29]
reg [2:0] r_xcpt_uop_debug_tsrc; // @[rob.scala:245:29]
reg [39:0] r_xcpt_badvaddr; // @[rob.scala:246:29]
wire _rob_unsafe_masked_0_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_1_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_2_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_3_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_4_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_5_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_6_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_7_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_8_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_9_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_10_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_11_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_12_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_13_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_14_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_15_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_16_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_17_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_18_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_19_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_20_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_21_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_22_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_23_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_24_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_25_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_26_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_27_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_28_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_29_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_30_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_31_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_32_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_33_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_34_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_35_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_36_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_37_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_38_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_39_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_40_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_41_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_42_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_43_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_44_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_45_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_46_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_47_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_48_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_49_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_50_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_51_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_52_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_53_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_54_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_55_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_56_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_57_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_58_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_59_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_60_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_61_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_62_T_1; // @[rob.scala:525:71]
wire _rob_unsafe_masked_63_T_1; // @[rob.scala:525:71]
wire rob_unsafe_masked_0; // @[rob.scala:280:35]
wire rob_unsafe_masked_1; // @[rob.scala:280:35]
wire rob_unsafe_masked_2; // @[rob.scala:280:35]
wire rob_unsafe_masked_3; // @[rob.scala:280:35]
wire rob_unsafe_masked_4; // @[rob.scala:280:35]
wire rob_unsafe_masked_5; // @[rob.scala:280:35]
wire rob_unsafe_masked_6; // @[rob.scala:280:35]
wire rob_unsafe_masked_7; // @[rob.scala:280:35]
wire rob_unsafe_masked_8; // @[rob.scala:280:35]
wire rob_unsafe_masked_9; // @[rob.scala:280:35]
wire rob_unsafe_masked_10; // @[rob.scala:280:35]
wire rob_unsafe_masked_11; // @[rob.scala:280:35]
wire rob_unsafe_masked_12; // @[rob.scala:280:35]
wire rob_unsafe_masked_13; // @[rob.scala:280:35]
wire rob_unsafe_masked_14; // @[rob.scala:280:35]
wire rob_unsafe_masked_15; // @[rob.scala:280:35]
wire rob_unsafe_masked_16; // @[rob.scala:280:35]
wire rob_unsafe_masked_17; // @[rob.scala:280:35]
wire rob_unsafe_masked_18; // @[rob.scala:280:35]
wire rob_unsafe_masked_19; // @[rob.scala:280:35]
wire rob_unsafe_masked_20; // @[rob.scala:280:35]
wire rob_unsafe_masked_21; // @[rob.scala:280:35]
wire rob_unsafe_masked_22; // @[rob.scala:280:35]
wire rob_unsafe_masked_23; // @[rob.scala:280:35]
wire rob_unsafe_masked_24; // @[rob.scala:280:35]
wire rob_unsafe_masked_25; // @[rob.scala:280:35]
wire rob_unsafe_masked_26; // @[rob.scala:280:35]
wire rob_unsafe_masked_27; // @[rob.scala:280:35]
wire rob_unsafe_masked_28; // @[rob.scala:280:35]
wire rob_unsafe_masked_29; // @[rob.scala:280:35]
wire rob_unsafe_masked_30; // @[rob.scala:280:35]
wire rob_unsafe_masked_31; // @[rob.scala:280:35]
wire rob_unsafe_masked_32; // @[rob.scala:280:35]
wire rob_unsafe_masked_33; // @[rob.scala:280:35]
wire rob_unsafe_masked_34; // @[rob.scala:280:35]
wire rob_unsafe_masked_35; // @[rob.scala:280:35]
wire rob_unsafe_masked_36; // @[rob.scala:280:35]
wire rob_unsafe_masked_37; // @[rob.scala:280:35]
wire rob_unsafe_masked_38; // @[rob.scala:280:35]
wire rob_unsafe_masked_39; // @[rob.scala:280:35]
wire rob_unsafe_masked_40; // @[rob.scala:280:35]
wire rob_unsafe_masked_41; // @[rob.scala:280:35]
wire rob_unsafe_masked_42; // @[rob.scala:280:35]
wire rob_unsafe_masked_43; // @[rob.scala:280:35]
wire rob_unsafe_masked_44; // @[rob.scala:280:35]
wire rob_unsafe_masked_45; // @[rob.scala:280:35]
wire rob_unsafe_masked_46; // @[rob.scala:280:35]
wire rob_unsafe_masked_47; // @[rob.scala:280:35]
wire rob_unsafe_masked_48; // @[rob.scala:280:35]
wire rob_unsafe_masked_49; // @[rob.scala:280:35]
wire rob_unsafe_masked_50; // @[rob.scala:280:35]
wire rob_unsafe_masked_51; // @[rob.scala:280:35]
wire rob_unsafe_masked_52; // @[rob.scala:280:35]
wire rob_unsafe_masked_53; // @[rob.scala:280:35]
wire rob_unsafe_masked_54; // @[rob.scala:280:35]
wire rob_unsafe_masked_55; // @[rob.scala:280:35]
wire rob_unsafe_masked_56; // @[rob.scala:280:35]
wire rob_unsafe_masked_57; // @[rob.scala:280:35]
wire rob_unsafe_masked_58; // @[rob.scala:280:35]
wire rob_unsafe_masked_59; // @[rob.scala:280:35]
wire rob_unsafe_masked_60; // @[rob.scala:280:35]
wire rob_unsafe_masked_61; // @[rob.scala:280:35]
wire rob_unsafe_masked_62; // @[rob.scala:280:35]
wire rob_unsafe_masked_63; // @[rob.scala:280:35]
wire [5:0] _GEN = {1'h0, io_brupdate_b2_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] brupdate_b2_rob_row; // @[rob.scala:254:25]
assign brupdate_b2_rob_row = _GEN; // @[rob.scala:254:25]
wire [5:0] _rob_tail_T; // @[rob.scala:254:25]
assign _rob_tail_T = _GEN; // @[rob.scala:254:25]
wire [63:0] _GEN_0 = 64'h1 << brupdate_b2_rob_row; // @[OneHot.scala:58:35]
wire [63:0] brupdate_b2_rob_row_oh; // @[OneHot.scala:58:35]
assign brupdate_b2_rob_row_oh = _GEN_0; // @[OneHot.scala:58:35]
wire [63:0] _brupdate_b2_rob_clr_oh_hi_mask_T; // @[OneHot.scala:58:35]
assign _brupdate_b2_rob_clr_oh_hi_mask_T = _GEN_0; // @[OneHot.scala:58:35]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_1 = _brupdate_b2_rob_clr_oh_hi_mask_T[31:0]; // @[OneHot.scala:58:35]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_2 = _brupdate_b2_rob_clr_oh_hi_mask_T_1; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_3 = {1'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:1]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_4 = {2'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:2]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_5 = {3'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:3]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_6 = {4'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:4]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_7 = {5'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:5]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_8 = {6'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:6]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_9 = {7'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:7]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_10 = {8'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:8]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_11 = {9'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:9]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_12 = {10'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:10]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_13 = {11'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:11]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_14 = {12'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:12]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_15 = {13'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:13]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_16 = {14'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:14]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_17 = {15'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:15]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_18 = {16'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:16]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_19 = {17'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:17]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_20 = {18'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:18]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_21 = {19'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:19]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_22 = {20'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:20]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_23 = {21'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:21]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_24 = {22'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:22]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_25 = {23'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:23]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_26 = {24'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:24]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_27 = {25'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:25]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_28 = {26'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:26]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_29 = {27'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:27]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_30 = {28'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:28]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_31 = {29'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:29]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_32 = {30'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31:30]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_33 = {31'h0, _brupdate_b2_rob_clr_oh_hi_mask_T_1[31]}; // @[util.scala:370:41, :383:29]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_34 = _brupdate_b2_rob_clr_oh_hi_mask_T_2 | _brupdate_b2_rob_clr_oh_hi_mask_T_3; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_35 = _brupdate_b2_rob_clr_oh_hi_mask_T_34 | _brupdate_b2_rob_clr_oh_hi_mask_T_4; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_36 = _brupdate_b2_rob_clr_oh_hi_mask_T_35 | _brupdate_b2_rob_clr_oh_hi_mask_T_5; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_37 = _brupdate_b2_rob_clr_oh_hi_mask_T_36 | _brupdate_b2_rob_clr_oh_hi_mask_T_6; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_38 = _brupdate_b2_rob_clr_oh_hi_mask_T_37 | _brupdate_b2_rob_clr_oh_hi_mask_T_7; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_39 = _brupdate_b2_rob_clr_oh_hi_mask_T_38 | _brupdate_b2_rob_clr_oh_hi_mask_T_8; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_40 = _brupdate_b2_rob_clr_oh_hi_mask_T_39 | _brupdate_b2_rob_clr_oh_hi_mask_T_9; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_41 = _brupdate_b2_rob_clr_oh_hi_mask_T_40 | _brupdate_b2_rob_clr_oh_hi_mask_T_10; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_42 = _brupdate_b2_rob_clr_oh_hi_mask_T_41 | _brupdate_b2_rob_clr_oh_hi_mask_T_11; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_43 = _brupdate_b2_rob_clr_oh_hi_mask_T_42 | _brupdate_b2_rob_clr_oh_hi_mask_T_12; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_44 = _brupdate_b2_rob_clr_oh_hi_mask_T_43 | _brupdate_b2_rob_clr_oh_hi_mask_T_13; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_45 = _brupdate_b2_rob_clr_oh_hi_mask_T_44 | _brupdate_b2_rob_clr_oh_hi_mask_T_14; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_46 = _brupdate_b2_rob_clr_oh_hi_mask_T_45 | _brupdate_b2_rob_clr_oh_hi_mask_T_15; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_47 = _brupdate_b2_rob_clr_oh_hi_mask_T_46 | _brupdate_b2_rob_clr_oh_hi_mask_T_16; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_48 = _brupdate_b2_rob_clr_oh_hi_mask_T_47 | _brupdate_b2_rob_clr_oh_hi_mask_T_17; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_49 = _brupdate_b2_rob_clr_oh_hi_mask_T_48 | _brupdate_b2_rob_clr_oh_hi_mask_T_18; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_50 = _brupdate_b2_rob_clr_oh_hi_mask_T_49 | _brupdate_b2_rob_clr_oh_hi_mask_T_19; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_51 = _brupdate_b2_rob_clr_oh_hi_mask_T_50 | _brupdate_b2_rob_clr_oh_hi_mask_T_20; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_52 = _brupdate_b2_rob_clr_oh_hi_mask_T_51 | _brupdate_b2_rob_clr_oh_hi_mask_T_21; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_53 = _brupdate_b2_rob_clr_oh_hi_mask_T_52 | _brupdate_b2_rob_clr_oh_hi_mask_T_22; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_54 = _brupdate_b2_rob_clr_oh_hi_mask_T_53 | _brupdate_b2_rob_clr_oh_hi_mask_T_23; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_55 = _brupdate_b2_rob_clr_oh_hi_mask_T_54 | _brupdate_b2_rob_clr_oh_hi_mask_T_24; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_56 = _brupdate_b2_rob_clr_oh_hi_mask_T_55 | _brupdate_b2_rob_clr_oh_hi_mask_T_25; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_57 = _brupdate_b2_rob_clr_oh_hi_mask_T_56 | _brupdate_b2_rob_clr_oh_hi_mask_T_26; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_58 = _brupdate_b2_rob_clr_oh_hi_mask_T_57 | _brupdate_b2_rob_clr_oh_hi_mask_T_27; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_59 = _brupdate_b2_rob_clr_oh_hi_mask_T_58 | _brupdate_b2_rob_clr_oh_hi_mask_T_28; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_60 = _brupdate_b2_rob_clr_oh_hi_mask_T_59 | _brupdate_b2_rob_clr_oh_hi_mask_T_29; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_61 = _brupdate_b2_rob_clr_oh_hi_mask_T_60 | _brupdate_b2_rob_clr_oh_hi_mask_T_30; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_62 = _brupdate_b2_rob_clr_oh_hi_mask_T_61 | _brupdate_b2_rob_clr_oh_hi_mask_T_31; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_63 = _brupdate_b2_rob_clr_oh_hi_mask_T_62 | _brupdate_b2_rob_clr_oh_hi_mask_T_32; // @[util.scala:383:{29,45}]
wire [31:0] _brupdate_b2_rob_clr_oh_hi_mask_T_64 = _brupdate_b2_rob_clr_oh_hi_mask_T_63 | _brupdate_b2_rob_clr_oh_hi_mask_T_33; // @[util.scala:383:{29,45}]
wire [31:0] brupdate_b2_rob_clr_oh_hi_mask = ~_brupdate_b2_rob_clr_oh_hi_mask_T_64; // @[util.scala:370:19, :383:45]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T = 32'h1 << rob_head; // @[OneHot.scala:58:35]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_1 = _brupdate_b2_rob_clr_oh_lo_mask_T; // @[OneHot.scala:58:35]
wire [32:0] _brupdate_b2_rob_clr_oh_lo_mask_T_2 = {1'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_3 = _brupdate_b2_rob_clr_oh_lo_mask_T_2[31:0]; // @[util.scala:394:{30,37}]
wire [32:0] _brupdate_b2_rob_clr_oh_lo_mask_T_4 = {_brupdate_b2_rob_clr_oh_lo_mask_T_1, 1'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_5 = _brupdate_b2_rob_clr_oh_lo_mask_T_4[31:0]; // @[util.scala:394:{30,37}]
wire [34:0] _brupdate_b2_rob_clr_oh_lo_mask_T_6 = {1'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 2'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_7 = _brupdate_b2_rob_clr_oh_lo_mask_T_6[31:0]; // @[util.scala:394:{30,37}]
wire [34:0] _brupdate_b2_rob_clr_oh_lo_mask_T_8 = {_brupdate_b2_rob_clr_oh_lo_mask_T_1, 3'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_9 = _brupdate_b2_rob_clr_oh_lo_mask_T_8[31:0]; // @[util.scala:394:{30,37}]
wire [38:0] _brupdate_b2_rob_clr_oh_lo_mask_T_10 = {3'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 4'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_11 = _brupdate_b2_rob_clr_oh_lo_mask_T_10[31:0]; // @[util.scala:394:{30,37}]
wire [38:0] _brupdate_b2_rob_clr_oh_lo_mask_T_12 = {2'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 5'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_13 = _brupdate_b2_rob_clr_oh_lo_mask_T_12[31:0]; // @[util.scala:394:{30,37}]
wire [38:0] _brupdate_b2_rob_clr_oh_lo_mask_T_14 = {1'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 6'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_15 = _brupdate_b2_rob_clr_oh_lo_mask_T_14[31:0]; // @[util.scala:394:{30,37}]
wire [38:0] _brupdate_b2_rob_clr_oh_lo_mask_T_16 = {_brupdate_b2_rob_clr_oh_lo_mask_T_1, 7'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_17 = _brupdate_b2_rob_clr_oh_lo_mask_T_16[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_18 = {7'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 8'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_19 = _brupdate_b2_rob_clr_oh_lo_mask_T_18[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_20 = {6'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 9'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_21 = _brupdate_b2_rob_clr_oh_lo_mask_T_20[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_22 = {5'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 10'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_23 = _brupdate_b2_rob_clr_oh_lo_mask_T_22[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_24 = {4'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 11'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_25 = _brupdate_b2_rob_clr_oh_lo_mask_T_24[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_26 = {3'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 12'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_27 = _brupdate_b2_rob_clr_oh_lo_mask_T_26[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_28 = {2'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 13'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_29 = _brupdate_b2_rob_clr_oh_lo_mask_T_28[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_30 = {1'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 14'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_31 = _brupdate_b2_rob_clr_oh_lo_mask_T_30[31:0]; // @[util.scala:394:{30,37}]
wire [46:0] _brupdate_b2_rob_clr_oh_lo_mask_T_32 = {_brupdate_b2_rob_clr_oh_lo_mask_T_1, 15'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_33 = _brupdate_b2_rob_clr_oh_lo_mask_T_32[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_34 = {15'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 16'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_35 = _brupdate_b2_rob_clr_oh_lo_mask_T_34[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_36 = {14'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 17'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_37 = _brupdate_b2_rob_clr_oh_lo_mask_T_36[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_38 = {13'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 18'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_39 = _brupdate_b2_rob_clr_oh_lo_mask_T_38[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_40 = {12'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 19'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_41 = _brupdate_b2_rob_clr_oh_lo_mask_T_40[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_42 = {11'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 20'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_43 = _brupdate_b2_rob_clr_oh_lo_mask_T_42[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_44 = {10'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 21'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_45 = _brupdate_b2_rob_clr_oh_lo_mask_T_44[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_46 = {9'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 22'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_47 = _brupdate_b2_rob_clr_oh_lo_mask_T_46[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_48 = {8'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 23'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_49 = _brupdate_b2_rob_clr_oh_lo_mask_T_48[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_50 = {7'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 24'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_51 = _brupdate_b2_rob_clr_oh_lo_mask_T_50[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_52 = {6'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 25'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_53 = _brupdate_b2_rob_clr_oh_lo_mask_T_52[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_54 = {5'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 26'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_55 = _brupdate_b2_rob_clr_oh_lo_mask_T_54[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_56 = {4'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 27'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_57 = _brupdate_b2_rob_clr_oh_lo_mask_T_56[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_58 = {3'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 28'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_59 = _brupdate_b2_rob_clr_oh_lo_mask_T_58[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_60 = {2'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 29'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_61 = _brupdate_b2_rob_clr_oh_lo_mask_T_60[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_62 = {1'h0, _brupdate_b2_rob_clr_oh_lo_mask_T_1, 30'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_63 = _brupdate_b2_rob_clr_oh_lo_mask_T_62[31:0]; // @[util.scala:394:{30,37}]
wire [62:0] _brupdate_b2_rob_clr_oh_lo_mask_T_64 = {_brupdate_b2_rob_clr_oh_lo_mask_T_1, 31'h0}; // @[util.scala:371:44, :394:30]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_65 = _brupdate_b2_rob_clr_oh_lo_mask_T_64[31:0]; // @[util.scala:394:{30,37}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_66 = _brupdate_b2_rob_clr_oh_lo_mask_T_3 | _brupdate_b2_rob_clr_oh_lo_mask_T_5; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_67 = _brupdate_b2_rob_clr_oh_lo_mask_T_66 | _brupdate_b2_rob_clr_oh_lo_mask_T_7; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_68 = _brupdate_b2_rob_clr_oh_lo_mask_T_67 | _brupdate_b2_rob_clr_oh_lo_mask_T_9; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_69 = _brupdate_b2_rob_clr_oh_lo_mask_T_68 | _brupdate_b2_rob_clr_oh_lo_mask_T_11; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_70 = _brupdate_b2_rob_clr_oh_lo_mask_T_69 | _brupdate_b2_rob_clr_oh_lo_mask_T_13; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_71 = _brupdate_b2_rob_clr_oh_lo_mask_T_70 | _brupdate_b2_rob_clr_oh_lo_mask_T_15; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_72 = _brupdate_b2_rob_clr_oh_lo_mask_T_71 | _brupdate_b2_rob_clr_oh_lo_mask_T_17; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_73 = _brupdate_b2_rob_clr_oh_lo_mask_T_72 | _brupdate_b2_rob_clr_oh_lo_mask_T_19; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_74 = _brupdate_b2_rob_clr_oh_lo_mask_T_73 | _brupdate_b2_rob_clr_oh_lo_mask_T_21; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_75 = _brupdate_b2_rob_clr_oh_lo_mask_T_74 | _brupdate_b2_rob_clr_oh_lo_mask_T_23; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_76 = _brupdate_b2_rob_clr_oh_lo_mask_T_75 | _brupdate_b2_rob_clr_oh_lo_mask_T_25; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_77 = _brupdate_b2_rob_clr_oh_lo_mask_T_76 | _brupdate_b2_rob_clr_oh_lo_mask_T_27; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_78 = _brupdate_b2_rob_clr_oh_lo_mask_T_77 | _brupdate_b2_rob_clr_oh_lo_mask_T_29; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_79 = _brupdate_b2_rob_clr_oh_lo_mask_T_78 | _brupdate_b2_rob_clr_oh_lo_mask_T_31; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_80 = _brupdate_b2_rob_clr_oh_lo_mask_T_79 | _brupdate_b2_rob_clr_oh_lo_mask_T_33; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_81 = _brupdate_b2_rob_clr_oh_lo_mask_T_80 | _brupdate_b2_rob_clr_oh_lo_mask_T_35; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_82 = _brupdate_b2_rob_clr_oh_lo_mask_T_81 | _brupdate_b2_rob_clr_oh_lo_mask_T_37; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_83 = _brupdate_b2_rob_clr_oh_lo_mask_T_82 | _brupdate_b2_rob_clr_oh_lo_mask_T_39; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_84 = _brupdate_b2_rob_clr_oh_lo_mask_T_83 | _brupdate_b2_rob_clr_oh_lo_mask_T_41; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_85 = _brupdate_b2_rob_clr_oh_lo_mask_T_84 | _brupdate_b2_rob_clr_oh_lo_mask_T_43; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_86 = _brupdate_b2_rob_clr_oh_lo_mask_T_85 | _brupdate_b2_rob_clr_oh_lo_mask_T_45; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_87 = _brupdate_b2_rob_clr_oh_lo_mask_T_86 | _brupdate_b2_rob_clr_oh_lo_mask_T_47; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_88 = _brupdate_b2_rob_clr_oh_lo_mask_T_87 | _brupdate_b2_rob_clr_oh_lo_mask_T_49; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_89 = _brupdate_b2_rob_clr_oh_lo_mask_T_88 | _brupdate_b2_rob_clr_oh_lo_mask_T_51; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_90 = _brupdate_b2_rob_clr_oh_lo_mask_T_89 | _brupdate_b2_rob_clr_oh_lo_mask_T_53; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_91 = _brupdate_b2_rob_clr_oh_lo_mask_T_90 | _brupdate_b2_rob_clr_oh_lo_mask_T_55; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_92 = _brupdate_b2_rob_clr_oh_lo_mask_T_91 | _brupdate_b2_rob_clr_oh_lo_mask_T_57; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_93 = _brupdate_b2_rob_clr_oh_lo_mask_T_92 | _brupdate_b2_rob_clr_oh_lo_mask_T_59; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_94 = _brupdate_b2_rob_clr_oh_lo_mask_T_93 | _brupdate_b2_rob_clr_oh_lo_mask_T_61; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_95 = _brupdate_b2_rob_clr_oh_lo_mask_T_94 | _brupdate_b2_rob_clr_oh_lo_mask_T_63; // @[util.scala:394:{37,54}]
wire [31:0] _brupdate_b2_rob_clr_oh_lo_mask_T_96 = _brupdate_b2_rob_clr_oh_lo_mask_T_95 | _brupdate_b2_rob_clr_oh_lo_mask_T_65; // @[util.scala:394:{37,54}]
wire [31:0] brupdate_b2_rob_clr_oh_lo_mask = ~_brupdate_b2_rob_clr_oh_lo_mask_T_96; // @[util.scala:371:19, :394:54]
wire [5:0] _GEN_1 = {1'h0, rob_head}; // @[util.scala:372:11]
wire _brupdate_b2_rob_clr_oh_T = brupdate_b2_rob_row < _GEN_1; // @[util.scala:372:11]
wire [31:0] _brupdate_b2_rob_clr_oh_T_1 = brupdate_b2_rob_clr_oh_hi_mask & brupdate_b2_rob_clr_oh_lo_mask; // @[util.scala:370:19, :371:19, :372:27]
wire [31:0] _brupdate_b2_rob_clr_oh_T_2 = brupdate_b2_rob_clr_oh_hi_mask | brupdate_b2_rob_clr_oh_lo_mask; // @[util.scala:370:19, :371:19, :372:46]
wire [31:0] _brupdate_b2_rob_clr_oh_T_3 = _brupdate_b2_rob_clr_oh_T ? _brupdate_b2_rob_clr_oh_T_1 : _brupdate_b2_rob_clr_oh_T_2; // @[util.scala:372:{8,11,27,46}]
wire [31:0] brupdate_b2_rob_clr_oh = _brupdate_b2_rob_clr_oh_T_3; // @[util.scala:372:{8,56}]
wire brupdate_b2_rob_bank_idx = io_brupdate_b2_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36]
wire [1:0] _brupdate_b2_rob_bank_clr_oh_T = 2'h1 << brupdate_b2_rob_bank_idx; // @[OneHot.scala:58:35]
wire [1:0] _brupdate_b2_rob_bank_clr_oh_T_1 = _brupdate_b2_rob_bank_clr_oh_T; // @[OneHot.scala:58:35]
wire [1:0] _brupdate_b2_rob_bank_clr_oh_T_2 = {1'h0, _brupdate_b2_rob_bank_clr_oh_T[1]}; // @[OneHot.scala:58:35]
wire [1:0] _brupdate_b2_rob_bank_clr_oh_T_3 = _brupdate_b2_rob_bank_clr_oh_T_1 | _brupdate_b2_rob_bank_clr_oh_T_2; // @[util.scala:383:{29,45}]
wire [1:0] brupdate_b2_rob_bank_clr_oh = ~_brupdate_b2_rob_bank_clr_oh_T_3; // @[util.scala:383:45]
wire [29:0] rob_compact_uop_wdata_0; // @[rob.scala:338:38]
wire [29:0] rob_compact_uop_wdata_1; // @[rob.scala:338:38]
wire [13:0] rob_compact_uop_wdata_lo_lo = {rob_compact_uop_wdata_out_pdst, rob_compact_uop_wdata_out_stale_pdst}; // @[rob.scala:325:19, :338:78]
wire [7:0] rob_compact_uop_wdata_lo_hi = {rob_compact_uop_wdata_out_dst_rtype, rob_compact_uop_wdata_out_ldst}; // @[rob.scala:325:19, :338:78]
wire [21:0] rob_compact_uop_wdata_lo = {rob_compact_uop_wdata_lo_hi, rob_compact_uop_wdata_lo_lo}; // @[rob.scala:338:78]
wire [1:0] rob_compact_uop_wdata_hi_lo = {rob_compact_uop_wdata_out_uses_ldq, rob_compact_uop_wdata_out_uses_stq}; // @[rob.scala:325:19, :338:78]
wire [5:0] rob_compact_uop_wdata_hi_hi = {rob_compact_uop_wdata_out_is_fencei, rob_compact_uop_wdata_out_ftq_idx}; // @[rob.scala:325:19, :338:78]
wire [7:0] rob_compact_uop_wdata_hi = {rob_compact_uop_wdata_hi_hi, rob_compact_uop_wdata_hi_lo}; // @[rob.scala:338:78]
wire [29:0] _rob_compact_uop_wdata_T = {rob_compact_uop_wdata_hi, rob_compact_uop_wdata_lo}; // @[rob.scala:338:78]
assign rob_compact_uop_wdata_0 = _rob_compact_uop_wdata_T; // @[rob.scala:338:{38,78}]
wire [13:0] rob_compact_uop_wdata_lo_lo_1 = {rob_compact_uop_wdata_out_1_pdst, rob_compact_uop_wdata_out_1_stale_pdst}; // @[rob.scala:325:19, :338:78]
wire [7:0] rob_compact_uop_wdata_lo_hi_1 = {rob_compact_uop_wdata_out_1_dst_rtype, rob_compact_uop_wdata_out_1_ldst}; // @[rob.scala:325:19, :338:78]
wire [21:0] rob_compact_uop_wdata_lo_1 = {rob_compact_uop_wdata_lo_hi_1, rob_compact_uop_wdata_lo_lo_1}; // @[rob.scala:338:78]
wire [1:0] rob_compact_uop_wdata_hi_lo_1 = {rob_compact_uop_wdata_out_1_uses_ldq, rob_compact_uop_wdata_out_1_uses_stq}; // @[rob.scala:325:19, :338:78]
wire [5:0] rob_compact_uop_wdata_hi_hi_1 = {rob_compact_uop_wdata_out_1_is_fencei, rob_compact_uop_wdata_out_1_ftq_idx}; // @[rob.scala:325:19, :338:78]
wire [7:0] rob_compact_uop_wdata_hi_1 = {rob_compact_uop_wdata_hi_hi_1, rob_compact_uop_wdata_hi_lo_1}; // @[rob.scala:338:78]
wire [29:0] _rob_compact_uop_wdata_T_1 = {rob_compact_uop_wdata_hi_1, rob_compact_uop_wdata_lo_1}; // @[rob.scala:338:78]
assign rob_compact_uop_wdata_1 = _rob_compact_uop_wdata_T_1; // @[rob.scala:338:{38,78}]
wire [4:0] _rob_compact_uop_rdata_T = _rob_compact_uop_rdata_WIRE; // @[rob.scala:340:55]
wire [4:0] _rob_compact_uop_rdata_T_1 = _rob_compact_uop_rdata_T; // @[rob.scala:340:55]
reg [4:0] rob_compact_uop_might_bypass_REG; // @[rob.scala:341:58]
wire rob_compact_uop_might_bypass = rob_head == rob_compact_uop_might_bypass_REG; // @[rob.scala:210:29, :341:{47,58}]
reg [4:0] rob_compact_uop_bypassed_REG; // @[rob.scala:343:29]
wire _rob_compact_uop_bypassed_T = rob_head == rob_compact_uop_bypassed_REG; // @[rob.scala:210:29, :343:{18,29}]
reg rob_compact_uop_bypassed_REG_1; // @[rob.scala:343:50]
wire _rob_compact_uop_bypassed_T_1 = _rob_compact_uop_bypassed_T & rob_compact_uop_bypassed_REG_1; // @[rob.scala:343:{18,40,50}]
reg [29:0] rob_compact_uop_bypassed_REG_2; // @[rob.scala:344:14]
reg [4:0] rob_compact_uop_bypassed_r; // @[rob.scala:345:37]
reg [4:0] rob_compact_uop_bypassed_r_1; // @[rob.scala:345:37]
wire _rob_compact_uop_bypassed_T_2 = rob_head == rob_compact_uop_bypassed_r_1; // @[rob.scala:210:29, :345:{20,37}]
reg rob_compact_uop_bypassed_r_2; // @[rob.scala:345:67]
reg rob_compact_uop_bypassed_r_3; // @[rob.scala:345:67]
wire _rob_compact_uop_bypassed_T_3 = _rob_compact_uop_bypassed_T_2 & rob_compact_uop_bypassed_r_3; // @[rob.scala:345:{20,51,67}]
reg [29:0] rob_compact_uop_bypassed_r_4; // @[rob.scala:346:22]
reg [29:0] rob_compact_uop_bypassed_r_5; // @[rob.scala:346:22]
wire [29:0] _rob_compact_uop_bypassed_T_4 = _rob_compact_uop_bypassed_T_3 ? rob_compact_uop_bypassed_r_5 : _rob_compact_uop_mem_R0_data[29:0]; // @[rob.scala:337:40, :345:{10,51}, :346:22]
wire [29:0] _rob_compact_uop_bypassed_T_5 = _rob_compact_uop_bypassed_T_1 ? rob_compact_uop_bypassed_REG_2 : _rob_compact_uop_bypassed_T_4; // @[rob.scala:343:{8,40}, :344:14, :345:10]
wire [29:0] _rob_compact_uop_bypassed_WIRE = _rob_compact_uop_bypassed_T_5; // @[rob.scala:343:8, :349:15]
wire _rob_compact_uop_bypassed_T_13; // @[rob.scala:349:15]
wire [4:0] _rob_compact_uop_bypassed_T_12; // @[rob.scala:349:15]
assign io_commit_uops_0_out_is_fencei = rob_compact_uop_bypassed_0_is_fencei; // @[rob.scala:313:23, :349:15]
wire _rob_compact_uop_bypassed_T_11; // @[rob.scala:349:15]
assign io_commit_uops_0_out_ftq_idx = rob_compact_uop_bypassed_0_ftq_idx; // @[rob.scala:313:23, :349:15]
wire _rob_compact_uop_bypassed_T_10; // @[rob.scala:349:15]
assign io_commit_uops_0_out_uses_ldq = rob_compact_uop_bypassed_0_uses_ldq; // @[rob.scala:313:23, :349:15]
wire [1:0] _rob_compact_uop_bypassed_T_9; // @[rob.scala:349:15]
assign io_commit_uops_0_out_uses_stq = rob_compact_uop_bypassed_0_uses_stq; // @[rob.scala:313:23, :349:15]
wire [5:0] _rob_compact_uop_bypassed_T_8; // @[rob.scala:349:15]
assign io_commit_uops_0_out_dst_rtype = rob_compact_uop_bypassed_0_dst_rtype; // @[rob.scala:313:23, :349:15]
wire [6:0] _rob_compact_uop_bypassed_T_7; // @[rob.scala:349:15]
assign io_commit_uops_0_out_ldst = rob_compact_uop_bypassed_0_ldst; // @[rob.scala:313:23, :349:15]
wire [6:0] _rob_compact_uop_bypassed_T_6; // @[rob.scala:349:15]
assign io_commit_uops_0_out_pdst = rob_compact_uop_bypassed_0_pdst; // @[rob.scala:313:23, :349:15]
wire [6:0] rob_compact_uop_bypassed_0_stale_pdst; // @[rob.scala:349:15]
assign io_commit_uops_0_out_stale_pdst = rob_compact_uop_bypassed_0_stale_pdst; // @[rob.scala:313:23, :349:15]
assign _rob_compact_uop_bypassed_T_6 = _rob_compact_uop_bypassed_WIRE[6:0]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_stale_pdst = _rob_compact_uop_bypassed_T_6; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_7 = _rob_compact_uop_bypassed_WIRE[13:7]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_pdst = _rob_compact_uop_bypassed_T_7; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_8 = _rob_compact_uop_bypassed_WIRE[19:14]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_ldst = _rob_compact_uop_bypassed_T_8; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_9 = _rob_compact_uop_bypassed_WIRE[21:20]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_dst_rtype = _rob_compact_uop_bypassed_T_9; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_10 = _rob_compact_uop_bypassed_WIRE[22]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_uses_stq = _rob_compact_uop_bypassed_T_10; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_11 = _rob_compact_uop_bypassed_WIRE[23]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_uses_ldq = _rob_compact_uop_bypassed_T_11; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_12 = _rob_compact_uop_bypassed_WIRE[28:24]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_ftq_idx = _rob_compact_uop_bypassed_T_12; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_13 = _rob_compact_uop_bypassed_WIRE[29]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_0_is_fencei = _rob_compact_uop_bypassed_T_13; // @[rob.scala:349:15]
reg [4:0] rob_compact_uop_bypassed_REG_3; // @[rob.scala:343:29]
wire _rob_compact_uop_bypassed_T_14 = rob_head == rob_compact_uop_bypassed_REG_3; // @[rob.scala:210:29, :343:{18,29}]
reg rob_compact_uop_bypassed_REG_4; // @[rob.scala:343:50]
wire _rob_compact_uop_bypassed_T_15 = _rob_compact_uop_bypassed_T_14 & rob_compact_uop_bypassed_REG_4; // @[rob.scala:343:{18,40,50}]
reg [29:0] rob_compact_uop_bypassed_REG_5; // @[rob.scala:344:14]
reg [4:0] rob_compact_uop_bypassed_r_6; // @[rob.scala:345:37]
reg [4:0] rob_compact_uop_bypassed_r_7; // @[rob.scala:345:37]
wire _rob_compact_uop_bypassed_T_16 = rob_head == rob_compact_uop_bypassed_r_7; // @[rob.scala:210:29, :345:{20,37}]
reg rob_compact_uop_bypassed_r_8; // @[rob.scala:345:67]
reg rob_compact_uop_bypassed_r_9; // @[rob.scala:345:67]
wire _rob_compact_uop_bypassed_T_17 = _rob_compact_uop_bypassed_T_16 & rob_compact_uop_bypassed_r_9; // @[rob.scala:345:{20,51,67}]
reg [29:0] rob_compact_uop_bypassed_r_10; // @[rob.scala:346:22]
reg [29:0] rob_compact_uop_bypassed_r_11; // @[rob.scala:346:22]
wire [29:0] _rob_compact_uop_bypassed_T_18 = _rob_compact_uop_bypassed_T_17 ? rob_compact_uop_bypassed_r_11 : _rob_compact_uop_mem_R0_data[59:30]; // @[rob.scala:337:40, :345:{10,51}, :346:22]
wire [29:0] _rob_compact_uop_bypassed_T_19 = _rob_compact_uop_bypassed_T_15 ? rob_compact_uop_bypassed_REG_5 : _rob_compact_uop_bypassed_T_18; // @[rob.scala:343:{8,40}, :344:14, :345:10]
wire [29:0] _rob_compact_uop_bypassed_WIRE_1 = _rob_compact_uop_bypassed_T_19; // @[rob.scala:343:8, :349:15]
wire _rob_compact_uop_bypassed_T_27; // @[rob.scala:349:15]
wire [4:0] _rob_compact_uop_bypassed_T_26; // @[rob.scala:349:15]
assign io_commit_uops_1_out_is_fencei = rob_compact_uop_bypassed_1_is_fencei; // @[rob.scala:313:23, :349:15]
wire _rob_compact_uop_bypassed_T_25; // @[rob.scala:349:15]
assign io_commit_uops_1_out_ftq_idx = rob_compact_uop_bypassed_1_ftq_idx; // @[rob.scala:313:23, :349:15]
wire _rob_compact_uop_bypassed_T_24; // @[rob.scala:349:15]
assign io_commit_uops_1_out_uses_ldq = rob_compact_uop_bypassed_1_uses_ldq; // @[rob.scala:313:23, :349:15]
wire [1:0] _rob_compact_uop_bypassed_T_23; // @[rob.scala:349:15]
assign io_commit_uops_1_out_uses_stq = rob_compact_uop_bypassed_1_uses_stq; // @[rob.scala:313:23, :349:15]
wire [5:0] _rob_compact_uop_bypassed_T_22; // @[rob.scala:349:15]
assign io_commit_uops_1_out_dst_rtype = rob_compact_uop_bypassed_1_dst_rtype; // @[rob.scala:313:23, :349:15]
wire [6:0] _rob_compact_uop_bypassed_T_21; // @[rob.scala:349:15]
assign io_commit_uops_1_out_ldst = rob_compact_uop_bypassed_1_ldst; // @[rob.scala:313:23, :349:15]
wire [6:0] _rob_compact_uop_bypassed_T_20; // @[rob.scala:349:15]
assign io_commit_uops_1_out_pdst = rob_compact_uop_bypassed_1_pdst; // @[rob.scala:313:23, :349:15]
wire [6:0] rob_compact_uop_bypassed_1_stale_pdst; // @[rob.scala:349:15]
assign io_commit_uops_1_out_stale_pdst = rob_compact_uop_bypassed_1_stale_pdst; // @[rob.scala:313:23, :349:15]
assign _rob_compact_uop_bypassed_T_20 = _rob_compact_uop_bypassed_WIRE_1[6:0]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_stale_pdst = _rob_compact_uop_bypassed_T_20; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_21 = _rob_compact_uop_bypassed_WIRE_1[13:7]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_pdst = _rob_compact_uop_bypassed_T_21; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_22 = _rob_compact_uop_bypassed_WIRE_1[19:14]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_ldst = _rob_compact_uop_bypassed_T_22; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_23 = _rob_compact_uop_bypassed_WIRE_1[21:20]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_dst_rtype = _rob_compact_uop_bypassed_T_23; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_24 = _rob_compact_uop_bypassed_WIRE_1[22]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_uses_stq = _rob_compact_uop_bypassed_T_24; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_25 = _rob_compact_uop_bypassed_WIRE_1[23]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_uses_ldq = _rob_compact_uop_bypassed_T_25; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_26 = _rob_compact_uop_bypassed_WIRE_1[28:24]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_ftq_idx = _rob_compact_uop_bypassed_T_26; // @[rob.scala:349:15]
assign _rob_compact_uop_bypassed_T_27 = _rob_compact_uop_bypassed_WIRE_1[29]; // @[rob.scala:349:15]
assign rob_compact_uop_bypassed_1_is_fencei = _rob_compact_uop_bypassed_T_27; // @[rob.scala:349:15]
reg rob_val_0; // @[rob.scala:358:32]
reg rob_val_1; // @[rob.scala:358:32]
reg rob_val_2; // @[rob.scala:358:32]
reg rob_val_3; // @[rob.scala:358:32]
reg rob_val_4; // @[rob.scala:358:32]
reg rob_val_5; // @[rob.scala:358:32]
reg rob_val_6; // @[rob.scala:358:32]
reg rob_val_7; // @[rob.scala:358:32]
reg rob_val_8; // @[rob.scala:358:32]
reg rob_val_9; // @[rob.scala:358:32]
reg rob_val_10; // @[rob.scala:358:32]
reg rob_val_11; // @[rob.scala:358:32]
reg rob_val_12; // @[rob.scala:358:32]
reg rob_val_13; // @[rob.scala:358:32]
reg rob_val_14; // @[rob.scala:358:32]
reg rob_val_15; // @[rob.scala:358:32]
reg rob_val_16; // @[rob.scala:358:32]
reg rob_val_17; // @[rob.scala:358:32]
reg rob_val_18; // @[rob.scala:358:32]
reg rob_val_19; // @[rob.scala:358:32]
reg rob_val_20; // @[rob.scala:358:32]
reg rob_val_21; // @[rob.scala:358:32]
reg rob_val_22; // @[rob.scala:358:32]
reg rob_val_23; // @[rob.scala:358:32]
reg rob_val_24; // @[rob.scala:358:32]
reg rob_val_25; // @[rob.scala:358:32]
reg rob_val_26; // @[rob.scala:358:32]
reg rob_val_27; // @[rob.scala:358:32]
reg rob_val_28; // @[rob.scala:358:32]
reg rob_val_29; // @[rob.scala:358:32]
reg rob_val_30; // @[rob.scala:358:32]
reg rob_val_31; // @[rob.scala:358:32]
reg rob_bsy_0; // @[rob.scala:359:28]
reg rob_bsy_1; // @[rob.scala:359:28]
reg rob_bsy_2; // @[rob.scala:359:28]
reg rob_bsy_3; // @[rob.scala:359:28]
reg rob_bsy_4; // @[rob.scala:359:28]
reg rob_bsy_5; // @[rob.scala:359:28]
reg rob_bsy_6; // @[rob.scala:359:28]
reg rob_bsy_7; // @[rob.scala:359:28]
reg rob_bsy_8; // @[rob.scala:359:28]
reg rob_bsy_9; // @[rob.scala:359:28]
reg rob_bsy_10; // @[rob.scala:359:28]
reg rob_bsy_11; // @[rob.scala:359:28]
reg rob_bsy_12; // @[rob.scala:359:28]
reg rob_bsy_13; // @[rob.scala:359:28]
reg rob_bsy_14; // @[rob.scala:359:28]
reg rob_bsy_15; // @[rob.scala:359:28]
reg rob_bsy_16; // @[rob.scala:359:28]
reg rob_bsy_17; // @[rob.scala:359:28]
reg rob_bsy_18; // @[rob.scala:359:28]
reg rob_bsy_19; // @[rob.scala:359:28]
reg rob_bsy_20; // @[rob.scala:359:28]
reg rob_bsy_21; // @[rob.scala:359:28]
reg rob_bsy_22; // @[rob.scala:359:28]
reg rob_bsy_23; // @[rob.scala:359:28]
reg rob_bsy_24; // @[rob.scala:359:28]
reg rob_bsy_25; // @[rob.scala:359:28]
reg rob_bsy_26; // @[rob.scala:359:28]
reg rob_bsy_27; // @[rob.scala:359:28]
reg rob_bsy_28; // @[rob.scala:359:28]
reg rob_bsy_29; // @[rob.scala:359:28]
reg rob_bsy_30; // @[rob.scala:359:28]
reg rob_bsy_31; // @[rob.scala:359:28]
reg rob_unsafe_0; // @[rob.scala:360:28]
reg rob_unsafe_1; // @[rob.scala:360:28]
reg rob_unsafe_2; // @[rob.scala:360:28]
reg rob_unsafe_3; // @[rob.scala:360:28]
reg rob_unsafe_4; // @[rob.scala:360:28]
reg rob_unsafe_5; // @[rob.scala:360:28]
reg rob_unsafe_6; // @[rob.scala:360:28]
reg rob_unsafe_7; // @[rob.scala:360:28]
reg rob_unsafe_8; // @[rob.scala:360:28]
reg rob_unsafe_9; // @[rob.scala:360:28]
reg rob_unsafe_10; // @[rob.scala:360:28]
reg rob_unsafe_11; // @[rob.scala:360:28]
reg rob_unsafe_12; // @[rob.scala:360:28]
reg rob_unsafe_13; // @[rob.scala:360:28]
reg rob_unsafe_14; // @[rob.scala:360:28]
reg rob_unsafe_15; // @[rob.scala:360:28]
reg rob_unsafe_16; // @[rob.scala:360:28]
reg rob_unsafe_17; // @[rob.scala:360:28]
reg rob_unsafe_18; // @[rob.scala:360:28]
reg rob_unsafe_19; // @[rob.scala:360:28]
reg rob_unsafe_20; // @[rob.scala:360:28]
reg rob_unsafe_21; // @[rob.scala:360:28]
reg rob_unsafe_22; // @[rob.scala:360:28]
reg rob_unsafe_23; // @[rob.scala:360:28]
reg rob_unsafe_24; // @[rob.scala:360:28]
reg rob_unsafe_25; // @[rob.scala:360:28]
reg rob_unsafe_26; // @[rob.scala:360:28]
reg rob_unsafe_27; // @[rob.scala:360:28]
reg rob_unsafe_28; // @[rob.scala:360:28]
reg rob_unsafe_29; // @[rob.scala:360:28]
reg rob_unsafe_30; // @[rob.scala:360:28]
reg rob_unsafe_31; // @[rob.scala:360:28]
reg [31:0] rob_uop_0_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_0_debug_inst; // @[rob.scala:361:28]
reg rob_uop_0_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_0_debug_pc; // @[rob.scala:361:28]
reg rob_uop_0_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_0_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_0_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_0_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_0_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_0_iw_issued; // @[rob.scala:361:28]
reg rob_uop_0_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_0_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_0_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_0_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_0_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_0_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_0_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_0_br_type; // @[rob.scala:361:28]
reg rob_uop_0_is_sfb; // @[rob.scala:361:28]
reg rob_uop_0_is_fence; // @[rob.scala:361:28]
reg rob_uop_0_is_fencei; // @[rob.scala:361:28]
reg rob_uop_0_is_sfence; // @[rob.scala:361:28]
reg rob_uop_0_is_amo; // @[rob.scala:361:28]
reg rob_uop_0_is_eret; // @[rob.scala:361:28]
reg rob_uop_0_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_0_is_rocc; // @[rob.scala:361:28]
reg rob_uop_0_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_0_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_0_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_pc_lob; // @[rob.scala:361:28]
reg rob_uop_0_taken; // @[rob.scala:361:28]
reg rob_uop_0_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_0_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_0_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_op2_sel; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_0_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_0_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_0_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_0_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_0_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_0_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_0_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_0_ppred; // @[rob.scala:361:28]
reg rob_uop_0_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_0_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_0_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_0_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_0_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_0_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_0_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_0_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_mem_size; // @[rob.scala:361:28]
reg rob_uop_0_mem_signed; // @[rob.scala:361:28]
reg rob_uop_0_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_0_uses_stq; // @[rob.scala:361:28]
reg rob_uop_0_is_unique; // @[rob.scala:361:28]
reg rob_uop_0_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_0_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_0_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_0_frs3_en; // @[rob.scala:361:28]
reg rob_uop_0_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_0_fcn_op; // @[rob.scala:361:28]
reg rob_uop_0_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_0_fp_typ; // @[rob.scala:361:28]
reg rob_uop_0_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_0_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_0_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_0_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_0_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_0_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_br_type; // @[rob.scala:361:28]
reg rob_uop_1_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_taken; // @[rob.scala:361:28]
reg rob_uop_1_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_ppred; // @[rob.scala:361:28]
reg rob_uop_1_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_2_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_2_debug_inst; // @[rob.scala:361:28]
reg rob_uop_2_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_2_debug_pc; // @[rob.scala:361:28]
reg rob_uop_2_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_2_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_2_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_2_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_2_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_2_iw_issued; // @[rob.scala:361:28]
reg rob_uop_2_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_2_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_2_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_2_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_2_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_2_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_2_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_2_br_type; // @[rob.scala:361:28]
reg rob_uop_2_is_sfb; // @[rob.scala:361:28]
reg rob_uop_2_is_fence; // @[rob.scala:361:28]
reg rob_uop_2_is_fencei; // @[rob.scala:361:28]
reg rob_uop_2_is_sfence; // @[rob.scala:361:28]
reg rob_uop_2_is_amo; // @[rob.scala:361:28]
reg rob_uop_2_is_eret; // @[rob.scala:361:28]
reg rob_uop_2_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_2_is_rocc; // @[rob.scala:361:28]
reg rob_uop_2_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_2_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_2_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_pc_lob; // @[rob.scala:361:28]
reg rob_uop_2_taken; // @[rob.scala:361:28]
reg rob_uop_2_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_2_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_2_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_op2_sel; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_2_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_2_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_2_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_2_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_2_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_2_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_2_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_2_ppred; // @[rob.scala:361:28]
reg rob_uop_2_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_2_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_2_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_2_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_2_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_2_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_2_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_2_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_mem_size; // @[rob.scala:361:28]
reg rob_uop_2_mem_signed; // @[rob.scala:361:28]
reg rob_uop_2_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_2_uses_stq; // @[rob.scala:361:28]
reg rob_uop_2_is_unique; // @[rob.scala:361:28]
reg rob_uop_2_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_2_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_2_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_2_frs3_en; // @[rob.scala:361:28]
reg rob_uop_2_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_2_fcn_op; // @[rob.scala:361:28]
reg rob_uop_2_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_2_fp_typ; // @[rob.scala:361:28]
reg rob_uop_2_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_2_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_2_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_2_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_2_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_2_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_3_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_3_debug_inst; // @[rob.scala:361:28]
reg rob_uop_3_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_3_debug_pc; // @[rob.scala:361:28]
reg rob_uop_3_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_3_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_3_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_3_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_3_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_3_iw_issued; // @[rob.scala:361:28]
reg rob_uop_3_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_3_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_3_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_3_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_3_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_3_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_3_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_3_br_type; // @[rob.scala:361:28]
reg rob_uop_3_is_sfb; // @[rob.scala:361:28]
reg rob_uop_3_is_fence; // @[rob.scala:361:28]
reg rob_uop_3_is_fencei; // @[rob.scala:361:28]
reg rob_uop_3_is_sfence; // @[rob.scala:361:28]
reg rob_uop_3_is_amo; // @[rob.scala:361:28]
reg rob_uop_3_is_eret; // @[rob.scala:361:28]
reg rob_uop_3_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_3_is_rocc; // @[rob.scala:361:28]
reg rob_uop_3_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_3_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_3_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_pc_lob; // @[rob.scala:361:28]
reg rob_uop_3_taken; // @[rob.scala:361:28]
reg rob_uop_3_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_3_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_3_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_op2_sel; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_3_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_3_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_3_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_3_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_3_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_3_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_3_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_3_ppred; // @[rob.scala:361:28]
reg rob_uop_3_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_3_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_3_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_3_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_3_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_3_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_3_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_3_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_mem_size; // @[rob.scala:361:28]
reg rob_uop_3_mem_signed; // @[rob.scala:361:28]
reg rob_uop_3_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_3_uses_stq; // @[rob.scala:361:28]
reg rob_uop_3_is_unique; // @[rob.scala:361:28]
reg rob_uop_3_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_3_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_3_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_3_frs3_en; // @[rob.scala:361:28]
reg rob_uop_3_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_3_fcn_op; // @[rob.scala:361:28]
reg rob_uop_3_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_3_fp_typ; // @[rob.scala:361:28]
reg rob_uop_3_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_3_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_3_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_3_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_3_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_3_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_4_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_4_debug_inst; // @[rob.scala:361:28]
reg rob_uop_4_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_4_debug_pc; // @[rob.scala:361:28]
reg rob_uop_4_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_4_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_4_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_4_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_4_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_4_iw_issued; // @[rob.scala:361:28]
reg rob_uop_4_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_4_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_4_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_4_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_4_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_4_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_4_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_4_br_type; // @[rob.scala:361:28]
reg rob_uop_4_is_sfb; // @[rob.scala:361:28]
reg rob_uop_4_is_fence; // @[rob.scala:361:28]
reg rob_uop_4_is_fencei; // @[rob.scala:361:28]
reg rob_uop_4_is_sfence; // @[rob.scala:361:28]
reg rob_uop_4_is_amo; // @[rob.scala:361:28]
reg rob_uop_4_is_eret; // @[rob.scala:361:28]
reg rob_uop_4_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_4_is_rocc; // @[rob.scala:361:28]
reg rob_uop_4_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_4_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_4_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_pc_lob; // @[rob.scala:361:28]
reg rob_uop_4_taken; // @[rob.scala:361:28]
reg rob_uop_4_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_4_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_4_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_op2_sel; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_4_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_4_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_4_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_4_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_4_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_4_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_4_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_4_ppred; // @[rob.scala:361:28]
reg rob_uop_4_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_4_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_4_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_4_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_4_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_4_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_4_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_4_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_mem_size; // @[rob.scala:361:28]
reg rob_uop_4_mem_signed; // @[rob.scala:361:28]
reg rob_uop_4_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_4_uses_stq; // @[rob.scala:361:28]
reg rob_uop_4_is_unique; // @[rob.scala:361:28]
reg rob_uop_4_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_4_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_4_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_4_frs3_en; // @[rob.scala:361:28]
reg rob_uop_4_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_4_fcn_op; // @[rob.scala:361:28]
reg rob_uop_4_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_4_fp_typ; // @[rob.scala:361:28]
reg rob_uop_4_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_4_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_4_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_4_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_4_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_4_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_5_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_5_debug_inst; // @[rob.scala:361:28]
reg rob_uop_5_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_5_debug_pc; // @[rob.scala:361:28]
reg rob_uop_5_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_5_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_5_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_5_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_5_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_5_iw_issued; // @[rob.scala:361:28]
reg rob_uop_5_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_5_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_5_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_5_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_5_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_5_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_5_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_5_br_type; // @[rob.scala:361:28]
reg rob_uop_5_is_sfb; // @[rob.scala:361:28]
reg rob_uop_5_is_fence; // @[rob.scala:361:28]
reg rob_uop_5_is_fencei; // @[rob.scala:361:28]
reg rob_uop_5_is_sfence; // @[rob.scala:361:28]
reg rob_uop_5_is_amo; // @[rob.scala:361:28]
reg rob_uop_5_is_eret; // @[rob.scala:361:28]
reg rob_uop_5_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_5_is_rocc; // @[rob.scala:361:28]
reg rob_uop_5_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_5_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_5_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_pc_lob; // @[rob.scala:361:28]
reg rob_uop_5_taken; // @[rob.scala:361:28]
reg rob_uop_5_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_5_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_5_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_op2_sel; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_5_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_5_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_5_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_5_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_5_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_5_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_5_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_5_ppred; // @[rob.scala:361:28]
reg rob_uop_5_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_5_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_5_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_5_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_5_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_5_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_5_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_5_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_mem_size; // @[rob.scala:361:28]
reg rob_uop_5_mem_signed; // @[rob.scala:361:28]
reg rob_uop_5_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_5_uses_stq; // @[rob.scala:361:28]
reg rob_uop_5_is_unique; // @[rob.scala:361:28]
reg rob_uop_5_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_5_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_5_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_5_frs3_en; // @[rob.scala:361:28]
reg rob_uop_5_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_5_fcn_op; // @[rob.scala:361:28]
reg rob_uop_5_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_5_fp_typ; // @[rob.scala:361:28]
reg rob_uop_5_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_5_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_5_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_5_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_5_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_5_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_6_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_6_debug_inst; // @[rob.scala:361:28]
reg rob_uop_6_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_6_debug_pc; // @[rob.scala:361:28]
reg rob_uop_6_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_6_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_6_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_6_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_6_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_6_iw_issued; // @[rob.scala:361:28]
reg rob_uop_6_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_6_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_6_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_6_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_6_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_6_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_6_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_6_br_type; // @[rob.scala:361:28]
reg rob_uop_6_is_sfb; // @[rob.scala:361:28]
reg rob_uop_6_is_fence; // @[rob.scala:361:28]
reg rob_uop_6_is_fencei; // @[rob.scala:361:28]
reg rob_uop_6_is_sfence; // @[rob.scala:361:28]
reg rob_uop_6_is_amo; // @[rob.scala:361:28]
reg rob_uop_6_is_eret; // @[rob.scala:361:28]
reg rob_uop_6_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_6_is_rocc; // @[rob.scala:361:28]
reg rob_uop_6_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_6_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_6_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_pc_lob; // @[rob.scala:361:28]
reg rob_uop_6_taken; // @[rob.scala:361:28]
reg rob_uop_6_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_6_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_6_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_op2_sel; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_6_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_6_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_6_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_6_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_6_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_6_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_6_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_6_ppred; // @[rob.scala:361:28]
reg rob_uop_6_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_6_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_6_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_6_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_6_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_6_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_6_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_6_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_mem_size; // @[rob.scala:361:28]
reg rob_uop_6_mem_signed; // @[rob.scala:361:28]
reg rob_uop_6_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_6_uses_stq; // @[rob.scala:361:28]
reg rob_uop_6_is_unique; // @[rob.scala:361:28]
reg rob_uop_6_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_6_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_6_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_6_frs3_en; // @[rob.scala:361:28]
reg rob_uop_6_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_6_fcn_op; // @[rob.scala:361:28]
reg rob_uop_6_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_6_fp_typ; // @[rob.scala:361:28]
reg rob_uop_6_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_6_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_6_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_6_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_6_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_6_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_7_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_7_debug_inst; // @[rob.scala:361:28]
reg rob_uop_7_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_7_debug_pc; // @[rob.scala:361:28]
reg rob_uop_7_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_7_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_7_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_7_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_7_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_7_iw_issued; // @[rob.scala:361:28]
reg rob_uop_7_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_7_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_7_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_7_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_7_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_7_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_7_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_7_br_type; // @[rob.scala:361:28]
reg rob_uop_7_is_sfb; // @[rob.scala:361:28]
reg rob_uop_7_is_fence; // @[rob.scala:361:28]
reg rob_uop_7_is_fencei; // @[rob.scala:361:28]
reg rob_uop_7_is_sfence; // @[rob.scala:361:28]
reg rob_uop_7_is_amo; // @[rob.scala:361:28]
reg rob_uop_7_is_eret; // @[rob.scala:361:28]
reg rob_uop_7_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_7_is_rocc; // @[rob.scala:361:28]
reg rob_uop_7_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_7_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_7_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_pc_lob; // @[rob.scala:361:28]
reg rob_uop_7_taken; // @[rob.scala:361:28]
reg rob_uop_7_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_7_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_7_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_op2_sel; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_7_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_7_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_7_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_7_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_7_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_7_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_7_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_7_ppred; // @[rob.scala:361:28]
reg rob_uop_7_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_7_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_7_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_7_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_7_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_7_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_7_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_7_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_mem_size; // @[rob.scala:361:28]
reg rob_uop_7_mem_signed; // @[rob.scala:361:28]
reg rob_uop_7_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_7_uses_stq; // @[rob.scala:361:28]
reg rob_uop_7_is_unique; // @[rob.scala:361:28]
reg rob_uop_7_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_7_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_7_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_7_frs3_en; // @[rob.scala:361:28]
reg rob_uop_7_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_7_fcn_op; // @[rob.scala:361:28]
reg rob_uop_7_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_7_fp_typ; // @[rob.scala:361:28]
reg rob_uop_7_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_7_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_7_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_7_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_7_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_7_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_8_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_8_debug_inst; // @[rob.scala:361:28]
reg rob_uop_8_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_8_debug_pc; // @[rob.scala:361:28]
reg rob_uop_8_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_8_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_8_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_8_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_8_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_8_iw_issued; // @[rob.scala:361:28]
reg rob_uop_8_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_8_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_8_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_8_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_8_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_8_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_8_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_8_br_type; // @[rob.scala:361:28]
reg rob_uop_8_is_sfb; // @[rob.scala:361:28]
reg rob_uop_8_is_fence; // @[rob.scala:361:28]
reg rob_uop_8_is_fencei; // @[rob.scala:361:28]
reg rob_uop_8_is_sfence; // @[rob.scala:361:28]
reg rob_uop_8_is_amo; // @[rob.scala:361:28]
reg rob_uop_8_is_eret; // @[rob.scala:361:28]
reg rob_uop_8_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_8_is_rocc; // @[rob.scala:361:28]
reg rob_uop_8_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_8_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_8_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_pc_lob; // @[rob.scala:361:28]
reg rob_uop_8_taken; // @[rob.scala:361:28]
reg rob_uop_8_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_8_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_8_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_op2_sel; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_8_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_8_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_8_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_8_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_8_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_8_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_8_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_8_ppred; // @[rob.scala:361:28]
reg rob_uop_8_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_8_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_8_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_8_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_8_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_8_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_8_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_8_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_mem_size; // @[rob.scala:361:28]
reg rob_uop_8_mem_signed; // @[rob.scala:361:28]
reg rob_uop_8_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_8_uses_stq; // @[rob.scala:361:28]
reg rob_uop_8_is_unique; // @[rob.scala:361:28]
reg rob_uop_8_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_8_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_8_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_8_frs3_en; // @[rob.scala:361:28]
reg rob_uop_8_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_8_fcn_op; // @[rob.scala:361:28]
reg rob_uop_8_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_8_fp_typ; // @[rob.scala:361:28]
reg rob_uop_8_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_8_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_8_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_8_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_8_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_8_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_9_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_9_debug_inst; // @[rob.scala:361:28]
reg rob_uop_9_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_9_debug_pc; // @[rob.scala:361:28]
reg rob_uop_9_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_9_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_9_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_9_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_9_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_9_iw_issued; // @[rob.scala:361:28]
reg rob_uop_9_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_9_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_9_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_9_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_9_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_9_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_9_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_9_br_type; // @[rob.scala:361:28]
reg rob_uop_9_is_sfb; // @[rob.scala:361:28]
reg rob_uop_9_is_fence; // @[rob.scala:361:28]
reg rob_uop_9_is_fencei; // @[rob.scala:361:28]
reg rob_uop_9_is_sfence; // @[rob.scala:361:28]
reg rob_uop_9_is_amo; // @[rob.scala:361:28]
reg rob_uop_9_is_eret; // @[rob.scala:361:28]
reg rob_uop_9_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_9_is_rocc; // @[rob.scala:361:28]
reg rob_uop_9_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_9_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_9_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_pc_lob; // @[rob.scala:361:28]
reg rob_uop_9_taken; // @[rob.scala:361:28]
reg rob_uop_9_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_9_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_9_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_op2_sel; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_9_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_9_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_9_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_9_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_9_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_9_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_9_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_9_ppred; // @[rob.scala:361:28]
reg rob_uop_9_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_9_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_9_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_9_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_9_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_9_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_9_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_9_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_mem_size; // @[rob.scala:361:28]
reg rob_uop_9_mem_signed; // @[rob.scala:361:28]
reg rob_uop_9_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_9_uses_stq; // @[rob.scala:361:28]
reg rob_uop_9_is_unique; // @[rob.scala:361:28]
reg rob_uop_9_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_9_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_9_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_9_frs3_en; // @[rob.scala:361:28]
reg rob_uop_9_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_9_fcn_op; // @[rob.scala:361:28]
reg rob_uop_9_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_9_fp_typ; // @[rob.scala:361:28]
reg rob_uop_9_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_9_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_9_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_9_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_9_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_9_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_10_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_10_debug_inst; // @[rob.scala:361:28]
reg rob_uop_10_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_10_debug_pc; // @[rob.scala:361:28]
reg rob_uop_10_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_10_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_10_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_10_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_10_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_10_iw_issued; // @[rob.scala:361:28]
reg rob_uop_10_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_10_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_10_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_10_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_10_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_10_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_10_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_10_br_type; // @[rob.scala:361:28]
reg rob_uop_10_is_sfb; // @[rob.scala:361:28]
reg rob_uop_10_is_fence; // @[rob.scala:361:28]
reg rob_uop_10_is_fencei; // @[rob.scala:361:28]
reg rob_uop_10_is_sfence; // @[rob.scala:361:28]
reg rob_uop_10_is_amo; // @[rob.scala:361:28]
reg rob_uop_10_is_eret; // @[rob.scala:361:28]
reg rob_uop_10_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_10_is_rocc; // @[rob.scala:361:28]
reg rob_uop_10_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_10_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_10_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_pc_lob; // @[rob.scala:361:28]
reg rob_uop_10_taken; // @[rob.scala:361:28]
reg rob_uop_10_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_10_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_10_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_op2_sel; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_10_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_10_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_10_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_10_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_10_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_10_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_10_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_10_ppred; // @[rob.scala:361:28]
reg rob_uop_10_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_10_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_10_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_10_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_10_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_10_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_10_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_10_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_mem_size; // @[rob.scala:361:28]
reg rob_uop_10_mem_signed; // @[rob.scala:361:28]
reg rob_uop_10_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_10_uses_stq; // @[rob.scala:361:28]
reg rob_uop_10_is_unique; // @[rob.scala:361:28]
reg rob_uop_10_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_10_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_10_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_10_frs3_en; // @[rob.scala:361:28]
reg rob_uop_10_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_10_fcn_op; // @[rob.scala:361:28]
reg rob_uop_10_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_10_fp_typ; // @[rob.scala:361:28]
reg rob_uop_10_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_10_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_10_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_10_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_10_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_10_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_11_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_11_debug_inst; // @[rob.scala:361:28]
reg rob_uop_11_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_11_debug_pc; // @[rob.scala:361:28]
reg rob_uop_11_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_11_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_11_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_11_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_11_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_11_iw_issued; // @[rob.scala:361:28]
reg rob_uop_11_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_11_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_11_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_11_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_11_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_11_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_11_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_11_br_type; // @[rob.scala:361:28]
reg rob_uop_11_is_sfb; // @[rob.scala:361:28]
reg rob_uop_11_is_fence; // @[rob.scala:361:28]
reg rob_uop_11_is_fencei; // @[rob.scala:361:28]
reg rob_uop_11_is_sfence; // @[rob.scala:361:28]
reg rob_uop_11_is_amo; // @[rob.scala:361:28]
reg rob_uop_11_is_eret; // @[rob.scala:361:28]
reg rob_uop_11_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_11_is_rocc; // @[rob.scala:361:28]
reg rob_uop_11_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_11_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_11_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_pc_lob; // @[rob.scala:361:28]
reg rob_uop_11_taken; // @[rob.scala:361:28]
reg rob_uop_11_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_11_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_11_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_op2_sel; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_11_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_11_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_11_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_11_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_11_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_11_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_11_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_11_ppred; // @[rob.scala:361:28]
reg rob_uop_11_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_11_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_11_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_11_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_11_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_11_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_11_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_11_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_mem_size; // @[rob.scala:361:28]
reg rob_uop_11_mem_signed; // @[rob.scala:361:28]
reg rob_uop_11_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_11_uses_stq; // @[rob.scala:361:28]
reg rob_uop_11_is_unique; // @[rob.scala:361:28]
reg rob_uop_11_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_11_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_11_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_11_frs3_en; // @[rob.scala:361:28]
reg rob_uop_11_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_11_fcn_op; // @[rob.scala:361:28]
reg rob_uop_11_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_11_fp_typ; // @[rob.scala:361:28]
reg rob_uop_11_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_11_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_11_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_11_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_11_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_11_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_12_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_12_debug_inst; // @[rob.scala:361:28]
reg rob_uop_12_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_12_debug_pc; // @[rob.scala:361:28]
reg rob_uop_12_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_12_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_12_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_12_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_12_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_12_iw_issued; // @[rob.scala:361:28]
reg rob_uop_12_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_12_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_12_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_12_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_12_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_12_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_12_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_12_br_type; // @[rob.scala:361:28]
reg rob_uop_12_is_sfb; // @[rob.scala:361:28]
reg rob_uop_12_is_fence; // @[rob.scala:361:28]
reg rob_uop_12_is_fencei; // @[rob.scala:361:28]
reg rob_uop_12_is_sfence; // @[rob.scala:361:28]
reg rob_uop_12_is_amo; // @[rob.scala:361:28]
reg rob_uop_12_is_eret; // @[rob.scala:361:28]
reg rob_uop_12_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_12_is_rocc; // @[rob.scala:361:28]
reg rob_uop_12_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_12_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_12_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_pc_lob; // @[rob.scala:361:28]
reg rob_uop_12_taken; // @[rob.scala:361:28]
reg rob_uop_12_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_12_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_12_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_op2_sel; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_12_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_12_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_12_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_12_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_12_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_12_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_12_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_12_ppred; // @[rob.scala:361:28]
reg rob_uop_12_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_12_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_12_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_12_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_12_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_12_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_12_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_12_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_mem_size; // @[rob.scala:361:28]
reg rob_uop_12_mem_signed; // @[rob.scala:361:28]
reg rob_uop_12_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_12_uses_stq; // @[rob.scala:361:28]
reg rob_uop_12_is_unique; // @[rob.scala:361:28]
reg rob_uop_12_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_12_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_12_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_12_frs3_en; // @[rob.scala:361:28]
reg rob_uop_12_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_12_fcn_op; // @[rob.scala:361:28]
reg rob_uop_12_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_12_fp_typ; // @[rob.scala:361:28]
reg rob_uop_12_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_12_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_12_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_12_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_12_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_12_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_13_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_13_debug_inst; // @[rob.scala:361:28]
reg rob_uop_13_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_13_debug_pc; // @[rob.scala:361:28]
reg rob_uop_13_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_13_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_13_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_13_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_13_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_13_iw_issued; // @[rob.scala:361:28]
reg rob_uop_13_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_13_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_13_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_13_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_13_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_13_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_13_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_13_br_type; // @[rob.scala:361:28]
reg rob_uop_13_is_sfb; // @[rob.scala:361:28]
reg rob_uop_13_is_fence; // @[rob.scala:361:28]
reg rob_uop_13_is_fencei; // @[rob.scala:361:28]
reg rob_uop_13_is_sfence; // @[rob.scala:361:28]
reg rob_uop_13_is_amo; // @[rob.scala:361:28]
reg rob_uop_13_is_eret; // @[rob.scala:361:28]
reg rob_uop_13_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_13_is_rocc; // @[rob.scala:361:28]
reg rob_uop_13_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_13_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_13_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_pc_lob; // @[rob.scala:361:28]
reg rob_uop_13_taken; // @[rob.scala:361:28]
reg rob_uop_13_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_13_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_13_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_op2_sel; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_13_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_13_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_13_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_13_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_13_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_13_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_13_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_13_ppred; // @[rob.scala:361:28]
reg rob_uop_13_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_13_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_13_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_13_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_13_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_13_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_13_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_13_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_mem_size; // @[rob.scala:361:28]
reg rob_uop_13_mem_signed; // @[rob.scala:361:28]
reg rob_uop_13_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_13_uses_stq; // @[rob.scala:361:28]
reg rob_uop_13_is_unique; // @[rob.scala:361:28]
reg rob_uop_13_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_13_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_13_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_13_frs3_en; // @[rob.scala:361:28]
reg rob_uop_13_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_13_fcn_op; // @[rob.scala:361:28]
reg rob_uop_13_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_13_fp_typ; // @[rob.scala:361:28]
reg rob_uop_13_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_13_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_13_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_13_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_13_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_13_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_14_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_14_debug_inst; // @[rob.scala:361:28]
reg rob_uop_14_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_14_debug_pc; // @[rob.scala:361:28]
reg rob_uop_14_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_14_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_14_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_14_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_14_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_14_iw_issued; // @[rob.scala:361:28]
reg rob_uop_14_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_14_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_14_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_14_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_14_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_14_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_14_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_14_br_type; // @[rob.scala:361:28]
reg rob_uop_14_is_sfb; // @[rob.scala:361:28]
reg rob_uop_14_is_fence; // @[rob.scala:361:28]
reg rob_uop_14_is_fencei; // @[rob.scala:361:28]
reg rob_uop_14_is_sfence; // @[rob.scala:361:28]
reg rob_uop_14_is_amo; // @[rob.scala:361:28]
reg rob_uop_14_is_eret; // @[rob.scala:361:28]
reg rob_uop_14_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_14_is_rocc; // @[rob.scala:361:28]
reg rob_uop_14_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_14_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_14_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_pc_lob; // @[rob.scala:361:28]
reg rob_uop_14_taken; // @[rob.scala:361:28]
reg rob_uop_14_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_14_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_14_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_op2_sel; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_14_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_14_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_14_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_14_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_14_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_14_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_14_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_14_ppred; // @[rob.scala:361:28]
reg rob_uop_14_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_14_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_14_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_14_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_14_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_14_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_14_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_14_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_mem_size; // @[rob.scala:361:28]
reg rob_uop_14_mem_signed; // @[rob.scala:361:28]
reg rob_uop_14_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_14_uses_stq; // @[rob.scala:361:28]
reg rob_uop_14_is_unique; // @[rob.scala:361:28]
reg rob_uop_14_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_14_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_14_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_14_frs3_en; // @[rob.scala:361:28]
reg rob_uop_14_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_14_fcn_op; // @[rob.scala:361:28]
reg rob_uop_14_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_14_fp_typ; // @[rob.scala:361:28]
reg rob_uop_14_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_14_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_14_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_14_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_14_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_14_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_15_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_15_debug_inst; // @[rob.scala:361:28]
reg rob_uop_15_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_15_debug_pc; // @[rob.scala:361:28]
reg rob_uop_15_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_15_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_15_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_15_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_15_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_15_iw_issued; // @[rob.scala:361:28]
reg rob_uop_15_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_15_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_15_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_15_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_15_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_15_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_15_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_15_br_type; // @[rob.scala:361:28]
reg rob_uop_15_is_sfb; // @[rob.scala:361:28]
reg rob_uop_15_is_fence; // @[rob.scala:361:28]
reg rob_uop_15_is_fencei; // @[rob.scala:361:28]
reg rob_uop_15_is_sfence; // @[rob.scala:361:28]
reg rob_uop_15_is_amo; // @[rob.scala:361:28]
reg rob_uop_15_is_eret; // @[rob.scala:361:28]
reg rob_uop_15_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_15_is_rocc; // @[rob.scala:361:28]
reg rob_uop_15_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_15_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_15_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_pc_lob; // @[rob.scala:361:28]
reg rob_uop_15_taken; // @[rob.scala:361:28]
reg rob_uop_15_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_15_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_15_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_op2_sel; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_15_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_15_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_15_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_15_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_15_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_15_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_15_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_15_ppred; // @[rob.scala:361:28]
reg rob_uop_15_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_15_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_15_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_15_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_15_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_15_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_15_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_15_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_mem_size; // @[rob.scala:361:28]
reg rob_uop_15_mem_signed; // @[rob.scala:361:28]
reg rob_uop_15_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_15_uses_stq; // @[rob.scala:361:28]
reg rob_uop_15_is_unique; // @[rob.scala:361:28]
reg rob_uop_15_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_15_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_15_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_15_frs3_en; // @[rob.scala:361:28]
reg rob_uop_15_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_15_fcn_op; // @[rob.scala:361:28]
reg rob_uop_15_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_15_fp_typ; // @[rob.scala:361:28]
reg rob_uop_15_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_15_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_15_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_15_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_15_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_15_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_16_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_16_debug_inst; // @[rob.scala:361:28]
reg rob_uop_16_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_16_debug_pc; // @[rob.scala:361:28]
reg rob_uop_16_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_16_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_16_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_16_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_16_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_16_iw_issued; // @[rob.scala:361:28]
reg rob_uop_16_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_16_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_16_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_16_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_16_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_16_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_16_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_16_br_type; // @[rob.scala:361:28]
reg rob_uop_16_is_sfb; // @[rob.scala:361:28]
reg rob_uop_16_is_fence; // @[rob.scala:361:28]
reg rob_uop_16_is_fencei; // @[rob.scala:361:28]
reg rob_uop_16_is_sfence; // @[rob.scala:361:28]
reg rob_uop_16_is_amo; // @[rob.scala:361:28]
reg rob_uop_16_is_eret; // @[rob.scala:361:28]
reg rob_uop_16_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_16_is_rocc; // @[rob.scala:361:28]
reg rob_uop_16_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_16_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_16_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_pc_lob; // @[rob.scala:361:28]
reg rob_uop_16_taken; // @[rob.scala:361:28]
reg rob_uop_16_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_16_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_16_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_op2_sel; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_16_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_16_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_16_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_16_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_16_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_16_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_16_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_16_ppred; // @[rob.scala:361:28]
reg rob_uop_16_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_16_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_16_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_16_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_16_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_16_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_16_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_16_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_mem_size; // @[rob.scala:361:28]
reg rob_uop_16_mem_signed; // @[rob.scala:361:28]
reg rob_uop_16_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_16_uses_stq; // @[rob.scala:361:28]
reg rob_uop_16_is_unique; // @[rob.scala:361:28]
reg rob_uop_16_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_16_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_16_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_16_frs3_en; // @[rob.scala:361:28]
reg rob_uop_16_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_16_fcn_op; // @[rob.scala:361:28]
reg rob_uop_16_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_16_fp_typ; // @[rob.scala:361:28]
reg rob_uop_16_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_16_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_16_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_16_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_16_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_16_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_17_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_17_debug_inst; // @[rob.scala:361:28]
reg rob_uop_17_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_17_debug_pc; // @[rob.scala:361:28]
reg rob_uop_17_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_17_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_17_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_17_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_17_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_17_iw_issued; // @[rob.scala:361:28]
reg rob_uop_17_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_17_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_17_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_17_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_17_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_17_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_17_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_17_br_type; // @[rob.scala:361:28]
reg rob_uop_17_is_sfb; // @[rob.scala:361:28]
reg rob_uop_17_is_fence; // @[rob.scala:361:28]
reg rob_uop_17_is_fencei; // @[rob.scala:361:28]
reg rob_uop_17_is_sfence; // @[rob.scala:361:28]
reg rob_uop_17_is_amo; // @[rob.scala:361:28]
reg rob_uop_17_is_eret; // @[rob.scala:361:28]
reg rob_uop_17_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_17_is_rocc; // @[rob.scala:361:28]
reg rob_uop_17_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_17_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_17_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_pc_lob; // @[rob.scala:361:28]
reg rob_uop_17_taken; // @[rob.scala:361:28]
reg rob_uop_17_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_17_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_17_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_op2_sel; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_17_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_17_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_17_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_17_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_17_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_17_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_17_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_17_ppred; // @[rob.scala:361:28]
reg rob_uop_17_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_17_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_17_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_17_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_17_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_17_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_17_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_17_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_mem_size; // @[rob.scala:361:28]
reg rob_uop_17_mem_signed; // @[rob.scala:361:28]
reg rob_uop_17_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_17_uses_stq; // @[rob.scala:361:28]
reg rob_uop_17_is_unique; // @[rob.scala:361:28]
reg rob_uop_17_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_17_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_17_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_17_frs3_en; // @[rob.scala:361:28]
reg rob_uop_17_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_17_fcn_op; // @[rob.scala:361:28]
reg rob_uop_17_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_17_fp_typ; // @[rob.scala:361:28]
reg rob_uop_17_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_17_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_17_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_17_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_17_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_17_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_18_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_18_debug_inst; // @[rob.scala:361:28]
reg rob_uop_18_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_18_debug_pc; // @[rob.scala:361:28]
reg rob_uop_18_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_18_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_18_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_18_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_18_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_18_iw_issued; // @[rob.scala:361:28]
reg rob_uop_18_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_18_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_18_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_18_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_18_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_18_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_18_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_18_br_type; // @[rob.scala:361:28]
reg rob_uop_18_is_sfb; // @[rob.scala:361:28]
reg rob_uop_18_is_fence; // @[rob.scala:361:28]
reg rob_uop_18_is_fencei; // @[rob.scala:361:28]
reg rob_uop_18_is_sfence; // @[rob.scala:361:28]
reg rob_uop_18_is_amo; // @[rob.scala:361:28]
reg rob_uop_18_is_eret; // @[rob.scala:361:28]
reg rob_uop_18_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_18_is_rocc; // @[rob.scala:361:28]
reg rob_uop_18_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_18_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_18_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_pc_lob; // @[rob.scala:361:28]
reg rob_uop_18_taken; // @[rob.scala:361:28]
reg rob_uop_18_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_18_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_18_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_op2_sel; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_18_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_18_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_18_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_18_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_18_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_18_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_18_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_18_ppred; // @[rob.scala:361:28]
reg rob_uop_18_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_18_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_18_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_18_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_18_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_18_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_18_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_18_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_mem_size; // @[rob.scala:361:28]
reg rob_uop_18_mem_signed; // @[rob.scala:361:28]
reg rob_uop_18_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_18_uses_stq; // @[rob.scala:361:28]
reg rob_uop_18_is_unique; // @[rob.scala:361:28]
reg rob_uop_18_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_18_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_18_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_18_frs3_en; // @[rob.scala:361:28]
reg rob_uop_18_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_18_fcn_op; // @[rob.scala:361:28]
reg rob_uop_18_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_18_fp_typ; // @[rob.scala:361:28]
reg rob_uop_18_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_18_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_18_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_18_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_18_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_18_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_19_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_19_debug_inst; // @[rob.scala:361:28]
reg rob_uop_19_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_19_debug_pc; // @[rob.scala:361:28]
reg rob_uop_19_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_19_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_19_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_19_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_19_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_19_iw_issued; // @[rob.scala:361:28]
reg rob_uop_19_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_19_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_19_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_19_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_19_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_19_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_19_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_19_br_type; // @[rob.scala:361:28]
reg rob_uop_19_is_sfb; // @[rob.scala:361:28]
reg rob_uop_19_is_fence; // @[rob.scala:361:28]
reg rob_uop_19_is_fencei; // @[rob.scala:361:28]
reg rob_uop_19_is_sfence; // @[rob.scala:361:28]
reg rob_uop_19_is_amo; // @[rob.scala:361:28]
reg rob_uop_19_is_eret; // @[rob.scala:361:28]
reg rob_uop_19_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_19_is_rocc; // @[rob.scala:361:28]
reg rob_uop_19_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_19_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_19_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_pc_lob; // @[rob.scala:361:28]
reg rob_uop_19_taken; // @[rob.scala:361:28]
reg rob_uop_19_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_19_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_19_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_op2_sel; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_19_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_19_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_19_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_19_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_19_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_19_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_19_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_19_ppred; // @[rob.scala:361:28]
reg rob_uop_19_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_19_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_19_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_19_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_19_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_19_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_19_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_19_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_mem_size; // @[rob.scala:361:28]
reg rob_uop_19_mem_signed; // @[rob.scala:361:28]
reg rob_uop_19_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_19_uses_stq; // @[rob.scala:361:28]
reg rob_uop_19_is_unique; // @[rob.scala:361:28]
reg rob_uop_19_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_19_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_19_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_19_frs3_en; // @[rob.scala:361:28]
reg rob_uop_19_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_19_fcn_op; // @[rob.scala:361:28]
reg rob_uop_19_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_19_fp_typ; // @[rob.scala:361:28]
reg rob_uop_19_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_19_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_19_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_19_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_19_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_19_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_20_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_20_debug_inst; // @[rob.scala:361:28]
reg rob_uop_20_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_20_debug_pc; // @[rob.scala:361:28]
reg rob_uop_20_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_20_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_20_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_20_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_20_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_20_iw_issued; // @[rob.scala:361:28]
reg rob_uop_20_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_20_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_20_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_20_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_20_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_20_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_20_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_20_br_type; // @[rob.scala:361:28]
reg rob_uop_20_is_sfb; // @[rob.scala:361:28]
reg rob_uop_20_is_fence; // @[rob.scala:361:28]
reg rob_uop_20_is_fencei; // @[rob.scala:361:28]
reg rob_uop_20_is_sfence; // @[rob.scala:361:28]
reg rob_uop_20_is_amo; // @[rob.scala:361:28]
reg rob_uop_20_is_eret; // @[rob.scala:361:28]
reg rob_uop_20_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_20_is_rocc; // @[rob.scala:361:28]
reg rob_uop_20_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_20_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_20_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_pc_lob; // @[rob.scala:361:28]
reg rob_uop_20_taken; // @[rob.scala:361:28]
reg rob_uop_20_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_20_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_20_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_op2_sel; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_20_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_20_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_20_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_20_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_20_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_20_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_20_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_20_ppred; // @[rob.scala:361:28]
reg rob_uop_20_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_20_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_20_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_20_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_20_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_20_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_20_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_20_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_mem_size; // @[rob.scala:361:28]
reg rob_uop_20_mem_signed; // @[rob.scala:361:28]
reg rob_uop_20_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_20_uses_stq; // @[rob.scala:361:28]
reg rob_uop_20_is_unique; // @[rob.scala:361:28]
reg rob_uop_20_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_20_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_20_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_20_frs3_en; // @[rob.scala:361:28]
reg rob_uop_20_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_20_fcn_op; // @[rob.scala:361:28]
reg rob_uop_20_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_20_fp_typ; // @[rob.scala:361:28]
reg rob_uop_20_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_20_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_20_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_20_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_20_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_20_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_21_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_21_debug_inst; // @[rob.scala:361:28]
reg rob_uop_21_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_21_debug_pc; // @[rob.scala:361:28]
reg rob_uop_21_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_21_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_21_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_21_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_21_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_21_iw_issued; // @[rob.scala:361:28]
reg rob_uop_21_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_21_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_21_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_21_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_21_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_21_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_21_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_21_br_type; // @[rob.scala:361:28]
reg rob_uop_21_is_sfb; // @[rob.scala:361:28]
reg rob_uop_21_is_fence; // @[rob.scala:361:28]
reg rob_uop_21_is_fencei; // @[rob.scala:361:28]
reg rob_uop_21_is_sfence; // @[rob.scala:361:28]
reg rob_uop_21_is_amo; // @[rob.scala:361:28]
reg rob_uop_21_is_eret; // @[rob.scala:361:28]
reg rob_uop_21_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_21_is_rocc; // @[rob.scala:361:28]
reg rob_uop_21_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_21_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_21_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_pc_lob; // @[rob.scala:361:28]
reg rob_uop_21_taken; // @[rob.scala:361:28]
reg rob_uop_21_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_21_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_21_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_op2_sel; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_21_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_21_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_21_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_21_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_21_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_21_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_21_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_21_ppred; // @[rob.scala:361:28]
reg rob_uop_21_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_21_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_21_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_21_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_21_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_21_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_21_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_21_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_mem_size; // @[rob.scala:361:28]
reg rob_uop_21_mem_signed; // @[rob.scala:361:28]
reg rob_uop_21_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_21_uses_stq; // @[rob.scala:361:28]
reg rob_uop_21_is_unique; // @[rob.scala:361:28]
reg rob_uop_21_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_21_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_21_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_21_frs3_en; // @[rob.scala:361:28]
reg rob_uop_21_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_21_fcn_op; // @[rob.scala:361:28]
reg rob_uop_21_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_21_fp_typ; // @[rob.scala:361:28]
reg rob_uop_21_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_21_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_21_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_21_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_21_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_21_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_22_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_22_debug_inst; // @[rob.scala:361:28]
reg rob_uop_22_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_22_debug_pc; // @[rob.scala:361:28]
reg rob_uop_22_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_22_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_22_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_22_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_22_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_22_iw_issued; // @[rob.scala:361:28]
reg rob_uop_22_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_22_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_22_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_22_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_22_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_22_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_22_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_22_br_type; // @[rob.scala:361:28]
reg rob_uop_22_is_sfb; // @[rob.scala:361:28]
reg rob_uop_22_is_fence; // @[rob.scala:361:28]
reg rob_uop_22_is_fencei; // @[rob.scala:361:28]
reg rob_uop_22_is_sfence; // @[rob.scala:361:28]
reg rob_uop_22_is_amo; // @[rob.scala:361:28]
reg rob_uop_22_is_eret; // @[rob.scala:361:28]
reg rob_uop_22_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_22_is_rocc; // @[rob.scala:361:28]
reg rob_uop_22_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_22_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_22_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_pc_lob; // @[rob.scala:361:28]
reg rob_uop_22_taken; // @[rob.scala:361:28]
reg rob_uop_22_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_22_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_22_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_op2_sel; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_22_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_22_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_22_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_22_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_22_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_22_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_22_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_22_ppred; // @[rob.scala:361:28]
reg rob_uop_22_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_22_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_22_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_22_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_22_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_22_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_22_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_22_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_mem_size; // @[rob.scala:361:28]
reg rob_uop_22_mem_signed; // @[rob.scala:361:28]
reg rob_uop_22_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_22_uses_stq; // @[rob.scala:361:28]
reg rob_uop_22_is_unique; // @[rob.scala:361:28]
reg rob_uop_22_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_22_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_22_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_22_frs3_en; // @[rob.scala:361:28]
reg rob_uop_22_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_22_fcn_op; // @[rob.scala:361:28]
reg rob_uop_22_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_22_fp_typ; // @[rob.scala:361:28]
reg rob_uop_22_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_22_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_22_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_22_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_22_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_22_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_23_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_23_debug_inst; // @[rob.scala:361:28]
reg rob_uop_23_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_23_debug_pc; // @[rob.scala:361:28]
reg rob_uop_23_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_23_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_23_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_23_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_23_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_23_iw_issued; // @[rob.scala:361:28]
reg rob_uop_23_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_23_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_23_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_23_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_23_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_23_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_23_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_23_br_type; // @[rob.scala:361:28]
reg rob_uop_23_is_sfb; // @[rob.scala:361:28]
reg rob_uop_23_is_fence; // @[rob.scala:361:28]
reg rob_uop_23_is_fencei; // @[rob.scala:361:28]
reg rob_uop_23_is_sfence; // @[rob.scala:361:28]
reg rob_uop_23_is_amo; // @[rob.scala:361:28]
reg rob_uop_23_is_eret; // @[rob.scala:361:28]
reg rob_uop_23_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_23_is_rocc; // @[rob.scala:361:28]
reg rob_uop_23_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_23_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_23_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_pc_lob; // @[rob.scala:361:28]
reg rob_uop_23_taken; // @[rob.scala:361:28]
reg rob_uop_23_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_23_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_23_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_op2_sel; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_23_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_23_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_23_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_23_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_23_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_23_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_23_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_23_ppred; // @[rob.scala:361:28]
reg rob_uop_23_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_23_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_23_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_23_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_23_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_23_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_23_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_23_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_mem_size; // @[rob.scala:361:28]
reg rob_uop_23_mem_signed; // @[rob.scala:361:28]
reg rob_uop_23_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_23_uses_stq; // @[rob.scala:361:28]
reg rob_uop_23_is_unique; // @[rob.scala:361:28]
reg rob_uop_23_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_23_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_23_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_23_frs3_en; // @[rob.scala:361:28]
reg rob_uop_23_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_23_fcn_op; // @[rob.scala:361:28]
reg rob_uop_23_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_23_fp_typ; // @[rob.scala:361:28]
reg rob_uop_23_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_23_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_23_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_23_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_23_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_23_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_24_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_24_debug_inst; // @[rob.scala:361:28]
reg rob_uop_24_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_24_debug_pc; // @[rob.scala:361:28]
reg rob_uop_24_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_24_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_24_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_24_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_24_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_24_iw_issued; // @[rob.scala:361:28]
reg rob_uop_24_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_24_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_24_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_24_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_24_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_24_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_24_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_24_br_type; // @[rob.scala:361:28]
reg rob_uop_24_is_sfb; // @[rob.scala:361:28]
reg rob_uop_24_is_fence; // @[rob.scala:361:28]
reg rob_uop_24_is_fencei; // @[rob.scala:361:28]
reg rob_uop_24_is_sfence; // @[rob.scala:361:28]
reg rob_uop_24_is_amo; // @[rob.scala:361:28]
reg rob_uop_24_is_eret; // @[rob.scala:361:28]
reg rob_uop_24_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_24_is_rocc; // @[rob.scala:361:28]
reg rob_uop_24_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_24_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_24_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_pc_lob; // @[rob.scala:361:28]
reg rob_uop_24_taken; // @[rob.scala:361:28]
reg rob_uop_24_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_24_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_24_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_op2_sel; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_24_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_24_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_24_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_24_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_24_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_24_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_24_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_24_ppred; // @[rob.scala:361:28]
reg rob_uop_24_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_24_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_24_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_24_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_24_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_24_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_24_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_24_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_mem_size; // @[rob.scala:361:28]
reg rob_uop_24_mem_signed; // @[rob.scala:361:28]
reg rob_uop_24_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_24_uses_stq; // @[rob.scala:361:28]
reg rob_uop_24_is_unique; // @[rob.scala:361:28]
reg rob_uop_24_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_24_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_24_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_24_frs3_en; // @[rob.scala:361:28]
reg rob_uop_24_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_24_fcn_op; // @[rob.scala:361:28]
reg rob_uop_24_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_24_fp_typ; // @[rob.scala:361:28]
reg rob_uop_24_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_24_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_24_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_24_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_24_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_24_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_25_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_25_debug_inst; // @[rob.scala:361:28]
reg rob_uop_25_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_25_debug_pc; // @[rob.scala:361:28]
reg rob_uop_25_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_25_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_25_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_25_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_25_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_25_iw_issued; // @[rob.scala:361:28]
reg rob_uop_25_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_25_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_25_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_25_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_25_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_25_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_25_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_25_br_type; // @[rob.scala:361:28]
reg rob_uop_25_is_sfb; // @[rob.scala:361:28]
reg rob_uop_25_is_fence; // @[rob.scala:361:28]
reg rob_uop_25_is_fencei; // @[rob.scala:361:28]
reg rob_uop_25_is_sfence; // @[rob.scala:361:28]
reg rob_uop_25_is_amo; // @[rob.scala:361:28]
reg rob_uop_25_is_eret; // @[rob.scala:361:28]
reg rob_uop_25_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_25_is_rocc; // @[rob.scala:361:28]
reg rob_uop_25_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_25_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_25_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_pc_lob; // @[rob.scala:361:28]
reg rob_uop_25_taken; // @[rob.scala:361:28]
reg rob_uop_25_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_25_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_25_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_op2_sel; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_25_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_25_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_25_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_25_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_25_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_25_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_25_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_25_ppred; // @[rob.scala:361:28]
reg rob_uop_25_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_25_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_25_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_25_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_25_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_25_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_25_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_25_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_mem_size; // @[rob.scala:361:28]
reg rob_uop_25_mem_signed; // @[rob.scala:361:28]
reg rob_uop_25_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_25_uses_stq; // @[rob.scala:361:28]
reg rob_uop_25_is_unique; // @[rob.scala:361:28]
reg rob_uop_25_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_25_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_25_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_25_frs3_en; // @[rob.scala:361:28]
reg rob_uop_25_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_25_fcn_op; // @[rob.scala:361:28]
reg rob_uop_25_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_25_fp_typ; // @[rob.scala:361:28]
reg rob_uop_25_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_25_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_25_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_25_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_25_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_25_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_26_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_26_debug_inst; // @[rob.scala:361:28]
reg rob_uop_26_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_26_debug_pc; // @[rob.scala:361:28]
reg rob_uop_26_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_26_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_26_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_26_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_26_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_26_iw_issued; // @[rob.scala:361:28]
reg rob_uop_26_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_26_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_26_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_26_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_26_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_26_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_26_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_26_br_type; // @[rob.scala:361:28]
reg rob_uop_26_is_sfb; // @[rob.scala:361:28]
reg rob_uop_26_is_fence; // @[rob.scala:361:28]
reg rob_uop_26_is_fencei; // @[rob.scala:361:28]
reg rob_uop_26_is_sfence; // @[rob.scala:361:28]
reg rob_uop_26_is_amo; // @[rob.scala:361:28]
reg rob_uop_26_is_eret; // @[rob.scala:361:28]
reg rob_uop_26_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_26_is_rocc; // @[rob.scala:361:28]
reg rob_uop_26_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_26_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_26_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_pc_lob; // @[rob.scala:361:28]
reg rob_uop_26_taken; // @[rob.scala:361:28]
reg rob_uop_26_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_26_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_26_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_op2_sel; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_26_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_26_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_26_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_26_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_26_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_26_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_26_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_26_ppred; // @[rob.scala:361:28]
reg rob_uop_26_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_26_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_26_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_26_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_26_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_26_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_26_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_26_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_mem_size; // @[rob.scala:361:28]
reg rob_uop_26_mem_signed; // @[rob.scala:361:28]
reg rob_uop_26_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_26_uses_stq; // @[rob.scala:361:28]
reg rob_uop_26_is_unique; // @[rob.scala:361:28]
reg rob_uop_26_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_26_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_26_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_26_frs3_en; // @[rob.scala:361:28]
reg rob_uop_26_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_26_fcn_op; // @[rob.scala:361:28]
reg rob_uop_26_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_26_fp_typ; // @[rob.scala:361:28]
reg rob_uop_26_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_26_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_26_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_26_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_26_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_26_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_27_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_27_debug_inst; // @[rob.scala:361:28]
reg rob_uop_27_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_27_debug_pc; // @[rob.scala:361:28]
reg rob_uop_27_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_27_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_27_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_27_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_27_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_27_iw_issued; // @[rob.scala:361:28]
reg rob_uop_27_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_27_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_27_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_27_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_27_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_27_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_27_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_27_br_type; // @[rob.scala:361:28]
reg rob_uop_27_is_sfb; // @[rob.scala:361:28]
reg rob_uop_27_is_fence; // @[rob.scala:361:28]
reg rob_uop_27_is_fencei; // @[rob.scala:361:28]
reg rob_uop_27_is_sfence; // @[rob.scala:361:28]
reg rob_uop_27_is_amo; // @[rob.scala:361:28]
reg rob_uop_27_is_eret; // @[rob.scala:361:28]
reg rob_uop_27_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_27_is_rocc; // @[rob.scala:361:28]
reg rob_uop_27_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_27_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_27_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_pc_lob; // @[rob.scala:361:28]
reg rob_uop_27_taken; // @[rob.scala:361:28]
reg rob_uop_27_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_27_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_27_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_op2_sel; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_27_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_27_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_27_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_27_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_27_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_27_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_27_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_27_ppred; // @[rob.scala:361:28]
reg rob_uop_27_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_27_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_27_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_27_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_27_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_27_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_27_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_27_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_mem_size; // @[rob.scala:361:28]
reg rob_uop_27_mem_signed; // @[rob.scala:361:28]
reg rob_uop_27_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_27_uses_stq; // @[rob.scala:361:28]
reg rob_uop_27_is_unique; // @[rob.scala:361:28]
reg rob_uop_27_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_27_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_27_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_27_frs3_en; // @[rob.scala:361:28]
reg rob_uop_27_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_27_fcn_op; // @[rob.scala:361:28]
reg rob_uop_27_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_27_fp_typ; // @[rob.scala:361:28]
reg rob_uop_27_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_27_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_27_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_27_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_27_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_27_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_28_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_28_debug_inst; // @[rob.scala:361:28]
reg rob_uop_28_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_28_debug_pc; // @[rob.scala:361:28]
reg rob_uop_28_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_28_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_28_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_28_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_28_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_28_iw_issued; // @[rob.scala:361:28]
reg rob_uop_28_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_28_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_28_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_28_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_28_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_28_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_28_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_28_br_type; // @[rob.scala:361:28]
reg rob_uop_28_is_sfb; // @[rob.scala:361:28]
reg rob_uop_28_is_fence; // @[rob.scala:361:28]
reg rob_uop_28_is_fencei; // @[rob.scala:361:28]
reg rob_uop_28_is_sfence; // @[rob.scala:361:28]
reg rob_uop_28_is_amo; // @[rob.scala:361:28]
reg rob_uop_28_is_eret; // @[rob.scala:361:28]
reg rob_uop_28_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_28_is_rocc; // @[rob.scala:361:28]
reg rob_uop_28_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_28_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_28_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_pc_lob; // @[rob.scala:361:28]
reg rob_uop_28_taken; // @[rob.scala:361:28]
reg rob_uop_28_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_28_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_28_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_op2_sel; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_28_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_28_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_28_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_28_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_28_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_28_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_28_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_28_ppred; // @[rob.scala:361:28]
reg rob_uop_28_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_28_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_28_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_28_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_28_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_28_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_28_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_28_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_mem_size; // @[rob.scala:361:28]
reg rob_uop_28_mem_signed; // @[rob.scala:361:28]
reg rob_uop_28_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_28_uses_stq; // @[rob.scala:361:28]
reg rob_uop_28_is_unique; // @[rob.scala:361:28]
reg rob_uop_28_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_28_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_28_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_28_frs3_en; // @[rob.scala:361:28]
reg rob_uop_28_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_28_fcn_op; // @[rob.scala:361:28]
reg rob_uop_28_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_28_fp_typ; // @[rob.scala:361:28]
reg rob_uop_28_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_28_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_28_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_28_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_28_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_28_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_29_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_29_debug_inst; // @[rob.scala:361:28]
reg rob_uop_29_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_29_debug_pc; // @[rob.scala:361:28]
reg rob_uop_29_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_29_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_29_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_29_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_29_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_29_iw_issued; // @[rob.scala:361:28]
reg rob_uop_29_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_29_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_29_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_29_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_29_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_29_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_29_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_29_br_type; // @[rob.scala:361:28]
reg rob_uop_29_is_sfb; // @[rob.scala:361:28]
reg rob_uop_29_is_fence; // @[rob.scala:361:28]
reg rob_uop_29_is_fencei; // @[rob.scala:361:28]
reg rob_uop_29_is_sfence; // @[rob.scala:361:28]
reg rob_uop_29_is_amo; // @[rob.scala:361:28]
reg rob_uop_29_is_eret; // @[rob.scala:361:28]
reg rob_uop_29_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_29_is_rocc; // @[rob.scala:361:28]
reg rob_uop_29_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_29_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_29_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_pc_lob; // @[rob.scala:361:28]
reg rob_uop_29_taken; // @[rob.scala:361:28]
reg rob_uop_29_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_29_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_29_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_op2_sel; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_29_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_29_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_29_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_29_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_29_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_29_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_29_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_29_ppred; // @[rob.scala:361:28]
reg rob_uop_29_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_29_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_29_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_29_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_29_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_29_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_29_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_29_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_mem_size; // @[rob.scala:361:28]
reg rob_uop_29_mem_signed; // @[rob.scala:361:28]
reg rob_uop_29_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_29_uses_stq; // @[rob.scala:361:28]
reg rob_uop_29_is_unique; // @[rob.scala:361:28]
reg rob_uop_29_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_29_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_29_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_29_frs3_en; // @[rob.scala:361:28]
reg rob_uop_29_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_29_fcn_op; // @[rob.scala:361:28]
reg rob_uop_29_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_29_fp_typ; // @[rob.scala:361:28]
reg rob_uop_29_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_29_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_29_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_29_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_29_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_29_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_30_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_30_debug_inst; // @[rob.scala:361:28]
reg rob_uop_30_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_30_debug_pc; // @[rob.scala:361:28]
reg rob_uop_30_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_30_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_30_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_30_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_30_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_30_iw_issued; // @[rob.scala:361:28]
reg rob_uop_30_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_30_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_30_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_30_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_30_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_30_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_30_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_30_br_type; // @[rob.scala:361:28]
reg rob_uop_30_is_sfb; // @[rob.scala:361:28]
reg rob_uop_30_is_fence; // @[rob.scala:361:28]
reg rob_uop_30_is_fencei; // @[rob.scala:361:28]
reg rob_uop_30_is_sfence; // @[rob.scala:361:28]
reg rob_uop_30_is_amo; // @[rob.scala:361:28]
reg rob_uop_30_is_eret; // @[rob.scala:361:28]
reg rob_uop_30_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_30_is_rocc; // @[rob.scala:361:28]
reg rob_uop_30_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_30_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_30_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_pc_lob; // @[rob.scala:361:28]
reg rob_uop_30_taken; // @[rob.scala:361:28]
reg rob_uop_30_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_30_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_30_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_op2_sel; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_30_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_30_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_30_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_30_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_30_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_30_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_30_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_30_ppred; // @[rob.scala:361:28]
reg rob_uop_30_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_30_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_30_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_30_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_30_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_30_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_30_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_30_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_mem_size; // @[rob.scala:361:28]
reg rob_uop_30_mem_signed; // @[rob.scala:361:28]
reg rob_uop_30_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_30_uses_stq; // @[rob.scala:361:28]
reg rob_uop_30_is_unique; // @[rob.scala:361:28]
reg rob_uop_30_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_30_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_30_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_30_frs3_en; // @[rob.scala:361:28]
reg rob_uop_30_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_30_fcn_op; // @[rob.scala:361:28]
reg rob_uop_30_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_30_fp_typ; // @[rob.scala:361:28]
reg rob_uop_30_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_30_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_30_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_30_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_30_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_30_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_31_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_31_debug_inst; // @[rob.scala:361:28]
reg rob_uop_31_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_31_debug_pc; // @[rob.scala:361:28]
reg rob_uop_31_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_31_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_31_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_31_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_31_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_31_iw_issued; // @[rob.scala:361:28]
reg rob_uop_31_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_31_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_31_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_31_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_31_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_31_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_31_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_31_br_type; // @[rob.scala:361:28]
reg rob_uop_31_is_sfb; // @[rob.scala:361:28]
reg rob_uop_31_is_fence; // @[rob.scala:361:28]
reg rob_uop_31_is_fencei; // @[rob.scala:361:28]
reg rob_uop_31_is_sfence; // @[rob.scala:361:28]
reg rob_uop_31_is_amo; // @[rob.scala:361:28]
reg rob_uop_31_is_eret; // @[rob.scala:361:28]
reg rob_uop_31_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_31_is_rocc; // @[rob.scala:361:28]
reg rob_uop_31_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_31_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_31_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_pc_lob; // @[rob.scala:361:28]
reg rob_uop_31_taken; // @[rob.scala:361:28]
reg rob_uop_31_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_31_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_31_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_op2_sel; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_31_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_31_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_31_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_31_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_31_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_31_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_31_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_31_ppred; // @[rob.scala:361:28]
reg rob_uop_31_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_31_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_31_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_31_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_31_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_31_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_31_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_31_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_mem_size; // @[rob.scala:361:28]
reg rob_uop_31_mem_signed; // @[rob.scala:361:28]
reg rob_uop_31_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_31_uses_stq; // @[rob.scala:361:28]
reg rob_uop_31_is_unique; // @[rob.scala:361:28]
reg rob_uop_31_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_31_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_31_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_31_frs3_en; // @[rob.scala:361:28]
reg rob_uop_31_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_31_fcn_op; // @[rob.scala:361:28]
reg rob_uop_31_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_31_fp_typ; // @[rob.scala:361:28]
reg rob_uop_31_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_31_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_31_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_31_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_31_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_31_debug_tsrc; // @[rob.scala:361:28]
reg rob_exception_0; // @[rob.scala:362:28]
reg rob_exception_1; // @[rob.scala:362:28]
reg rob_exception_2; // @[rob.scala:362:28]
reg rob_exception_3; // @[rob.scala:362:28]
reg rob_exception_4; // @[rob.scala:362:28]
reg rob_exception_5; // @[rob.scala:362:28]
reg rob_exception_6; // @[rob.scala:362:28]
reg rob_exception_7; // @[rob.scala:362:28]
reg rob_exception_8; // @[rob.scala:362:28]
reg rob_exception_9; // @[rob.scala:362:28]
reg rob_exception_10; // @[rob.scala:362:28]
reg rob_exception_11; // @[rob.scala:362:28]
reg rob_exception_12; // @[rob.scala:362:28]
reg rob_exception_13; // @[rob.scala:362:28]
reg rob_exception_14; // @[rob.scala:362:28]
reg rob_exception_15; // @[rob.scala:362:28]
reg rob_exception_16; // @[rob.scala:362:28]
reg rob_exception_17; // @[rob.scala:362:28]
reg rob_exception_18; // @[rob.scala:362:28]
reg rob_exception_19; // @[rob.scala:362:28]
reg rob_exception_20; // @[rob.scala:362:28]
reg rob_exception_21; // @[rob.scala:362:28]
reg rob_exception_22; // @[rob.scala:362:28]
reg rob_exception_23; // @[rob.scala:362:28]
reg rob_exception_24; // @[rob.scala:362:28]
reg rob_exception_25; // @[rob.scala:362:28]
reg rob_exception_26; // @[rob.scala:362:28]
reg rob_exception_27; // @[rob.scala:362:28]
reg rob_exception_28; // @[rob.scala:362:28]
reg rob_exception_29; // @[rob.scala:362:28]
reg rob_exception_30; // @[rob.scala:362:28]
reg rob_exception_31; // @[rob.scala:362:28]
reg rob_predicated_0; // @[rob.scala:363:29]
reg rob_predicated_1; // @[rob.scala:363:29]
reg rob_predicated_2; // @[rob.scala:363:29]
reg rob_predicated_3; // @[rob.scala:363:29]
reg rob_predicated_4; // @[rob.scala:363:29]
reg rob_predicated_5; // @[rob.scala:363:29]
reg rob_predicated_6; // @[rob.scala:363:29]
reg rob_predicated_7; // @[rob.scala:363:29]
reg rob_predicated_8; // @[rob.scala:363:29]
reg rob_predicated_9; // @[rob.scala:363:29]
reg rob_predicated_10; // @[rob.scala:363:29]
reg rob_predicated_11; // @[rob.scala:363:29]
reg rob_predicated_12; // @[rob.scala:363:29]
reg rob_predicated_13; // @[rob.scala:363:29]
reg rob_predicated_14; // @[rob.scala:363:29]
reg rob_predicated_15; // @[rob.scala:363:29]
reg rob_predicated_16; // @[rob.scala:363:29]
reg rob_predicated_17; // @[rob.scala:363:29]
reg rob_predicated_18; // @[rob.scala:363:29]
reg rob_predicated_19; // @[rob.scala:363:29]
reg rob_predicated_20; // @[rob.scala:363:29]
reg rob_predicated_21; // @[rob.scala:363:29]
reg rob_predicated_22; // @[rob.scala:363:29]
reg rob_predicated_23; // @[rob.scala:363:29]
reg rob_predicated_24; // @[rob.scala:363:29]
reg rob_predicated_25; // @[rob.scala:363:29]
reg rob_predicated_26; // @[rob.scala:363:29]
reg rob_predicated_27; // @[rob.scala:363:29]
reg rob_predicated_28; // @[rob.scala:363:29]
reg rob_predicated_29; // @[rob.scala:363:29]
reg rob_predicated_30; // @[rob.scala:363:29]
reg rob_predicated_31; // @[rob.scala:363:29]
reg rob_fflags_0_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_0_bits; // @[rob.scala:364:28]
reg rob_fflags_1_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_1_bits; // @[rob.scala:364:28]
reg rob_fflags_2_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_bits; // @[rob.scala:364:28]
reg rob_fflags_3_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_3_bits; // @[rob.scala:364:28]
reg rob_fflags_4_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_4_bits; // @[rob.scala:364:28]
reg rob_fflags_5_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_5_bits; // @[rob.scala:364:28]
reg rob_fflags_6_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_6_bits; // @[rob.scala:364:28]
reg rob_fflags_7_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_7_bits; // @[rob.scala:364:28]
reg rob_fflags_8_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_8_bits; // @[rob.scala:364:28]
reg rob_fflags_9_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_9_bits; // @[rob.scala:364:28]
reg rob_fflags_10_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_10_bits; // @[rob.scala:364:28]
reg rob_fflags_11_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_11_bits; // @[rob.scala:364:28]
reg rob_fflags_12_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_12_bits; // @[rob.scala:364:28]
reg rob_fflags_13_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_13_bits; // @[rob.scala:364:28]
reg rob_fflags_14_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_14_bits; // @[rob.scala:364:28]
reg rob_fflags_15_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_15_bits; // @[rob.scala:364:28]
reg rob_fflags_16_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_16_bits; // @[rob.scala:364:28]
reg rob_fflags_17_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_17_bits; // @[rob.scala:364:28]
reg rob_fflags_18_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_18_bits; // @[rob.scala:364:28]
reg rob_fflags_19_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_19_bits; // @[rob.scala:364:28]
reg rob_fflags_20_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_20_bits; // @[rob.scala:364:28]
reg rob_fflags_21_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_21_bits; // @[rob.scala:364:28]
reg rob_fflags_22_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_22_bits; // @[rob.scala:364:28]
reg rob_fflags_23_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_23_bits; // @[rob.scala:364:28]
reg rob_fflags_24_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_24_bits; // @[rob.scala:364:28]
reg rob_fflags_25_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_25_bits; // @[rob.scala:364:28]
reg rob_fflags_26_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_26_bits; // @[rob.scala:364:28]
reg rob_fflags_27_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_27_bits; // @[rob.scala:364:28]
reg rob_fflags_28_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_28_bits; // @[rob.scala:364:28]
reg rob_fflags_29_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_29_bits; // @[rob.scala:364:28]
reg rob_fflags_30_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_30_bits; // @[rob.scala:364:28]
reg rob_fflags_31_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_31_bits; // @[rob.scala:364:28]
wire [31:0] _GEN_2 = {{rob_val_31}, {rob_val_30}, {rob_val_29}, {rob_val_28}, {rob_val_27}, {rob_val_26}, {rob_val_25}, {rob_val_24}, {rob_val_23}, {rob_val_22}, {rob_val_21}, {rob_val_20}, {rob_val_19}, {rob_val_18}, {rob_val_17}, {rob_val_16}, {rob_val_15}, {rob_val_14}, {rob_val_13}, {rob_val_12}, {rob_val_11}, {rob_val_10}, {rob_val_9}, {rob_val_8}, {rob_val_7}, {rob_val_6}, {rob_val_5}, {rob_val_4}, {rob_val_3}, {rob_val_2}, {rob_val_1}, {rob_val_0}}; // @[rob.scala:358:32, :375:31]
assign rob_tail_vals_0 = _GEN_2[rob_tail]; // @[rob.scala:214:29, :235:33, :375:31]
wire _rob_bsy_T = io_enq_uops_0_is_fence_0 | io_enq_uops_0_is_fencei_0; // @[rob.scala:199:7]
wire _rob_bsy_T_1 = ~_rob_bsy_T; // @[micro-op.scala:162:{26,37}]
wire _rob_unsafe_T = ~io_enq_uops_0_is_fence_0; // @[rob.scala:199:7]
wire _rob_unsafe_T_1 = io_enq_uops_0_uses_stq_0 & _rob_unsafe_T; // @[rob.scala:199:7]
wire _rob_unsafe_T_2 = io_enq_uops_0_uses_ldq_0 | _rob_unsafe_T_1; // @[rob.scala:199:7]
wire _rob_unsafe_T_3 = io_enq_uops_0_br_type_0 == 4'h1; // @[package.scala:16:47]
wire _rob_unsafe_T_4 = io_enq_uops_0_br_type_0 == 4'h2; // @[package.scala:16:47]
wire _rob_unsafe_T_5 = io_enq_uops_0_br_type_0 == 4'h3; // @[package.scala:16:47]
wire _rob_unsafe_T_6 = io_enq_uops_0_br_type_0 == 4'h4; // @[package.scala:16:47]
wire _rob_unsafe_T_7 = io_enq_uops_0_br_type_0 == 4'h5; // @[package.scala:16:47]
wire _rob_unsafe_T_8 = io_enq_uops_0_br_type_0 == 4'h6; // @[package.scala:16:47]
wire _rob_unsafe_T_9 = _rob_unsafe_T_3 | _rob_unsafe_T_4; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_10 = _rob_unsafe_T_9 | _rob_unsafe_T_5; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_11 = _rob_unsafe_T_10 | _rob_unsafe_T_6; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_12 = _rob_unsafe_T_11 | _rob_unsafe_T_7; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_13 = _rob_unsafe_T_12 | _rob_unsafe_T_8; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_14 = _rob_unsafe_T_2 | _rob_unsafe_T_13; // @[package.scala:81:59]
wire _rob_unsafe_T_15 = io_enq_uops_0_br_type_0 == 4'h8; // @[rob.scala:199:7]
wire _rob_unsafe_T_16 = _rob_unsafe_T_14 | _rob_unsafe_T_15; // @[micro-op.scala:119:34, :164:{62,71}]
wire [5:0] _GEN_3 = {1'h0, io_wb_resps_0_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx; // @[rob.scala:254:25]
assign row_idx = _GEN_3; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T; // @[rob.scala:254:25]
assign _temp_uop_T = _GEN_3; // @[rob.scala:254:25]
wire [5:0] row_idx_6; // @[rob.scala:254:25]
assign row_idx_6 = _GEN_3; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_12; // @[rob.scala:254:25]
assign _temp_uop_T_12 = _GEN_3; // @[rob.scala:254:25]
wire _T_14 = io_wb_resps_0_valid_0 & ~(io_wb_resps_0_bits_uop_rob_idx_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :397:27]
wire [31:0] _GEN_4 = {{rob_fflags_31_valid}, {rob_fflags_30_valid}, {rob_fflags_29_valid}, {rob_fflags_28_valid}, {rob_fflags_27_valid}, {rob_fflags_26_valid}, {rob_fflags_25_valid}, {rob_fflags_24_valid}, {rob_fflags_23_valid}, {rob_fflags_22_valid}, {rob_fflags_21_valid}, {rob_fflags_20_valid}, {rob_fflags_19_valid}, {rob_fflags_18_valid}, {rob_fflags_17_valid}, {rob_fflags_16_valid}, {rob_fflags_15_valid}, {rob_fflags_14_valid}, {rob_fflags_13_valid}, {rob_fflags_12_valid}, {rob_fflags_11_valid}, {rob_fflags_10_valid}, {rob_fflags_9_valid}, {rob_fflags_8_valid}, {rob_fflags_7_valid}, {rob_fflags_6_valid}, {rob_fflags_5_valid}, {rob_fflags_4_valid}, {rob_fflags_3_valid}, {rob_fflags_2_valid}, {rob_fflags_1_valid}, {rob_fflags_0_valid}}; // @[rob.scala:364:28, :402:18]
wire [5:0] _GEN_5 = {1'h0, io_wb_resps_1_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx_1; // @[rob.scala:254:25]
assign row_idx_1 = _GEN_5; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_2; // @[rob.scala:254:25]
assign _temp_uop_T_2 = _GEN_5; // @[rob.scala:254:25]
wire [5:0] row_idx_7; // @[rob.scala:254:25]
assign row_idx_7 = _GEN_5; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_14; // @[rob.scala:254:25]
assign _temp_uop_T_14 = _GEN_5; // @[rob.scala:254:25]
wire _T_27 = io_wb_resps_1_valid_0 & ~(io_wb_resps_1_bits_uop_rob_idx_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :397:27]
wire _GEN_6 = _T_27 & io_wb_resps_1_bits_fflags_valid_0; // @[rob.scala:199:7, :397:27, :401:42]
wire [5:0] _GEN_7 = {1'h0, io_wb_resps_2_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx_2; // @[rob.scala:254:25]
assign row_idx_2 = _GEN_7; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_4; // @[rob.scala:254:25]
assign _temp_uop_T_4 = _GEN_7; // @[rob.scala:254:25]
wire [5:0] row_idx_8; // @[rob.scala:254:25]
assign row_idx_8 = _GEN_7; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_16; // @[rob.scala:254:25]
assign _temp_uop_T_16 = _GEN_7; // @[rob.scala:254:25]
wire [5:0] _GEN_8 = {1'h0, io_wb_resps_3_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx_3; // @[rob.scala:254:25]
assign row_idx_3 = _GEN_8; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_6; // @[rob.scala:254:25]
assign _temp_uop_T_6 = _GEN_8; // @[rob.scala:254:25]
wire [5:0] row_idx_9; // @[rob.scala:254:25]
assign row_idx_9 = _GEN_8; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_18; // @[rob.scala:254:25]
assign _temp_uop_T_18 = _GEN_8; // @[rob.scala:254:25]
wire [5:0] _GEN_9 = {1'h0, io_wb_resps_4_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx_4; // @[rob.scala:254:25]
assign row_idx_4 = _GEN_9; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_8; // @[rob.scala:254:25]
assign _temp_uop_T_8 = _GEN_9; // @[rob.scala:254:25]
wire [5:0] row_idx_10; // @[rob.scala:254:25]
assign row_idx_10 = _GEN_9; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_20; // @[rob.scala:254:25]
assign _temp_uop_T_20 = _GEN_9; // @[rob.scala:254:25]
wire _T_66 = io_wb_resps_4_valid_0 & ~(io_wb_resps_4_bits_uop_rob_idx_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :397:27]
wire [5:0] _GEN_10 = {1'h0, io_wb_resps_5_bits_uop_rob_idx_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] row_idx_5; // @[rob.scala:254:25]
assign row_idx_5 = _GEN_10; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_10; // @[rob.scala:254:25]
assign _temp_uop_T_10 = _GEN_10; // @[rob.scala:254:25]
wire [5:0] row_idx_11; // @[rob.scala:254:25]
assign row_idx_11 = _GEN_10; // @[rob.scala:254:25]
wire [5:0] _temp_uop_T_22; // @[rob.scala:254:25]
assign _temp_uop_T_22 = _GEN_10; // @[rob.scala:254:25]
wire _T_79 = io_wb_resps_5_valid_0 & ~(io_wb_resps_5_bits_uop_rob_idx_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :397:27]
wire _GEN_11 = _T_79 & io_wb_resps_5_bits_fflags_valid_0; // @[rob.scala:199:7, :397:27, :401:42]
wire _T_92 = io_lsu_clr_bsy_0_valid_0 & ~(io_lsu_clr_bsy_0_bits_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :413:31]
wire [5:0] _GEN_12 = {1'h0, io_lsu_clr_bsy_0_bits_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] cidx; // @[rob.scala:254:25]
assign cidx = _GEN_12; // @[rob.scala:254:25]
wire [5:0] cidx_3; // @[rob.scala:254:25]
assign cidx_3 = _GEN_12; // @[rob.scala:254:25]
wire [31:0] _GEN_13 = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[rob.scala:359:28, :418:31]
wire _T_107 = io_lsu_clr_bsy_1_valid_0 & ~(io_lsu_clr_bsy_1_bits_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :413:31]
wire [5:0] _GEN_14 = {1'h0, io_lsu_clr_bsy_1_bits_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] cidx_1; // @[rob.scala:254:25]
assign cidx_1 = _GEN_14; // @[rob.scala:254:25]
wire [5:0] cidx_4; // @[rob.scala:254:25]
assign cidx_4 = _GEN_14; // @[rob.scala:254:25]
wire [5:0] _GEN_15 = {1'h0, io_lsu_clr_unsafe_0_bits_0[5:1]}; // @[rob.scala:199:7, :254:25]
wire [5:0] cidx_2; // @[rob.scala:254:25]
assign cidx_2 = _GEN_15; // @[rob.scala:254:25]
wire [5:0] cidx_5; // @[rob.scala:254:25]
assign cidx_5 = _GEN_15; // @[rob.scala:254:25]
wire _T_126 = io_lxcpt_valid_0 & ~(io_lxcpt_bits_uop_rob_idx_0[0]); // @[rob.scala:199:7, :258:36, :355:53, :433:26]
wire _GEN_16 = _T_126 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:199:7, :433:26, :435:{33,66}, :437:15]
wire [31:0] _GEN_17 = {{rob_unsafe_31}, {rob_unsafe_30}, {rob_unsafe_29}, {rob_unsafe_28}, {rob_unsafe_27}, {rob_unsafe_26}, {rob_unsafe_25}, {rob_unsafe_24}, {rob_unsafe_23}, {rob_unsafe_22}, {rob_unsafe_21}, {rob_unsafe_20}, {rob_unsafe_19}, {rob_unsafe_18}, {rob_unsafe_17}, {rob_unsafe_16}, {rob_unsafe_15}, {rob_unsafe_14}, {rob_unsafe_13}, {rob_unsafe_12}, {rob_unsafe_11}, {rob_unsafe_10}, {rob_unsafe_9}, {rob_unsafe_8}, {rob_unsafe_7}, {rob_unsafe_6}, {rob_unsafe_5}, {rob_unsafe_4}, {rob_unsafe_3}, {rob_unsafe_2}, {rob_unsafe_1}, {rob_unsafe_0}}; // @[rob.scala:360:28, :437:15]
wire _GEN_18 = _GEN_17[io_lxcpt_bits_uop_rob_idx_0[5:1]]; // @[rob.scala:199:7, :254:25, :437:15]
assign rob_head_vals_0 = _GEN_2[rob_head]; // @[rob.scala:210:29, :234:33, :375:31, :444:49]
wire [31:0] _GEN_19 = {{rob_exception_31}, {rob_exception_30}, {rob_exception_29}, {rob_exception_28}, {rob_exception_27}, {rob_exception_26}, {rob_exception_25}, {rob_exception_24}, {rob_exception_23}, {rob_exception_22}, {rob_exception_21}, {rob_exception_20}, {rob_exception_19}, {rob_exception_18}, {rob_exception_17}, {rob_exception_16}, {rob_exception_15}, {rob_exception_14}, {rob_exception_13}, {rob_exception_12}, {rob_exception_11}, {rob_exception_10}, {rob_exception_9}, {rob_exception_8}, {rob_exception_7}, {rob_exception_6}, {rob_exception_5}, {rob_exception_4}, {rob_exception_3}, {rob_exception_2}, {rob_exception_1}, {rob_exception_0}}; // @[rob.scala:362:28, :444:49]
assign _can_throw_exception_0_T = rob_head_vals_0 & _GEN_19[rob_head]; // @[rob.scala:210:29, :234:33, :444:49]
assign can_throw_exception_0 = _can_throw_exception_0_T; // @[rob.scala:231:33, :444:49]
wire _can_commit_0_T = ~_GEN_13[rob_head]; // @[rob.scala:210:29, :418:31, :451:43]
wire _can_commit_0_T_1 = rob_head_vals_0 & _can_commit_0_T; // @[rob.scala:234:33, :451:{40,43}]
wire _can_commit_0_T_2 = ~io_csr_stall_0; // @[rob.scala:199:7, :451:67]
wire _can_commit_0_T_3 = _can_commit_0_T_1 & _can_commit_0_T_2; // @[rob.scala:451:{40,64,67}]
wire _can_commit_0_T_4 = ~io_brupdate_b2_mispredict_0; // @[rob.scala:199:7, :451:84]
assign _can_commit_0_T_5 = _can_commit_0_T_3 & _can_commit_0_T_4; // @[rob.scala:451:{64,81,84}]
assign can_commit_0 = _can_commit_0_T_5; // @[rob.scala:230:33, :451:81]
wire [31:0] _GEN_20 = {{rob_predicated_31}, {rob_predicated_30}, {rob_predicated_29}, {rob_predicated_28}, {rob_predicated_27}, {rob_predicated_26}, {rob_predicated_25}, {rob_predicated_24}, {rob_predicated_23}, {rob_predicated_22}, {rob_predicated_21}, {rob_predicated_20}, {rob_predicated_19}, {rob_predicated_18}, {rob_predicated_17}, {rob_predicated_16}, {rob_predicated_15}, {rob_predicated_14}, {rob_predicated_13}, {rob_predicated_12}, {rob_predicated_11}, {rob_predicated_10}, {rob_predicated_9}, {rob_predicated_8}, {rob_predicated_7}, {rob_predicated_6}, {rob_predicated_5}, {rob_predicated_4}, {rob_predicated_3}, {rob_predicated_2}, {rob_predicated_1}, {rob_predicated_0}}; // @[rob.scala:363:29, :457:51]
wire _io_commit_arch_valids_0_T = ~_GEN_20[rob_head]; // @[rob.scala:210:29, :457:51]
assign _io_commit_arch_valids_0_T_1 = will_commit_0 & _io_commit_arch_valids_0_T; // @[rob.scala:229:33, :457:{48,51}]
assign io_commit_arch_valids_0_0 = _io_commit_arch_valids_0_T_1; // @[rob.scala:199:7, :457:48]
assign io_commit_uops_0_inst_0 = io_commit_uops_0_out_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_debug_inst_0 = io_commit_uops_0_out_debug_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_rvc_0 = io_commit_uops_0_out_is_rvc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_debug_pc_0 = io_commit_uops_0_out_debug_pc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iq_type_0_0 = io_commit_uops_0_out_iq_type_0; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iq_type_1_0 = io_commit_uops_0_out_iq_type_1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iq_type_2_0 = io_commit_uops_0_out_iq_type_2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iq_type_3_0 = io_commit_uops_0_out_iq_type_3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_0_0 = io_commit_uops_0_out_fu_code_0; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_1_0 = io_commit_uops_0_out_fu_code_1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_2_0 = io_commit_uops_0_out_fu_code_2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_3_0 = io_commit_uops_0_out_fu_code_3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_4_0 = io_commit_uops_0_out_fu_code_4; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_5_0 = io_commit_uops_0_out_fu_code_5; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_6_0 = io_commit_uops_0_out_fu_code_6; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_7_0 = io_commit_uops_0_out_fu_code_7; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_8_0 = io_commit_uops_0_out_fu_code_8; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fu_code_9_0 = io_commit_uops_0_out_fu_code_9; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_issued_0 = io_commit_uops_0_out_iw_issued; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_issued_partial_agen_0 = io_commit_uops_0_out_iw_issued_partial_agen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_issued_partial_dgen_0 = io_commit_uops_0_out_iw_issued_partial_dgen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_p1_speculative_child_0 = io_commit_uops_0_out_iw_p1_speculative_child; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_p2_speculative_child_0 = io_commit_uops_0_out_iw_p2_speculative_child; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_p1_bypass_hint_0 = io_commit_uops_0_out_iw_p1_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_p2_bypass_hint_0 = io_commit_uops_0_out_iw_p2_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_iw_p3_bypass_hint_0 = io_commit_uops_0_out_iw_p3_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_dis_col_sel_0 = io_commit_uops_0_out_dis_col_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_br_mask_0 = io_commit_uops_0_out_br_mask; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_br_tag_0 = io_commit_uops_0_out_br_tag; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_br_type_0 = io_commit_uops_0_out_br_type; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_sfb_0 = io_commit_uops_0_out_is_sfb; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_fence_0 = io_commit_uops_0_out_is_fence; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_fencei_0 = io_commit_uops_0_out_is_fencei; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_sfence_0 = io_commit_uops_0_out_is_sfence; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_amo_0 = io_commit_uops_0_out_is_amo; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_eret_0 = io_commit_uops_0_out_is_eret; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_sys_pc2epc_0 = io_commit_uops_0_out_is_sys_pc2epc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_rocc_0 = io_commit_uops_0_out_is_rocc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_mov_0 = io_commit_uops_0_out_is_mov; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ftq_idx_0 = io_commit_uops_0_out_ftq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_edge_inst_0 = io_commit_uops_0_out_edge_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_pc_lob_0 = io_commit_uops_0_out_pc_lob; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_imm_rename_0 = io_commit_uops_0_out_imm_rename; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_imm_sel_0 = io_commit_uops_0_out_imm_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_pimm_0 = io_commit_uops_0_out_pimm; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_imm_packed_0 = io_commit_uops_0_out_imm_packed; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_op1_sel_0 = io_commit_uops_0_out_op1_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_op2_sel_0 = io_commit_uops_0_out_op2_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_ldst_0 = io_commit_uops_0_out_fp_ctrl_ldst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_wen_0 = io_commit_uops_0_out_fp_ctrl_wen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_ren1_0 = io_commit_uops_0_out_fp_ctrl_ren1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_ren2_0 = io_commit_uops_0_out_fp_ctrl_ren2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_ren3_0 = io_commit_uops_0_out_fp_ctrl_ren3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_swap12_0 = io_commit_uops_0_out_fp_ctrl_swap12; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_swap23_0 = io_commit_uops_0_out_fp_ctrl_swap23; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_typeTagIn_0 = io_commit_uops_0_out_fp_ctrl_typeTagIn; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_typeTagOut_0 = io_commit_uops_0_out_fp_ctrl_typeTagOut; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_fromint_0 = io_commit_uops_0_out_fp_ctrl_fromint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_toint_0 = io_commit_uops_0_out_fp_ctrl_toint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_fastpipe_0 = io_commit_uops_0_out_fp_ctrl_fastpipe; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_fma_0 = io_commit_uops_0_out_fp_ctrl_fma; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_div_0 = io_commit_uops_0_out_fp_ctrl_div; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_sqrt_0 = io_commit_uops_0_out_fp_ctrl_sqrt; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_wflags_0 = io_commit_uops_0_out_fp_ctrl_wflags; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_ctrl_vec_0 = io_commit_uops_0_out_fp_ctrl_vec; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_rob_idx_0 = io_commit_uops_0_out_rob_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ldq_idx_0 = io_commit_uops_0_out_ldq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_stq_idx_0 = io_commit_uops_0_out_stq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_rxq_idx_0 = io_commit_uops_0_out_rxq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_pdst_0 = io_commit_uops_0_out_pdst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs1_0 = io_commit_uops_0_out_prs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs2_0 = io_commit_uops_0_out_prs2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs3_0 = io_commit_uops_0_out_prs3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ppred_0 = io_commit_uops_0_out_ppred; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs1_busy_0 = io_commit_uops_0_out_prs1_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs2_busy_0 = io_commit_uops_0_out_prs2_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_prs3_busy_0 = io_commit_uops_0_out_prs3_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ppred_busy_0 = io_commit_uops_0_out_ppred_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_stale_pdst_0 = io_commit_uops_0_out_stale_pdst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_exception_0 = io_commit_uops_0_out_exception; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_exc_cause_0 = io_commit_uops_0_out_exc_cause; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_mem_cmd_0 = io_commit_uops_0_out_mem_cmd; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_mem_size_0 = io_commit_uops_0_out_mem_size; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_mem_signed_0 = io_commit_uops_0_out_mem_signed; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_uses_ldq_0 = io_commit_uops_0_out_uses_ldq; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_uses_stq_0 = io_commit_uops_0_out_uses_stq; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_is_unique_0 = io_commit_uops_0_out_is_unique; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_flush_on_commit_0 = io_commit_uops_0_out_flush_on_commit; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_csr_cmd_0 = io_commit_uops_0_out_csr_cmd; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ldst_is_rs1_0 = io_commit_uops_0_out_ldst_is_rs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_ldst_0 = io_commit_uops_0_out_ldst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_lrs1_0 = io_commit_uops_0_out_lrs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_lrs2_0 = io_commit_uops_0_out_lrs2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_lrs3_0 = io_commit_uops_0_out_lrs3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_dst_rtype_0 = io_commit_uops_0_out_dst_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_lrs1_rtype_0 = io_commit_uops_0_out_lrs1_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_lrs2_rtype_0 = io_commit_uops_0_out_lrs2_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_frs3_en_0 = io_commit_uops_0_out_frs3_en; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fcn_dw_0 = io_commit_uops_0_out_fcn_dw; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fcn_op_0 = io_commit_uops_0_out_fcn_op; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_val_0 = io_commit_uops_0_out_fp_val; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_rm_0 = io_commit_uops_0_out_fp_rm; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_fp_typ_0 = io_commit_uops_0_out_fp_typ; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_xcpt_pf_if_0 = io_commit_uops_0_out_xcpt_pf_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_xcpt_ae_if_0 = io_commit_uops_0_out_xcpt_ae_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_xcpt_ma_if_0 = io_commit_uops_0_out_xcpt_ma_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_bp_debug_if_0 = io_commit_uops_0_out_bp_debug_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_bp_xcpt_if_0 = io_commit_uops_0_out_bp_xcpt_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_0_debug_tsrc_0 = io_commit_uops_0_out_debug_tsrc; // @[rob.scala:199:7, :313:23]
wire io_commit_uops_0_out_taken; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_0_out_debug_fsrc; // @[rob.scala:313:23]
wire [31:0][31:0] _GEN_21 = {{rob_uop_31_inst}, {rob_uop_30_inst}, {rob_uop_29_inst}, {rob_uop_28_inst}, {rob_uop_27_inst}, {rob_uop_26_inst}, {rob_uop_25_inst}, {rob_uop_24_inst}, {rob_uop_23_inst}, {rob_uop_22_inst}, {rob_uop_21_inst}, {rob_uop_20_inst}, {rob_uop_19_inst}, {rob_uop_18_inst}, {rob_uop_17_inst}, {rob_uop_16_inst}, {rob_uop_15_inst}, {rob_uop_14_inst}, {rob_uop_13_inst}, {rob_uop_12_inst}, {rob_uop_11_inst}, {rob_uop_10_inst}, {rob_uop_9_inst}, {rob_uop_8_inst}, {rob_uop_7_inst}, {rob_uop_6_inst}, {rob_uop_5_inst}, {rob_uop_4_inst}, {rob_uop_3_inst}, {rob_uop_2_inst}, {rob_uop_1_inst}, {rob_uop_0_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_inst = _GEN_21[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][31:0] _GEN_22 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_debug_inst = _GEN_22[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_23 = {{rob_uop_31_is_rvc}, {rob_uop_30_is_rvc}, {rob_uop_29_is_rvc}, {rob_uop_28_is_rvc}, {rob_uop_27_is_rvc}, {rob_uop_26_is_rvc}, {rob_uop_25_is_rvc}, {rob_uop_24_is_rvc}, {rob_uop_23_is_rvc}, {rob_uop_22_is_rvc}, {rob_uop_21_is_rvc}, {rob_uop_20_is_rvc}, {rob_uop_19_is_rvc}, {rob_uop_18_is_rvc}, {rob_uop_17_is_rvc}, {rob_uop_16_is_rvc}, {rob_uop_15_is_rvc}, {rob_uop_14_is_rvc}, {rob_uop_13_is_rvc}, {rob_uop_12_is_rvc}, {rob_uop_11_is_rvc}, {rob_uop_10_is_rvc}, {rob_uop_9_is_rvc}, {rob_uop_8_is_rvc}, {rob_uop_7_is_rvc}, {rob_uop_6_is_rvc}, {rob_uop_5_is_rvc}, {rob_uop_4_is_rvc}, {rob_uop_3_is_rvc}, {rob_uop_2_is_rvc}, {rob_uop_1_is_rvc}, {rob_uop_0_is_rvc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_rvc = _GEN_23[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][39:0] _GEN_24 = {{rob_uop_31_debug_pc}, {rob_uop_30_debug_pc}, {rob_uop_29_debug_pc}, {rob_uop_28_debug_pc}, {rob_uop_27_debug_pc}, {rob_uop_26_debug_pc}, {rob_uop_25_debug_pc}, {rob_uop_24_debug_pc}, {rob_uop_23_debug_pc}, {rob_uop_22_debug_pc}, {rob_uop_21_debug_pc}, {rob_uop_20_debug_pc}, {rob_uop_19_debug_pc}, {rob_uop_18_debug_pc}, {rob_uop_17_debug_pc}, {rob_uop_16_debug_pc}, {rob_uop_15_debug_pc}, {rob_uop_14_debug_pc}, {rob_uop_13_debug_pc}, {rob_uop_12_debug_pc}, {rob_uop_11_debug_pc}, {rob_uop_10_debug_pc}, {rob_uop_9_debug_pc}, {rob_uop_8_debug_pc}, {rob_uop_7_debug_pc}, {rob_uop_6_debug_pc}, {rob_uop_5_debug_pc}, {rob_uop_4_debug_pc}, {rob_uop_3_debug_pc}, {rob_uop_2_debug_pc}, {rob_uop_1_debug_pc}, {rob_uop_0_debug_pc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_debug_pc = _GEN_24[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_25 = {{rob_uop_31_iq_type_0}, {rob_uop_30_iq_type_0}, {rob_uop_29_iq_type_0}, {rob_uop_28_iq_type_0}, {rob_uop_27_iq_type_0}, {rob_uop_26_iq_type_0}, {rob_uop_25_iq_type_0}, {rob_uop_24_iq_type_0}, {rob_uop_23_iq_type_0}, {rob_uop_22_iq_type_0}, {rob_uop_21_iq_type_0}, {rob_uop_20_iq_type_0}, {rob_uop_19_iq_type_0}, {rob_uop_18_iq_type_0}, {rob_uop_17_iq_type_0}, {rob_uop_16_iq_type_0}, {rob_uop_15_iq_type_0}, {rob_uop_14_iq_type_0}, {rob_uop_13_iq_type_0}, {rob_uop_12_iq_type_0}, {rob_uop_11_iq_type_0}, {rob_uop_10_iq_type_0}, {rob_uop_9_iq_type_0}, {rob_uop_8_iq_type_0}, {rob_uop_7_iq_type_0}, {rob_uop_6_iq_type_0}, {rob_uop_5_iq_type_0}, {rob_uop_4_iq_type_0}, {rob_uop_3_iq_type_0}, {rob_uop_2_iq_type_0}, {rob_uop_1_iq_type_0}, {rob_uop_0_iq_type_0}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iq_type_0 = _GEN_25[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_26 = {{rob_uop_31_iq_type_1}, {rob_uop_30_iq_type_1}, {rob_uop_29_iq_type_1}, {rob_uop_28_iq_type_1}, {rob_uop_27_iq_type_1}, {rob_uop_26_iq_type_1}, {rob_uop_25_iq_type_1}, {rob_uop_24_iq_type_1}, {rob_uop_23_iq_type_1}, {rob_uop_22_iq_type_1}, {rob_uop_21_iq_type_1}, {rob_uop_20_iq_type_1}, {rob_uop_19_iq_type_1}, {rob_uop_18_iq_type_1}, {rob_uop_17_iq_type_1}, {rob_uop_16_iq_type_1}, {rob_uop_15_iq_type_1}, {rob_uop_14_iq_type_1}, {rob_uop_13_iq_type_1}, {rob_uop_12_iq_type_1}, {rob_uop_11_iq_type_1}, {rob_uop_10_iq_type_1}, {rob_uop_9_iq_type_1}, {rob_uop_8_iq_type_1}, {rob_uop_7_iq_type_1}, {rob_uop_6_iq_type_1}, {rob_uop_5_iq_type_1}, {rob_uop_4_iq_type_1}, {rob_uop_3_iq_type_1}, {rob_uop_2_iq_type_1}, {rob_uop_1_iq_type_1}, {rob_uop_0_iq_type_1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iq_type_1 = _GEN_26[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_27 = {{rob_uop_31_iq_type_2}, {rob_uop_30_iq_type_2}, {rob_uop_29_iq_type_2}, {rob_uop_28_iq_type_2}, {rob_uop_27_iq_type_2}, {rob_uop_26_iq_type_2}, {rob_uop_25_iq_type_2}, {rob_uop_24_iq_type_2}, {rob_uop_23_iq_type_2}, {rob_uop_22_iq_type_2}, {rob_uop_21_iq_type_2}, {rob_uop_20_iq_type_2}, {rob_uop_19_iq_type_2}, {rob_uop_18_iq_type_2}, {rob_uop_17_iq_type_2}, {rob_uop_16_iq_type_2}, {rob_uop_15_iq_type_2}, {rob_uop_14_iq_type_2}, {rob_uop_13_iq_type_2}, {rob_uop_12_iq_type_2}, {rob_uop_11_iq_type_2}, {rob_uop_10_iq_type_2}, {rob_uop_9_iq_type_2}, {rob_uop_8_iq_type_2}, {rob_uop_7_iq_type_2}, {rob_uop_6_iq_type_2}, {rob_uop_5_iq_type_2}, {rob_uop_4_iq_type_2}, {rob_uop_3_iq_type_2}, {rob_uop_2_iq_type_2}, {rob_uop_1_iq_type_2}, {rob_uop_0_iq_type_2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iq_type_2 = _GEN_27[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_28 = {{rob_uop_31_iq_type_3}, {rob_uop_30_iq_type_3}, {rob_uop_29_iq_type_3}, {rob_uop_28_iq_type_3}, {rob_uop_27_iq_type_3}, {rob_uop_26_iq_type_3}, {rob_uop_25_iq_type_3}, {rob_uop_24_iq_type_3}, {rob_uop_23_iq_type_3}, {rob_uop_22_iq_type_3}, {rob_uop_21_iq_type_3}, {rob_uop_20_iq_type_3}, {rob_uop_19_iq_type_3}, {rob_uop_18_iq_type_3}, {rob_uop_17_iq_type_3}, {rob_uop_16_iq_type_3}, {rob_uop_15_iq_type_3}, {rob_uop_14_iq_type_3}, {rob_uop_13_iq_type_3}, {rob_uop_12_iq_type_3}, {rob_uop_11_iq_type_3}, {rob_uop_10_iq_type_3}, {rob_uop_9_iq_type_3}, {rob_uop_8_iq_type_3}, {rob_uop_7_iq_type_3}, {rob_uop_6_iq_type_3}, {rob_uop_5_iq_type_3}, {rob_uop_4_iq_type_3}, {rob_uop_3_iq_type_3}, {rob_uop_2_iq_type_3}, {rob_uop_1_iq_type_3}, {rob_uop_0_iq_type_3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iq_type_3 = _GEN_28[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_29 = {{rob_uop_31_fu_code_0}, {rob_uop_30_fu_code_0}, {rob_uop_29_fu_code_0}, {rob_uop_28_fu_code_0}, {rob_uop_27_fu_code_0}, {rob_uop_26_fu_code_0}, {rob_uop_25_fu_code_0}, {rob_uop_24_fu_code_0}, {rob_uop_23_fu_code_0}, {rob_uop_22_fu_code_0}, {rob_uop_21_fu_code_0}, {rob_uop_20_fu_code_0}, {rob_uop_19_fu_code_0}, {rob_uop_18_fu_code_0}, {rob_uop_17_fu_code_0}, {rob_uop_16_fu_code_0}, {rob_uop_15_fu_code_0}, {rob_uop_14_fu_code_0}, {rob_uop_13_fu_code_0}, {rob_uop_12_fu_code_0}, {rob_uop_11_fu_code_0}, {rob_uop_10_fu_code_0}, {rob_uop_9_fu_code_0}, {rob_uop_8_fu_code_0}, {rob_uop_7_fu_code_0}, {rob_uop_6_fu_code_0}, {rob_uop_5_fu_code_0}, {rob_uop_4_fu_code_0}, {rob_uop_3_fu_code_0}, {rob_uop_2_fu_code_0}, {rob_uop_1_fu_code_0}, {rob_uop_0_fu_code_0}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_0 = _GEN_29[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_30 = {{rob_uop_31_fu_code_1}, {rob_uop_30_fu_code_1}, {rob_uop_29_fu_code_1}, {rob_uop_28_fu_code_1}, {rob_uop_27_fu_code_1}, {rob_uop_26_fu_code_1}, {rob_uop_25_fu_code_1}, {rob_uop_24_fu_code_1}, {rob_uop_23_fu_code_1}, {rob_uop_22_fu_code_1}, {rob_uop_21_fu_code_1}, {rob_uop_20_fu_code_1}, {rob_uop_19_fu_code_1}, {rob_uop_18_fu_code_1}, {rob_uop_17_fu_code_1}, {rob_uop_16_fu_code_1}, {rob_uop_15_fu_code_1}, {rob_uop_14_fu_code_1}, {rob_uop_13_fu_code_1}, {rob_uop_12_fu_code_1}, {rob_uop_11_fu_code_1}, {rob_uop_10_fu_code_1}, {rob_uop_9_fu_code_1}, {rob_uop_8_fu_code_1}, {rob_uop_7_fu_code_1}, {rob_uop_6_fu_code_1}, {rob_uop_5_fu_code_1}, {rob_uop_4_fu_code_1}, {rob_uop_3_fu_code_1}, {rob_uop_2_fu_code_1}, {rob_uop_1_fu_code_1}, {rob_uop_0_fu_code_1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_1 = _GEN_30[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_31 = {{rob_uop_31_fu_code_2}, {rob_uop_30_fu_code_2}, {rob_uop_29_fu_code_2}, {rob_uop_28_fu_code_2}, {rob_uop_27_fu_code_2}, {rob_uop_26_fu_code_2}, {rob_uop_25_fu_code_2}, {rob_uop_24_fu_code_2}, {rob_uop_23_fu_code_2}, {rob_uop_22_fu_code_2}, {rob_uop_21_fu_code_2}, {rob_uop_20_fu_code_2}, {rob_uop_19_fu_code_2}, {rob_uop_18_fu_code_2}, {rob_uop_17_fu_code_2}, {rob_uop_16_fu_code_2}, {rob_uop_15_fu_code_2}, {rob_uop_14_fu_code_2}, {rob_uop_13_fu_code_2}, {rob_uop_12_fu_code_2}, {rob_uop_11_fu_code_2}, {rob_uop_10_fu_code_2}, {rob_uop_9_fu_code_2}, {rob_uop_8_fu_code_2}, {rob_uop_7_fu_code_2}, {rob_uop_6_fu_code_2}, {rob_uop_5_fu_code_2}, {rob_uop_4_fu_code_2}, {rob_uop_3_fu_code_2}, {rob_uop_2_fu_code_2}, {rob_uop_1_fu_code_2}, {rob_uop_0_fu_code_2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_2 = _GEN_31[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_32 = {{rob_uop_31_fu_code_3}, {rob_uop_30_fu_code_3}, {rob_uop_29_fu_code_3}, {rob_uop_28_fu_code_3}, {rob_uop_27_fu_code_3}, {rob_uop_26_fu_code_3}, {rob_uop_25_fu_code_3}, {rob_uop_24_fu_code_3}, {rob_uop_23_fu_code_3}, {rob_uop_22_fu_code_3}, {rob_uop_21_fu_code_3}, {rob_uop_20_fu_code_3}, {rob_uop_19_fu_code_3}, {rob_uop_18_fu_code_3}, {rob_uop_17_fu_code_3}, {rob_uop_16_fu_code_3}, {rob_uop_15_fu_code_3}, {rob_uop_14_fu_code_3}, {rob_uop_13_fu_code_3}, {rob_uop_12_fu_code_3}, {rob_uop_11_fu_code_3}, {rob_uop_10_fu_code_3}, {rob_uop_9_fu_code_3}, {rob_uop_8_fu_code_3}, {rob_uop_7_fu_code_3}, {rob_uop_6_fu_code_3}, {rob_uop_5_fu_code_3}, {rob_uop_4_fu_code_3}, {rob_uop_3_fu_code_3}, {rob_uop_2_fu_code_3}, {rob_uop_1_fu_code_3}, {rob_uop_0_fu_code_3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_3 = _GEN_32[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_33 = {{rob_uop_31_fu_code_4}, {rob_uop_30_fu_code_4}, {rob_uop_29_fu_code_4}, {rob_uop_28_fu_code_4}, {rob_uop_27_fu_code_4}, {rob_uop_26_fu_code_4}, {rob_uop_25_fu_code_4}, {rob_uop_24_fu_code_4}, {rob_uop_23_fu_code_4}, {rob_uop_22_fu_code_4}, {rob_uop_21_fu_code_4}, {rob_uop_20_fu_code_4}, {rob_uop_19_fu_code_4}, {rob_uop_18_fu_code_4}, {rob_uop_17_fu_code_4}, {rob_uop_16_fu_code_4}, {rob_uop_15_fu_code_4}, {rob_uop_14_fu_code_4}, {rob_uop_13_fu_code_4}, {rob_uop_12_fu_code_4}, {rob_uop_11_fu_code_4}, {rob_uop_10_fu_code_4}, {rob_uop_9_fu_code_4}, {rob_uop_8_fu_code_4}, {rob_uop_7_fu_code_4}, {rob_uop_6_fu_code_4}, {rob_uop_5_fu_code_4}, {rob_uop_4_fu_code_4}, {rob_uop_3_fu_code_4}, {rob_uop_2_fu_code_4}, {rob_uop_1_fu_code_4}, {rob_uop_0_fu_code_4}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_4 = _GEN_33[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_34 = {{rob_uop_31_fu_code_5}, {rob_uop_30_fu_code_5}, {rob_uop_29_fu_code_5}, {rob_uop_28_fu_code_5}, {rob_uop_27_fu_code_5}, {rob_uop_26_fu_code_5}, {rob_uop_25_fu_code_5}, {rob_uop_24_fu_code_5}, {rob_uop_23_fu_code_5}, {rob_uop_22_fu_code_5}, {rob_uop_21_fu_code_5}, {rob_uop_20_fu_code_5}, {rob_uop_19_fu_code_5}, {rob_uop_18_fu_code_5}, {rob_uop_17_fu_code_5}, {rob_uop_16_fu_code_5}, {rob_uop_15_fu_code_5}, {rob_uop_14_fu_code_5}, {rob_uop_13_fu_code_5}, {rob_uop_12_fu_code_5}, {rob_uop_11_fu_code_5}, {rob_uop_10_fu_code_5}, {rob_uop_9_fu_code_5}, {rob_uop_8_fu_code_5}, {rob_uop_7_fu_code_5}, {rob_uop_6_fu_code_5}, {rob_uop_5_fu_code_5}, {rob_uop_4_fu_code_5}, {rob_uop_3_fu_code_5}, {rob_uop_2_fu_code_5}, {rob_uop_1_fu_code_5}, {rob_uop_0_fu_code_5}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_5 = _GEN_34[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_35 = {{rob_uop_31_fu_code_6}, {rob_uop_30_fu_code_6}, {rob_uop_29_fu_code_6}, {rob_uop_28_fu_code_6}, {rob_uop_27_fu_code_6}, {rob_uop_26_fu_code_6}, {rob_uop_25_fu_code_6}, {rob_uop_24_fu_code_6}, {rob_uop_23_fu_code_6}, {rob_uop_22_fu_code_6}, {rob_uop_21_fu_code_6}, {rob_uop_20_fu_code_6}, {rob_uop_19_fu_code_6}, {rob_uop_18_fu_code_6}, {rob_uop_17_fu_code_6}, {rob_uop_16_fu_code_6}, {rob_uop_15_fu_code_6}, {rob_uop_14_fu_code_6}, {rob_uop_13_fu_code_6}, {rob_uop_12_fu_code_6}, {rob_uop_11_fu_code_6}, {rob_uop_10_fu_code_6}, {rob_uop_9_fu_code_6}, {rob_uop_8_fu_code_6}, {rob_uop_7_fu_code_6}, {rob_uop_6_fu_code_6}, {rob_uop_5_fu_code_6}, {rob_uop_4_fu_code_6}, {rob_uop_3_fu_code_6}, {rob_uop_2_fu_code_6}, {rob_uop_1_fu_code_6}, {rob_uop_0_fu_code_6}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_6 = _GEN_35[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_36 = {{rob_uop_31_fu_code_7}, {rob_uop_30_fu_code_7}, {rob_uop_29_fu_code_7}, {rob_uop_28_fu_code_7}, {rob_uop_27_fu_code_7}, {rob_uop_26_fu_code_7}, {rob_uop_25_fu_code_7}, {rob_uop_24_fu_code_7}, {rob_uop_23_fu_code_7}, {rob_uop_22_fu_code_7}, {rob_uop_21_fu_code_7}, {rob_uop_20_fu_code_7}, {rob_uop_19_fu_code_7}, {rob_uop_18_fu_code_7}, {rob_uop_17_fu_code_7}, {rob_uop_16_fu_code_7}, {rob_uop_15_fu_code_7}, {rob_uop_14_fu_code_7}, {rob_uop_13_fu_code_7}, {rob_uop_12_fu_code_7}, {rob_uop_11_fu_code_7}, {rob_uop_10_fu_code_7}, {rob_uop_9_fu_code_7}, {rob_uop_8_fu_code_7}, {rob_uop_7_fu_code_7}, {rob_uop_6_fu_code_7}, {rob_uop_5_fu_code_7}, {rob_uop_4_fu_code_7}, {rob_uop_3_fu_code_7}, {rob_uop_2_fu_code_7}, {rob_uop_1_fu_code_7}, {rob_uop_0_fu_code_7}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_7 = _GEN_36[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_37 = {{rob_uop_31_fu_code_8}, {rob_uop_30_fu_code_8}, {rob_uop_29_fu_code_8}, {rob_uop_28_fu_code_8}, {rob_uop_27_fu_code_8}, {rob_uop_26_fu_code_8}, {rob_uop_25_fu_code_8}, {rob_uop_24_fu_code_8}, {rob_uop_23_fu_code_8}, {rob_uop_22_fu_code_8}, {rob_uop_21_fu_code_8}, {rob_uop_20_fu_code_8}, {rob_uop_19_fu_code_8}, {rob_uop_18_fu_code_8}, {rob_uop_17_fu_code_8}, {rob_uop_16_fu_code_8}, {rob_uop_15_fu_code_8}, {rob_uop_14_fu_code_8}, {rob_uop_13_fu_code_8}, {rob_uop_12_fu_code_8}, {rob_uop_11_fu_code_8}, {rob_uop_10_fu_code_8}, {rob_uop_9_fu_code_8}, {rob_uop_8_fu_code_8}, {rob_uop_7_fu_code_8}, {rob_uop_6_fu_code_8}, {rob_uop_5_fu_code_8}, {rob_uop_4_fu_code_8}, {rob_uop_3_fu_code_8}, {rob_uop_2_fu_code_8}, {rob_uop_1_fu_code_8}, {rob_uop_0_fu_code_8}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_8 = _GEN_37[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_38 = {{rob_uop_31_fu_code_9}, {rob_uop_30_fu_code_9}, {rob_uop_29_fu_code_9}, {rob_uop_28_fu_code_9}, {rob_uop_27_fu_code_9}, {rob_uop_26_fu_code_9}, {rob_uop_25_fu_code_9}, {rob_uop_24_fu_code_9}, {rob_uop_23_fu_code_9}, {rob_uop_22_fu_code_9}, {rob_uop_21_fu_code_9}, {rob_uop_20_fu_code_9}, {rob_uop_19_fu_code_9}, {rob_uop_18_fu_code_9}, {rob_uop_17_fu_code_9}, {rob_uop_16_fu_code_9}, {rob_uop_15_fu_code_9}, {rob_uop_14_fu_code_9}, {rob_uop_13_fu_code_9}, {rob_uop_12_fu_code_9}, {rob_uop_11_fu_code_9}, {rob_uop_10_fu_code_9}, {rob_uop_9_fu_code_9}, {rob_uop_8_fu_code_9}, {rob_uop_7_fu_code_9}, {rob_uop_6_fu_code_9}, {rob_uop_5_fu_code_9}, {rob_uop_4_fu_code_9}, {rob_uop_3_fu_code_9}, {rob_uop_2_fu_code_9}, {rob_uop_1_fu_code_9}, {rob_uop_0_fu_code_9}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fu_code_9 = _GEN_38[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_39 = {{rob_uop_31_iw_issued}, {rob_uop_30_iw_issued}, {rob_uop_29_iw_issued}, {rob_uop_28_iw_issued}, {rob_uop_27_iw_issued}, {rob_uop_26_iw_issued}, {rob_uop_25_iw_issued}, {rob_uop_24_iw_issued}, {rob_uop_23_iw_issued}, {rob_uop_22_iw_issued}, {rob_uop_21_iw_issued}, {rob_uop_20_iw_issued}, {rob_uop_19_iw_issued}, {rob_uop_18_iw_issued}, {rob_uop_17_iw_issued}, {rob_uop_16_iw_issued}, {rob_uop_15_iw_issued}, {rob_uop_14_iw_issued}, {rob_uop_13_iw_issued}, {rob_uop_12_iw_issued}, {rob_uop_11_iw_issued}, {rob_uop_10_iw_issued}, {rob_uop_9_iw_issued}, {rob_uop_8_iw_issued}, {rob_uop_7_iw_issued}, {rob_uop_6_iw_issued}, {rob_uop_5_iw_issued}, {rob_uop_4_iw_issued}, {rob_uop_3_iw_issued}, {rob_uop_2_iw_issued}, {rob_uop_1_iw_issued}, {rob_uop_0_iw_issued}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_issued = _GEN_39[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_40 = {{rob_uop_31_iw_issued_partial_agen}, {rob_uop_30_iw_issued_partial_agen}, {rob_uop_29_iw_issued_partial_agen}, {rob_uop_28_iw_issued_partial_agen}, {rob_uop_27_iw_issued_partial_agen}, {rob_uop_26_iw_issued_partial_agen}, {rob_uop_25_iw_issued_partial_agen}, {rob_uop_24_iw_issued_partial_agen}, {rob_uop_23_iw_issued_partial_agen}, {rob_uop_22_iw_issued_partial_agen}, {rob_uop_21_iw_issued_partial_agen}, {rob_uop_20_iw_issued_partial_agen}, {rob_uop_19_iw_issued_partial_agen}, {rob_uop_18_iw_issued_partial_agen}, {rob_uop_17_iw_issued_partial_agen}, {rob_uop_16_iw_issued_partial_agen}, {rob_uop_15_iw_issued_partial_agen}, {rob_uop_14_iw_issued_partial_agen}, {rob_uop_13_iw_issued_partial_agen}, {rob_uop_12_iw_issued_partial_agen}, {rob_uop_11_iw_issued_partial_agen}, {rob_uop_10_iw_issued_partial_agen}, {rob_uop_9_iw_issued_partial_agen}, {rob_uop_8_iw_issued_partial_agen}, {rob_uop_7_iw_issued_partial_agen}, {rob_uop_6_iw_issued_partial_agen}, {rob_uop_5_iw_issued_partial_agen}, {rob_uop_4_iw_issued_partial_agen}, {rob_uop_3_iw_issued_partial_agen}, {rob_uop_2_iw_issued_partial_agen}, {rob_uop_1_iw_issued_partial_agen}, {rob_uop_0_iw_issued_partial_agen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_issued_partial_agen = _GEN_40[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_41 = {{rob_uop_31_iw_issued_partial_dgen}, {rob_uop_30_iw_issued_partial_dgen}, {rob_uop_29_iw_issued_partial_dgen}, {rob_uop_28_iw_issued_partial_dgen}, {rob_uop_27_iw_issued_partial_dgen}, {rob_uop_26_iw_issued_partial_dgen}, {rob_uop_25_iw_issued_partial_dgen}, {rob_uop_24_iw_issued_partial_dgen}, {rob_uop_23_iw_issued_partial_dgen}, {rob_uop_22_iw_issued_partial_dgen}, {rob_uop_21_iw_issued_partial_dgen}, {rob_uop_20_iw_issued_partial_dgen}, {rob_uop_19_iw_issued_partial_dgen}, {rob_uop_18_iw_issued_partial_dgen}, {rob_uop_17_iw_issued_partial_dgen}, {rob_uop_16_iw_issued_partial_dgen}, {rob_uop_15_iw_issued_partial_dgen}, {rob_uop_14_iw_issued_partial_dgen}, {rob_uop_13_iw_issued_partial_dgen}, {rob_uop_12_iw_issued_partial_dgen}, {rob_uop_11_iw_issued_partial_dgen}, {rob_uop_10_iw_issued_partial_dgen}, {rob_uop_9_iw_issued_partial_dgen}, {rob_uop_8_iw_issued_partial_dgen}, {rob_uop_7_iw_issued_partial_dgen}, {rob_uop_6_iw_issued_partial_dgen}, {rob_uop_5_iw_issued_partial_dgen}, {rob_uop_4_iw_issued_partial_dgen}, {rob_uop_3_iw_issued_partial_dgen}, {rob_uop_2_iw_issued_partial_dgen}, {rob_uop_1_iw_issued_partial_dgen}, {rob_uop_0_iw_issued_partial_dgen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_issued_partial_dgen = _GEN_41[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_42 = {{rob_uop_31_iw_p1_speculative_child}, {rob_uop_30_iw_p1_speculative_child}, {rob_uop_29_iw_p1_speculative_child}, {rob_uop_28_iw_p1_speculative_child}, {rob_uop_27_iw_p1_speculative_child}, {rob_uop_26_iw_p1_speculative_child}, {rob_uop_25_iw_p1_speculative_child}, {rob_uop_24_iw_p1_speculative_child}, {rob_uop_23_iw_p1_speculative_child}, {rob_uop_22_iw_p1_speculative_child}, {rob_uop_21_iw_p1_speculative_child}, {rob_uop_20_iw_p1_speculative_child}, {rob_uop_19_iw_p1_speculative_child}, {rob_uop_18_iw_p1_speculative_child}, {rob_uop_17_iw_p1_speculative_child}, {rob_uop_16_iw_p1_speculative_child}, {rob_uop_15_iw_p1_speculative_child}, {rob_uop_14_iw_p1_speculative_child}, {rob_uop_13_iw_p1_speculative_child}, {rob_uop_12_iw_p1_speculative_child}, {rob_uop_11_iw_p1_speculative_child}, {rob_uop_10_iw_p1_speculative_child}, {rob_uop_9_iw_p1_speculative_child}, {rob_uop_8_iw_p1_speculative_child}, {rob_uop_7_iw_p1_speculative_child}, {rob_uop_6_iw_p1_speculative_child}, {rob_uop_5_iw_p1_speculative_child}, {rob_uop_4_iw_p1_speculative_child}, {rob_uop_3_iw_p1_speculative_child}, {rob_uop_2_iw_p1_speculative_child}, {rob_uop_1_iw_p1_speculative_child}, {rob_uop_0_iw_p1_speculative_child}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_p1_speculative_child = _GEN_42[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_43 = {{rob_uop_31_iw_p2_speculative_child}, {rob_uop_30_iw_p2_speculative_child}, {rob_uop_29_iw_p2_speculative_child}, {rob_uop_28_iw_p2_speculative_child}, {rob_uop_27_iw_p2_speculative_child}, {rob_uop_26_iw_p2_speculative_child}, {rob_uop_25_iw_p2_speculative_child}, {rob_uop_24_iw_p2_speculative_child}, {rob_uop_23_iw_p2_speculative_child}, {rob_uop_22_iw_p2_speculative_child}, {rob_uop_21_iw_p2_speculative_child}, {rob_uop_20_iw_p2_speculative_child}, {rob_uop_19_iw_p2_speculative_child}, {rob_uop_18_iw_p2_speculative_child}, {rob_uop_17_iw_p2_speculative_child}, {rob_uop_16_iw_p2_speculative_child}, {rob_uop_15_iw_p2_speculative_child}, {rob_uop_14_iw_p2_speculative_child}, {rob_uop_13_iw_p2_speculative_child}, {rob_uop_12_iw_p2_speculative_child}, {rob_uop_11_iw_p2_speculative_child}, {rob_uop_10_iw_p2_speculative_child}, {rob_uop_9_iw_p2_speculative_child}, {rob_uop_8_iw_p2_speculative_child}, {rob_uop_7_iw_p2_speculative_child}, {rob_uop_6_iw_p2_speculative_child}, {rob_uop_5_iw_p2_speculative_child}, {rob_uop_4_iw_p2_speculative_child}, {rob_uop_3_iw_p2_speculative_child}, {rob_uop_2_iw_p2_speculative_child}, {rob_uop_1_iw_p2_speculative_child}, {rob_uop_0_iw_p2_speculative_child}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_p2_speculative_child = _GEN_43[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_44 = {{rob_uop_31_iw_p1_bypass_hint}, {rob_uop_30_iw_p1_bypass_hint}, {rob_uop_29_iw_p1_bypass_hint}, {rob_uop_28_iw_p1_bypass_hint}, {rob_uop_27_iw_p1_bypass_hint}, {rob_uop_26_iw_p1_bypass_hint}, {rob_uop_25_iw_p1_bypass_hint}, {rob_uop_24_iw_p1_bypass_hint}, {rob_uop_23_iw_p1_bypass_hint}, {rob_uop_22_iw_p1_bypass_hint}, {rob_uop_21_iw_p1_bypass_hint}, {rob_uop_20_iw_p1_bypass_hint}, {rob_uop_19_iw_p1_bypass_hint}, {rob_uop_18_iw_p1_bypass_hint}, {rob_uop_17_iw_p1_bypass_hint}, {rob_uop_16_iw_p1_bypass_hint}, {rob_uop_15_iw_p1_bypass_hint}, {rob_uop_14_iw_p1_bypass_hint}, {rob_uop_13_iw_p1_bypass_hint}, {rob_uop_12_iw_p1_bypass_hint}, {rob_uop_11_iw_p1_bypass_hint}, {rob_uop_10_iw_p1_bypass_hint}, {rob_uop_9_iw_p1_bypass_hint}, {rob_uop_8_iw_p1_bypass_hint}, {rob_uop_7_iw_p1_bypass_hint}, {rob_uop_6_iw_p1_bypass_hint}, {rob_uop_5_iw_p1_bypass_hint}, {rob_uop_4_iw_p1_bypass_hint}, {rob_uop_3_iw_p1_bypass_hint}, {rob_uop_2_iw_p1_bypass_hint}, {rob_uop_1_iw_p1_bypass_hint}, {rob_uop_0_iw_p1_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_p1_bypass_hint = _GEN_44[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_45 = {{rob_uop_31_iw_p2_bypass_hint}, {rob_uop_30_iw_p2_bypass_hint}, {rob_uop_29_iw_p2_bypass_hint}, {rob_uop_28_iw_p2_bypass_hint}, {rob_uop_27_iw_p2_bypass_hint}, {rob_uop_26_iw_p2_bypass_hint}, {rob_uop_25_iw_p2_bypass_hint}, {rob_uop_24_iw_p2_bypass_hint}, {rob_uop_23_iw_p2_bypass_hint}, {rob_uop_22_iw_p2_bypass_hint}, {rob_uop_21_iw_p2_bypass_hint}, {rob_uop_20_iw_p2_bypass_hint}, {rob_uop_19_iw_p2_bypass_hint}, {rob_uop_18_iw_p2_bypass_hint}, {rob_uop_17_iw_p2_bypass_hint}, {rob_uop_16_iw_p2_bypass_hint}, {rob_uop_15_iw_p2_bypass_hint}, {rob_uop_14_iw_p2_bypass_hint}, {rob_uop_13_iw_p2_bypass_hint}, {rob_uop_12_iw_p2_bypass_hint}, {rob_uop_11_iw_p2_bypass_hint}, {rob_uop_10_iw_p2_bypass_hint}, {rob_uop_9_iw_p2_bypass_hint}, {rob_uop_8_iw_p2_bypass_hint}, {rob_uop_7_iw_p2_bypass_hint}, {rob_uop_6_iw_p2_bypass_hint}, {rob_uop_5_iw_p2_bypass_hint}, {rob_uop_4_iw_p2_bypass_hint}, {rob_uop_3_iw_p2_bypass_hint}, {rob_uop_2_iw_p2_bypass_hint}, {rob_uop_1_iw_p2_bypass_hint}, {rob_uop_0_iw_p2_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_p2_bypass_hint = _GEN_45[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_46 = {{rob_uop_31_iw_p3_bypass_hint}, {rob_uop_30_iw_p3_bypass_hint}, {rob_uop_29_iw_p3_bypass_hint}, {rob_uop_28_iw_p3_bypass_hint}, {rob_uop_27_iw_p3_bypass_hint}, {rob_uop_26_iw_p3_bypass_hint}, {rob_uop_25_iw_p3_bypass_hint}, {rob_uop_24_iw_p3_bypass_hint}, {rob_uop_23_iw_p3_bypass_hint}, {rob_uop_22_iw_p3_bypass_hint}, {rob_uop_21_iw_p3_bypass_hint}, {rob_uop_20_iw_p3_bypass_hint}, {rob_uop_19_iw_p3_bypass_hint}, {rob_uop_18_iw_p3_bypass_hint}, {rob_uop_17_iw_p3_bypass_hint}, {rob_uop_16_iw_p3_bypass_hint}, {rob_uop_15_iw_p3_bypass_hint}, {rob_uop_14_iw_p3_bypass_hint}, {rob_uop_13_iw_p3_bypass_hint}, {rob_uop_12_iw_p3_bypass_hint}, {rob_uop_11_iw_p3_bypass_hint}, {rob_uop_10_iw_p3_bypass_hint}, {rob_uop_9_iw_p3_bypass_hint}, {rob_uop_8_iw_p3_bypass_hint}, {rob_uop_7_iw_p3_bypass_hint}, {rob_uop_6_iw_p3_bypass_hint}, {rob_uop_5_iw_p3_bypass_hint}, {rob_uop_4_iw_p3_bypass_hint}, {rob_uop_3_iw_p3_bypass_hint}, {rob_uop_2_iw_p3_bypass_hint}, {rob_uop_1_iw_p3_bypass_hint}, {rob_uop_0_iw_p3_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_iw_p3_bypass_hint = _GEN_46[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_47 = {{rob_uop_31_dis_col_sel}, {rob_uop_30_dis_col_sel}, {rob_uop_29_dis_col_sel}, {rob_uop_28_dis_col_sel}, {rob_uop_27_dis_col_sel}, {rob_uop_26_dis_col_sel}, {rob_uop_25_dis_col_sel}, {rob_uop_24_dis_col_sel}, {rob_uop_23_dis_col_sel}, {rob_uop_22_dis_col_sel}, {rob_uop_21_dis_col_sel}, {rob_uop_20_dis_col_sel}, {rob_uop_19_dis_col_sel}, {rob_uop_18_dis_col_sel}, {rob_uop_17_dis_col_sel}, {rob_uop_16_dis_col_sel}, {rob_uop_15_dis_col_sel}, {rob_uop_14_dis_col_sel}, {rob_uop_13_dis_col_sel}, {rob_uop_12_dis_col_sel}, {rob_uop_11_dis_col_sel}, {rob_uop_10_dis_col_sel}, {rob_uop_9_dis_col_sel}, {rob_uop_8_dis_col_sel}, {rob_uop_7_dis_col_sel}, {rob_uop_6_dis_col_sel}, {rob_uop_5_dis_col_sel}, {rob_uop_4_dis_col_sel}, {rob_uop_3_dis_col_sel}, {rob_uop_2_dis_col_sel}, {rob_uop_1_dis_col_sel}, {rob_uop_0_dis_col_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_dis_col_sel = _GEN_47[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][11:0] _GEN_48 = {{rob_uop_31_br_mask}, {rob_uop_30_br_mask}, {rob_uop_29_br_mask}, {rob_uop_28_br_mask}, {rob_uop_27_br_mask}, {rob_uop_26_br_mask}, {rob_uop_25_br_mask}, {rob_uop_24_br_mask}, {rob_uop_23_br_mask}, {rob_uop_22_br_mask}, {rob_uop_21_br_mask}, {rob_uop_20_br_mask}, {rob_uop_19_br_mask}, {rob_uop_18_br_mask}, {rob_uop_17_br_mask}, {rob_uop_16_br_mask}, {rob_uop_15_br_mask}, {rob_uop_14_br_mask}, {rob_uop_13_br_mask}, {rob_uop_12_br_mask}, {rob_uop_11_br_mask}, {rob_uop_10_br_mask}, {rob_uop_9_br_mask}, {rob_uop_8_br_mask}, {rob_uop_7_br_mask}, {rob_uop_6_br_mask}, {rob_uop_5_br_mask}, {rob_uop_4_br_mask}, {rob_uop_3_br_mask}, {rob_uop_2_br_mask}, {rob_uop_1_br_mask}, {rob_uop_0_br_mask}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_br_mask = _GEN_48[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_49 = {{rob_uop_31_br_tag}, {rob_uop_30_br_tag}, {rob_uop_29_br_tag}, {rob_uop_28_br_tag}, {rob_uop_27_br_tag}, {rob_uop_26_br_tag}, {rob_uop_25_br_tag}, {rob_uop_24_br_tag}, {rob_uop_23_br_tag}, {rob_uop_22_br_tag}, {rob_uop_21_br_tag}, {rob_uop_20_br_tag}, {rob_uop_19_br_tag}, {rob_uop_18_br_tag}, {rob_uop_17_br_tag}, {rob_uop_16_br_tag}, {rob_uop_15_br_tag}, {rob_uop_14_br_tag}, {rob_uop_13_br_tag}, {rob_uop_12_br_tag}, {rob_uop_11_br_tag}, {rob_uop_10_br_tag}, {rob_uop_9_br_tag}, {rob_uop_8_br_tag}, {rob_uop_7_br_tag}, {rob_uop_6_br_tag}, {rob_uop_5_br_tag}, {rob_uop_4_br_tag}, {rob_uop_3_br_tag}, {rob_uop_2_br_tag}, {rob_uop_1_br_tag}, {rob_uop_0_br_tag}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_br_tag = _GEN_49[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_50 = {{rob_uop_31_br_type}, {rob_uop_30_br_type}, {rob_uop_29_br_type}, {rob_uop_28_br_type}, {rob_uop_27_br_type}, {rob_uop_26_br_type}, {rob_uop_25_br_type}, {rob_uop_24_br_type}, {rob_uop_23_br_type}, {rob_uop_22_br_type}, {rob_uop_21_br_type}, {rob_uop_20_br_type}, {rob_uop_19_br_type}, {rob_uop_18_br_type}, {rob_uop_17_br_type}, {rob_uop_16_br_type}, {rob_uop_15_br_type}, {rob_uop_14_br_type}, {rob_uop_13_br_type}, {rob_uop_12_br_type}, {rob_uop_11_br_type}, {rob_uop_10_br_type}, {rob_uop_9_br_type}, {rob_uop_8_br_type}, {rob_uop_7_br_type}, {rob_uop_6_br_type}, {rob_uop_5_br_type}, {rob_uop_4_br_type}, {rob_uop_3_br_type}, {rob_uop_2_br_type}, {rob_uop_1_br_type}, {rob_uop_0_br_type}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_br_type = _GEN_50[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_51 = {{rob_uop_31_is_sfb}, {rob_uop_30_is_sfb}, {rob_uop_29_is_sfb}, {rob_uop_28_is_sfb}, {rob_uop_27_is_sfb}, {rob_uop_26_is_sfb}, {rob_uop_25_is_sfb}, {rob_uop_24_is_sfb}, {rob_uop_23_is_sfb}, {rob_uop_22_is_sfb}, {rob_uop_21_is_sfb}, {rob_uop_20_is_sfb}, {rob_uop_19_is_sfb}, {rob_uop_18_is_sfb}, {rob_uop_17_is_sfb}, {rob_uop_16_is_sfb}, {rob_uop_15_is_sfb}, {rob_uop_14_is_sfb}, {rob_uop_13_is_sfb}, {rob_uop_12_is_sfb}, {rob_uop_11_is_sfb}, {rob_uop_10_is_sfb}, {rob_uop_9_is_sfb}, {rob_uop_8_is_sfb}, {rob_uop_7_is_sfb}, {rob_uop_6_is_sfb}, {rob_uop_5_is_sfb}, {rob_uop_4_is_sfb}, {rob_uop_3_is_sfb}, {rob_uop_2_is_sfb}, {rob_uop_1_is_sfb}, {rob_uop_0_is_sfb}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_sfb = _GEN_51[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_52 = {{rob_uop_31_is_fence}, {rob_uop_30_is_fence}, {rob_uop_29_is_fence}, {rob_uop_28_is_fence}, {rob_uop_27_is_fence}, {rob_uop_26_is_fence}, {rob_uop_25_is_fence}, {rob_uop_24_is_fence}, {rob_uop_23_is_fence}, {rob_uop_22_is_fence}, {rob_uop_21_is_fence}, {rob_uop_20_is_fence}, {rob_uop_19_is_fence}, {rob_uop_18_is_fence}, {rob_uop_17_is_fence}, {rob_uop_16_is_fence}, {rob_uop_15_is_fence}, {rob_uop_14_is_fence}, {rob_uop_13_is_fence}, {rob_uop_12_is_fence}, {rob_uop_11_is_fence}, {rob_uop_10_is_fence}, {rob_uop_9_is_fence}, {rob_uop_8_is_fence}, {rob_uop_7_is_fence}, {rob_uop_6_is_fence}, {rob_uop_5_is_fence}, {rob_uop_4_is_fence}, {rob_uop_3_is_fence}, {rob_uop_2_is_fence}, {rob_uop_1_is_fence}, {rob_uop_0_is_fence}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_fence = _GEN_52[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_53 = {{rob_uop_31_is_sfence}, {rob_uop_30_is_sfence}, {rob_uop_29_is_sfence}, {rob_uop_28_is_sfence}, {rob_uop_27_is_sfence}, {rob_uop_26_is_sfence}, {rob_uop_25_is_sfence}, {rob_uop_24_is_sfence}, {rob_uop_23_is_sfence}, {rob_uop_22_is_sfence}, {rob_uop_21_is_sfence}, {rob_uop_20_is_sfence}, {rob_uop_19_is_sfence}, {rob_uop_18_is_sfence}, {rob_uop_17_is_sfence}, {rob_uop_16_is_sfence}, {rob_uop_15_is_sfence}, {rob_uop_14_is_sfence}, {rob_uop_13_is_sfence}, {rob_uop_12_is_sfence}, {rob_uop_11_is_sfence}, {rob_uop_10_is_sfence}, {rob_uop_9_is_sfence}, {rob_uop_8_is_sfence}, {rob_uop_7_is_sfence}, {rob_uop_6_is_sfence}, {rob_uop_5_is_sfence}, {rob_uop_4_is_sfence}, {rob_uop_3_is_sfence}, {rob_uop_2_is_sfence}, {rob_uop_1_is_sfence}, {rob_uop_0_is_sfence}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_sfence = _GEN_53[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_54 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_amo = _GEN_54[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_55 = {{rob_uop_31_is_eret}, {rob_uop_30_is_eret}, {rob_uop_29_is_eret}, {rob_uop_28_is_eret}, {rob_uop_27_is_eret}, {rob_uop_26_is_eret}, {rob_uop_25_is_eret}, {rob_uop_24_is_eret}, {rob_uop_23_is_eret}, {rob_uop_22_is_eret}, {rob_uop_21_is_eret}, {rob_uop_20_is_eret}, {rob_uop_19_is_eret}, {rob_uop_18_is_eret}, {rob_uop_17_is_eret}, {rob_uop_16_is_eret}, {rob_uop_15_is_eret}, {rob_uop_14_is_eret}, {rob_uop_13_is_eret}, {rob_uop_12_is_eret}, {rob_uop_11_is_eret}, {rob_uop_10_is_eret}, {rob_uop_9_is_eret}, {rob_uop_8_is_eret}, {rob_uop_7_is_eret}, {rob_uop_6_is_eret}, {rob_uop_5_is_eret}, {rob_uop_4_is_eret}, {rob_uop_3_is_eret}, {rob_uop_2_is_eret}, {rob_uop_1_is_eret}, {rob_uop_0_is_eret}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_eret = _GEN_55[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_56 = {{rob_uop_31_is_sys_pc2epc}, {rob_uop_30_is_sys_pc2epc}, {rob_uop_29_is_sys_pc2epc}, {rob_uop_28_is_sys_pc2epc}, {rob_uop_27_is_sys_pc2epc}, {rob_uop_26_is_sys_pc2epc}, {rob_uop_25_is_sys_pc2epc}, {rob_uop_24_is_sys_pc2epc}, {rob_uop_23_is_sys_pc2epc}, {rob_uop_22_is_sys_pc2epc}, {rob_uop_21_is_sys_pc2epc}, {rob_uop_20_is_sys_pc2epc}, {rob_uop_19_is_sys_pc2epc}, {rob_uop_18_is_sys_pc2epc}, {rob_uop_17_is_sys_pc2epc}, {rob_uop_16_is_sys_pc2epc}, {rob_uop_15_is_sys_pc2epc}, {rob_uop_14_is_sys_pc2epc}, {rob_uop_13_is_sys_pc2epc}, {rob_uop_12_is_sys_pc2epc}, {rob_uop_11_is_sys_pc2epc}, {rob_uop_10_is_sys_pc2epc}, {rob_uop_9_is_sys_pc2epc}, {rob_uop_8_is_sys_pc2epc}, {rob_uop_7_is_sys_pc2epc}, {rob_uop_6_is_sys_pc2epc}, {rob_uop_5_is_sys_pc2epc}, {rob_uop_4_is_sys_pc2epc}, {rob_uop_3_is_sys_pc2epc}, {rob_uop_2_is_sys_pc2epc}, {rob_uop_1_is_sys_pc2epc}, {rob_uop_0_is_sys_pc2epc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_sys_pc2epc = _GEN_56[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_57 = {{rob_uop_31_is_rocc}, {rob_uop_30_is_rocc}, {rob_uop_29_is_rocc}, {rob_uop_28_is_rocc}, {rob_uop_27_is_rocc}, {rob_uop_26_is_rocc}, {rob_uop_25_is_rocc}, {rob_uop_24_is_rocc}, {rob_uop_23_is_rocc}, {rob_uop_22_is_rocc}, {rob_uop_21_is_rocc}, {rob_uop_20_is_rocc}, {rob_uop_19_is_rocc}, {rob_uop_18_is_rocc}, {rob_uop_17_is_rocc}, {rob_uop_16_is_rocc}, {rob_uop_15_is_rocc}, {rob_uop_14_is_rocc}, {rob_uop_13_is_rocc}, {rob_uop_12_is_rocc}, {rob_uop_11_is_rocc}, {rob_uop_10_is_rocc}, {rob_uop_9_is_rocc}, {rob_uop_8_is_rocc}, {rob_uop_7_is_rocc}, {rob_uop_6_is_rocc}, {rob_uop_5_is_rocc}, {rob_uop_4_is_rocc}, {rob_uop_3_is_rocc}, {rob_uop_2_is_rocc}, {rob_uop_1_is_rocc}, {rob_uop_0_is_rocc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_rocc = _GEN_57[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_58 = {{rob_uop_31_is_mov}, {rob_uop_30_is_mov}, {rob_uop_29_is_mov}, {rob_uop_28_is_mov}, {rob_uop_27_is_mov}, {rob_uop_26_is_mov}, {rob_uop_25_is_mov}, {rob_uop_24_is_mov}, {rob_uop_23_is_mov}, {rob_uop_22_is_mov}, {rob_uop_21_is_mov}, {rob_uop_20_is_mov}, {rob_uop_19_is_mov}, {rob_uop_18_is_mov}, {rob_uop_17_is_mov}, {rob_uop_16_is_mov}, {rob_uop_15_is_mov}, {rob_uop_14_is_mov}, {rob_uop_13_is_mov}, {rob_uop_12_is_mov}, {rob_uop_11_is_mov}, {rob_uop_10_is_mov}, {rob_uop_9_is_mov}, {rob_uop_8_is_mov}, {rob_uop_7_is_mov}, {rob_uop_6_is_mov}, {rob_uop_5_is_mov}, {rob_uop_4_is_mov}, {rob_uop_3_is_mov}, {rob_uop_2_is_mov}, {rob_uop_1_is_mov}, {rob_uop_0_is_mov}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_mov = _GEN_58[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_59 = {{rob_uop_31_edge_inst}, {rob_uop_30_edge_inst}, {rob_uop_29_edge_inst}, {rob_uop_28_edge_inst}, {rob_uop_27_edge_inst}, {rob_uop_26_edge_inst}, {rob_uop_25_edge_inst}, {rob_uop_24_edge_inst}, {rob_uop_23_edge_inst}, {rob_uop_22_edge_inst}, {rob_uop_21_edge_inst}, {rob_uop_20_edge_inst}, {rob_uop_19_edge_inst}, {rob_uop_18_edge_inst}, {rob_uop_17_edge_inst}, {rob_uop_16_edge_inst}, {rob_uop_15_edge_inst}, {rob_uop_14_edge_inst}, {rob_uop_13_edge_inst}, {rob_uop_12_edge_inst}, {rob_uop_11_edge_inst}, {rob_uop_10_edge_inst}, {rob_uop_9_edge_inst}, {rob_uop_8_edge_inst}, {rob_uop_7_edge_inst}, {rob_uop_6_edge_inst}, {rob_uop_5_edge_inst}, {rob_uop_4_edge_inst}, {rob_uop_3_edge_inst}, {rob_uop_2_edge_inst}, {rob_uop_1_edge_inst}, {rob_uop_0_edge_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_edge_inst = _GEN_59[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_60 = {{rob_uop_31_pc_lob}, {rob_uop_30_pc_lob}, {rob_uop_29_pc_lob}, {rob_uop_28_pc_lob}, {rob_uop_27_pc_lob}, {rob_uop_26_pc_lob}, {rob_uop_25_pc_lob}, {rob_uop_24_pc_lob}, {rob_uop_23_pc_lob}, {rob_uop_22_pc_lob}, {rob_uop_21_pc_lob}, {rob_uop_20_pc_lob}, {rob_uop_19_pc_lob}, {rob_uop_18_pc_lob}, {rob_uop_17_pc_lob}, {rob_uop_16_pc_lob}, {rob_uop_15_pc_lob}, {rob_uop_14_pc_lob}, {rob_uop_13_pc_lob}, {rob_uop_12_pc_lob}, {rob_uop_11_pc_lob}, {rob_uop_10_pc_lob}, {rob_uop_9_pc_lob}, {rob_uop_8_pc_lob}, {rob_uop_7_pc_lob}, {rob_uop_6_pc_lob}, {rob_uop_5_pc_lob}, {rob_uop_4_pc_lob}, {rob_uop_3_pc_lob}, {rob_uop_2_pc_lob}, {rob_uop_1_pc_lob}, {rob_uop_0_pc_lob}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_pc_lob = _GEN_60[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_61 = {{rob_uop_31_taken}, {rob_uop_30_taken}, {rob_uop_29_taken}, {rob_uop_28_taken}, {rob_uop_27_taken}, {rob_uop_26_taken}, {rob_uop_25_taken}, {rob_uop_24_taken}, {rob_uop_23_taken}, {rob_uop_22_taken}, {rob_uop_21_taken}, {rob_uop_20_taken}, {rob_uop_19_taken}, {rob_uop_18_taken}, {rob_uop_17_taken}, {rob_uop_16_taken}, {rob_uop_15_taken}, {rob_uop_14_taken}, {rob_uop_13_taken}, {rob_uop_12_taken}, {rob_uop_11_taken}, {rob_uop_10_taken}, {rob_uop_9_taken}, {rob_uop_8_taken}, {rob_uop_7_taken}, {rob_uop_6_taken}, {rob_uop_5_taken}, {rob_uop_4_taken}, {rob_uop_3_taken}, {rob_uop_2_taken}, {rob_uop_1_taken}, {rob_uop_0_taken}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_taken = _GEN_61[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_62 = {{rob_uop_31_imm_rename}, {rob_uop_30_imm_rename}, {rob_uop_29_imm_rename}, {rob_uop_28_imm_rename}, {rob_uop_27_imm_rename}, {rob_uop_26_imm_rename}, {rob_uop_25_imm_rename}, {rob_uop_24_imm_rename}, {rob_uop_23_imm_rename}, {rob_uop_22_imm_rename}, {rob_uop_21_imm_rename}, {rob_uop_20_imm_rename}, {rob_uop_19_imm_rename}, {rob_uop_18_imm_rename}, {rob_uop_17_imm_rename}, {rob_uop_16_imm_rename}, {rob_uop_15_imm_rename}, {rob_uop_14_imm_rename}, {rob_uop_13_imm_rename}, {rob_uop_12_imm_rename}, {rob_uop_11_imm_rename}, {rob_uop_10_imm_rename}, {rob_uop_9_imm_rename}, {rob_uop_8_imm_rename}, {rob_uop_7_imm_rename}, {rob_uop_6_imm_rename}, {rob_uop_5_imm_rename}, {rob_uop_4_imm_rename}, {rob_uop_3_imm_rename}, {rob_uop_2_imm_rename}, {rob_uop_1_imm_rename}, {rob_uop_0_imm_rename}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_imm_rename = _GEN_62[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_63 = {{rob_uop_31_imm_sel}, {rob_uop_30_imm_sel}, {rob_uop_29_imm_sel}, {rob_uop_28_imm_sel}, {rob_uop_27_imm_sel}, {rob_uop_26_imm_sel}, {rob_uop_25_imm_sel}, {rob_uop_24_imm_sel}, {rob_uop_23_imm_sel}, {rob_uop_22_imm_sel}, {rob_uop_21_imm_sel}, {rob_uop_20_imm_sel}, {rob_uop_19_imm_sel}, {rob_uop_18_imm_sel}, {rob_uop_17_imm_sel}, {rob_uop_16_imm_sel}, {rob_uop_15_imm_sel}, {rob_uop_14_imm_sel}, {rob_uop_13_imm_sel}, {rob_uop_12_imm_sel}, {rob_uop_11_imm_sel}, {rob_uop_10_imm_sel}, {rob_uop_9_imm_sel}, {rob_uop_8_imm_sel}, {rob_uop_7_imm_sel}, {rob_uop_6_imm_sel}, {rob_uop_5_imm_sel}, {rob_uop_4_imm_sel}, {rob_uop_3_imm_sel}, {rob_uop_2_imm_sel}, {rob_uop_1_imm_sel}, {rob_uop_0_imm_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_imm_sel = _GEN_63[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_64 = {{rob_uop_31_pimm}, {rob_uop_30_pimm}, {rob_uop_29_pimm}, {rob_uop_28_pimm}, {rob_uop_27_pimm}, {rob_uop_26_pimm}, {rob_uop_25_pimm}, {rob_uop_24_pimm}, {rob_uop_23_pimm}, {rob_uop_22_pimm}, {rob_uop_21_pimm}, {rob_uop_20_pimm}, {rob_uop_19_pimm}, {rob_uop_18_pimm}, {rob_uop_17_pimm}, {rob_uop_16_pimm}, {rob_uop_15_pimm}, {rob_uop_14_pimm}, {rob_uop_13_pimm}, {rob_uop_12_pimm}, {rob_uop_11_pimm}, {rob_uop_10_pimm}, {rob_uop_9_pimm}, {rob_uop_8_pimm}, {rob_uop_7_pimm}, {rob_uop_6_pimm}, {rob_uop_5_pimm}, {rob_uop_4_pimm}, {rob_uop_3_pimm}, {rob_uop_2_pimm}, {rob_uop_1_pimm}, {rob_uop_0_pimm}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_pimm = _GEN_64[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][19:0] _GEN_65 = {{rob_uop_31_imm_packed}, {rob_uop_30_imm_packed}, {rob_uop_29_imm_packed}, {rob_uop_28_imm_packed}, {rob_uop_27_imm_packed}, {rob_uop_26_imm_packed}, {rob_uop_25_imm_packed}, {rob_uop_24_imm_packed}, {rob_uop_23_imm_packed}, {rob_uop_22_imm_packed}, {rob_uop_21_imm_packed}, {rob_uop_20_imm_packed}, {rob_uop_19_imm_packed}, {rob_uop_18_imm_packed}, {rob_uop_17_imm_packed}, {rob_uop_16_imm_packed}, {rob_uop_15_imm_packed}, {rob_uop_14_imm_packed}, {rob_uop_13_imm_packed}, {rob_uop_12_imm_packed}, {rob_uop_11_imm_packed}, {rob_uop_10_imm_packed}, {rob_uop_9_imm_packed}, {rob_uop_8_imm_packed}, {rob_uop_7_imm_packed}, {rob_uop_6_imm_packed}, {rob_uop_5_imm_packed}, {rob_uop_4_imm_packed}, {rob_uop_3_imm_packed}, {rob_uop_2_imm_packed}, {rob_uop_1_imm_packed}, {rob_uop_0_imm_packed}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_imm_packed = _GEN_65[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_66 = {{rob_uop_31_op1_sel}, {rob_uop_30_op1_sel}, {rob_uop_29_op1_sel}, {rob_uop_28_op1_sel}, {rob_uop_27_op1_sel}, {rob_uop_26_op1_sel}, {rob_uop_25_op1_sel}, {rob_uop_24_op1_sel}, {rob_uop_23_op1_sel}, {rob_uop_22_op1_sel}, {rob_uop_21_op1_sel}, {rob_uop_20_op1_sel}, {rob_uop_19_op1_sel}, {rob_uop_18_op1_sel}, {rob_uop_17_op1_sel}, {rob_uop_16_op1_sel}, {rob_uop_15_op1_sel}, {rob_uop_14_op1_sel}, {rob_uop_13_op1_sel}, {rob_uop_12_op1_sel}, {rob_uop_11_op1_sel}, {rob_uop_10_op1_sel}, {rob_uop_9_op1_sel}, {rob_uop_8_op1_sel}, {rob_uop_7_op1_sel}, {rob_uop_6_op1_sel}, {rob_uop_5_op1_sel}, {rob_uop_4_op1_sel}, {rob_uop_3_op1_sel}, {rob_uop_2_op1_sel}, {rob_uop_1_op1_sel}, {rob_uop_0_op1_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_op1_sel = _GEN_66[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_67 = {{rob_uop_31_op2_sel}, {rob_uop_30_op2_sel}, {rob_uop_29_op2_sel}, {rob_uop_28_op2_sel}, {rob_uop_27_op2_sel}, {rob_uop_26_op2_sel}, {rob_uop_25_op2_sel}, {rob_uop_24_op2_sel}, {rob_uop_23_op2_sel}, {rob_uop_22_op2_sel}, {rob_uop_21_op2_sel}, {rob_uop_20_op2_sel}, {rob_uop_19_op2_sel}, {rob_uop_18_op2_sel}, {rob_uop_17_op2_sel}, {rob_uop_16_op2_sel}, {rob_uop_15_op2_sel}, {rob_uop_14_op2_sel}, {rob_uop_13_op2_sel}, {rob_uop_12_op2_sel}, {rob_uop_11_op2_sel}, {rob_uop_10_op2_sel}, {rob_uop_9_op2_sel}, {rob_uop_8_op2_sel}, {rob_uop_7_op2_sel}, {rob_uop_6_op2_sel}, {rob_uop_5_op2_sel}, {rob_uop_4_op2_sel}, {rob_uop_3_op2_sel}, {rob_uop_2_op2_sel}, {rob_uop_1_op2_sel}, {rob_uop_0_op2_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_op2_sel = _GEN_67[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_68 = {{rob_uop_31_fp_ctrl_ldst}, {rob_uop_30_fp_ctrl_ldst}, {rob_uop_29_fp_ctrl_ldst}, {rob_uop_28_fp_ctrl_ldst}, {rob_uop_27_fp_ctrl_ldst}, {rob_uop_26_fp_ctrl_ldst}, {rob_uop_25_fp_ctrl_ldst}, {rob_uop_24_fp_ctrl_ldst}, {rob_uop_23_fp_ctrl_ldst}, {rob_uop_22_fp_ctrl_ldst}, {rob_uop_21_fp_ctrl_ldst}, {rob_uop_20_fp_ctrl_ldst}, {rob_uop_19_fp_ctrl_ldst}, {rob_uop_18_fp_ctrl_ldst}, {rob_uop_17_fp_ctrl_ldst}, {rob_uop_16_fp_ctrl_ldst}, {rob_uop_15_fp_ctrl_ldst}, {rob_uop_14_fp_ctrl_ldst}, {rob_uop_13_fp_ctrl_ldst}, {rob_uop_12_fp_ctrl_ldst}, {rob_uop_11_fp_ctrl_ldst}, {rob_uop_10_fp_ctrl_ldst}, {rob_uop_9_fp_ctrl_ldst}, {rob_uop_8_fp_ctrl_ldst}, {rob_uop_7_fp_ctrl_ldst}, {rob_uop_6_fp_ctrl_ldst}, {rob_uop_5_fp_ctrl_ldst}, {rob_uop_4_fp_ctrl_ldst}, {rob_uop_3_fp_ctrl_ldst}, {rob_uop_2_fp_ctrl_ldst}, {rob_uop_1_fp_ctrl_ldst}, {rob_uop_0_fp_ctrl_ldst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_ldst = _GEN_68[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_69 = {{rob_uop_31_fp_ctrl_wen}, {rob_uop_30_fp_ctrl_wen}, {rob_uop_29_fp_ctrl_wen}, {rob_uop_28_fp_ctrl_wen}, {rob_uop_27_fp_ctrl_wen}, {rob_uop_26_fp_ctrl_wen}, {rob_uop_25_fp_ctrl_wen}, {rob_uop_24_fp_ctrl_wen}, {rob_uop_23_fp_ctrl_wen}, {rob_uop_22_fp_ctrl_wen}, {rob_uop_21_fp_ctrl_wen}, {rob_uop_20_fp_ctrl_wen}, {rob_uop_19_fp_ctrl_wen}, {rob_uop_18_fp_ctrl_wen}, {rob_uop_17_fp_ctrl_wen}, {rob_uop_16_fp_ctrl_wen}, {rob_uop_15_fp_ctrl_wen}, {rob_uop_14_fp_ctrl_wen}, {rob_uop_13_fp_ctrl_wen}, {rob_uop_12_fp_ctrl_wen}, {rob_uop_11_fp_ctrl_wen}, {rob_uop_10_fp_ctrl_wen}, {rob_uop_9_fp_ctrl_wen}, {rob_uop_8_fp_ctrl_wen}, {rob_uop_7_fp_ctrl_wen}, {rob_uop_6_fp_ctrl_wen}, {rob_uop_5_fp_ctrl_wen}, {rob_uop_4_fp_ctrl_wen}, {rob_uop_3_fp_ctrl_wen}, {rob_uop_2_fp_ctrl_wen}, {rob_uop_1_fp_ctrl_wen}, {rob_uop_0_fp_ctrl_wen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_wen = _GEN_69[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_70 = {{rob_uop_31_fp_ctrl_ren1}, {rob_uop_30_fp_ctrl_ren1}, {rob_uop_29_fp_ctrl_ren1}, {rob_uop_28_fp_ctrl_ren1}, {rob_uop_27_fp_ctrl_ren1}, {rob_uop_26_fp_ctrl_ren1}, {rob_uop_25_fp_ctrl_ren1}, {rob_uop_24_fp_ctrl_ren1}, {rob_uop_23_fp_ctrl_ren1}, {rob_uop_22_fp_ctrl_ren1}, {rob_uop_21_fp_ctrl_ren1}, {rob_uop_20_fp_ctrl_ren1}, {rob_uop_19_fp_ctrl_ren1}, {rob_uop_18_fp_ctrl_ren1}, {rob_uop_17_fp_ctrl_ren1}, {rob_uop_16_fp_ctrl_ren1}, {rob_uop_15_fp_ctrl_ren1}, {rob_uop_14_fp_ctrl_ren1}, {rob_uop_13_fp_ctrl_ren1}, {rob_uop_12_fp_ctrl_ren1}, {rob_uop_11_fp_ctrl_ren1}, {rob_uop_10_fp_ctrl_ren1}, {rob_uop_9_fp_ctrl_ren1}, {rob_uop_8_fp_ctrl_ren1}, {rob_uop_7_fp_ctrl_ren1}, {rob_uop_6_fp_ctrl_ren1}, {rob_uop_5_fp_ctrl_ren1}, {rob_uop_4_fp_ctrl_ren1}, {rob_uop_3_fp_ctrl_ren1}, {rob_uop_2_fp_ctrl_ren1}, {rob_uop_1_fp_ctrl_ren1}, {rob_uop_0_fp_ctrl_ren1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_ren1 = _GEN_70[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_71 = {{rob_uop_31_fp_ctrl_ren2}, {rob_uop_30_fp_ctrl_ren2}, {rob_uop_29_fp_ctrl_ren2}, {rob_uop_28_fp_ctrl_ren2}, {rob_uop_27_fp_ctrl_ren2}, {rob_uop_26_fp_ctrl_ren2}, {rob_uop_25_fp_ctrl_ren2}, {rob_uop_24_fp_ctrl_ren2}, {rob_uop_23_fp_ctrl_ren2}, {rob_uop_22_fp_ctrl_ren2}, {rob_uop_21_fp_ctrl_ren2}, {rob_uop_20_fp_ctrl_ren2}, {rob_uop_19_fp_ctrl_ren2}, {rob_uop_18_fp_ctrl_ren2}, {rob_uop_17_fp_ctrl_ren2}, {rob_uop_16_fp_ctrl_ren2}, {rob_uop_15_fp_ctrl_ren2}, {rob_uop_14_fp_ctrl_ren2}, {rob_uop_13_fp_ctrl_ren2}, {rob_uop_12_fp_ctrl_ren2}, {rob_uop_11_fp_ctrl_ren2}, {rob_uop_10_fp_ctrl_ren2}, {rob_uop_9_fp_ctrl_ren2}, {rob_uop_8_fp_ctrl_ren2}, {rob_uop_7_fp_ctrl_ren2}, {rob_uop_6_fp_ctrl_ren2}, {rob_uop_5_fp_ctrl_ren2}, {rob_uop_4_fp_ctrl_ren2}, {rob_uop_3_fp_ctrl_ren2}, {rob_uop_2_fp_ctrl_ren2}, {rob_uop_1_fp_ctrl_ren2}, {rob_uop_0_fp_ctrl_ren2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_ren2 = _GEN_71[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_72 = {{rob_uop_31_fp_ctrl_ren3}, {rob_uop_30_fp_ctrl_ren3}, {rob_uop_29_fp_ctrl_ren3}, {rob_uop_28_fp_ctrl_ren3}, {rob_uop_27_fp_ctrl_ren3}, {rob_uop_26_fp_ctrl_ren3}, {rob_uop_25_fp_ctrl_ren3}, {rob_uop_24_fp_ctrl_ren3}, {rob_uop_23_fp_ctrl_ren3}, {rob_uop_22_fp_ctrl_ren3}, {rob_uop_21_fp_ctrl_ren3}, {rob_uop_20_fp_ctrl_ren3}, {rob_uop_19_fp_ctrl_ren3}, {rob_uop_18_fp_ctrl_ren3}, {rob_uop_17_fp_ctrl_ren3}, {rob_uop_16_fp_ctrl_ren3}, {rob_uop_15_fp_ctrl_ren3}, {rob_uop_14_fp_ctrl_ren3}, {rob_uop_13_fp_ctrl_ren3}, {rob_uop_12_fp_ctrl_ren3}, {rob_uop_11_fp_ctrl_ren3}, {rob_uop_10_fp_ctrl_ren3}, {rob_uop_9_fp_ctrl_ren3}, {rob_uop_8_fp_ctrl_ren3}, {rob_uop_7_fp_ctrl_ren3}, {rob_uop_6_fp_ctrl_ren3}, {rob_uop_5_fp_ctrl_ren3}, {rob_uop_4_fp_ctrl_ren3}, {rob_uop_3_fp_ctrl_ren3}, {rob_uop_2_fp_ctrl_ren3}, {rob_uop_1_fp_ctrl_ren3}, {rob_uop_0_fp_ctrl_ren3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_ren3 = _GEN_72[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_73 = {{rob_uop_31_fp_ctrl_swap12}, {rob_uop_30_fp_ctrl_swap12}, {rob_uop_29_fp_ctrl_swap12}, {rob_uop_28_fp_ctrl_swap12}, {rob_uop_27_fp_ctrl_swap12}, {rob_uop_26_fp_ctrl_swap12}, {rob_uop_25_fp_ctrl_swap12}, {rob_uop_24_fp_ctrl_swap12}, {rob_uop_23_fp_ctrl_swap12}, {rob_uop_22_fp_ctrl_swap12}, {rob_uop_21_fp_ctrl_swap12}, {rob_uop_20_fp_ctrl_swap12}, {rob_uop_19_fp_ctrl_swap12}, {rob_uop_18_fp_ctrl_swap12}, {rob_uop_17_fp_ctrl_swap12}, {rob_uop_16_fp_ctrl_swap12}, {rob_uop_15_fp_ctrl_swap12}, {rob_uop_14_fp_ctrl_swap12}, {rob_uop_13_fp_ctrl_swap12}, {rob_uop_12_fp_ctrl_swap12}, {rob_uop_11_fp_ctrl_swap12}, {rob_uop_10_fp_ctrl_swap12}, {rob_uop_9_fp_ctrl_swap12}, {rob_uop_8_fp_ctrl_swap12}, {rob_uop_7_fp_ctrl_swap12}, {rob_uop_6_fp_ctrl_swap12}, {rob_uop_5_fp_ctrl_swap12}, {rob_uop_4_fp_ctrl_swap12}, {rob_uop_3_fp_ctrl_swap12}, {rob_uop_2_fp_ctrl_swap12}, {rob_uop_1_fp_ctrl_swap12}, {rob_uop_0_fp_ctrl_swap12}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_swap12 = _GEN_73[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_74 = {{rob_uop_31_fp_ctrl_swap23}, {rob_uop_30_fp_ctrl_swap23}, {rob_uop_29_fp_ctrl_swap23}, {rob_uop_28_fp_ctrl_swap23}, {rob_uop_27_fp_ctrl_swap23}, {rob_uop_26_fp_ctrl_swap23}, {rob_uop_25_fp_ctrl_swap23}, {rob_uop_24_fp_ctrl_swap23}, {rob_uop_23_fp_ctrl_swap23}, {rob_uop_22_fp_ctrl_swap23}, {rob_uop_21_fp_ctrl_swap23}, {rob_uop_20_fp_ctrl_swap23}, {rob_uop_19_fp_ctrl_swap23}, {rob_uop_18_fp_ctrl_swap23}, {rob_uop_17_fp_ctrl_swap23}, {rob_uop_16_fp_ctrl_swap23}, {rob_uop_15_fp_ctrl_swap23}, {rob_uop_14_fp_ctrl_swap23}, {rob_uop_13_fp_ctrl_swap23}, {rob_uop_12_fp_ctrl_swap23}, {rob_uop_11_fp_ctrl_swap23}, {rob_uop_10_fp_ctrl_swap23}, {rob_uop_9_fp_ctrl_swap23}, {rob_uop_8_fp_ctrl_swap23}, {rob_uop_7_fp_ctrl_swap23}, {rob_uop_6_fp_ctrl_swap23}, {rob_uop_5_fp_ctrl_swap23}, {rob_uop_4_fp_ctrl_swap23}, {rob_uop_3_fp_ctrl_swap23}, {rob_uop_2_fp_ctrl_swap23}, {rob_uop_1_fp_ctrl_swap23}, {rob_uop_0_fp_ctrl_swap23}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_swap23 = _GEN_74[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_75 = {{rob_uop_31_fp_ctrl_typeTagIn}, {rob_uop_30_fp_ctrl_typeTagIn}, {rob_uop_29_fp_ctrl_typeTagIn}, {rob_uop_28_fp_ctrl_typeTagIn}, {rob_uop_27_fp_ctrl_typeTagIn}, {rob_uop_26_fp_ctrl_typeTagIn}, {rob_uop_25_fp_ctrl_typeTagIn}, {rob_uop_24_fp_ctrl_typeTagIn}, {rob_uop_23_fp_ctrl_typeTagIn}, {rob_uop_22_fp_ctrl_typeTagIn}, {rob_uop_21_fp_ctrl_typeTagIn}, {rob_uop_20_fp_ctrl_typeTagIn}, {rob_uop_19_fp_ctrl_typeTagIn}, {rob_uop_18_fp_ctrl_typeTagIn}, {rob_uop_17_fp_ctrl_typeTagIn}, {rob_uop_16_fp_ctrl_typeTagIn}, {rob_uop_15_fp_ctrl_typeTagIn}, {rob_uop_14_fp_ctrl_typeTagIn}, {rob_uop_13_fp_ctrl_typeTagIn}, {rob_uop_12_fp_ctrl_typeTagIn}, {rob_uop_11_fp_ctrl_typeTagIn}, {rob_uop_10_fp_ctrl_typeTagIn}, {rob_uop_9_fp_ctrl_typeTagIn}, {rob_uop_8_fp_ctrl_typeTagIn}, {rob_uop_7_fp_ctrl_typeTagIn}, {rob_uop_6_fp_ctrl_typeTagIn}, {rob_uop_5_fp_ctrl_typeTagIn}, {rob_uop_4_fp_ctrl_typeTagIn}, {rob_uop_3_fp_ctrl_typeTagIn}, {rob_uop_2_fp_ctrl_typeTagIn}, {rob_uop_1_fp_ctrl_typeTagIn}, {rob_uop_0_fp_ctrl_typeTagIn}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_typeTagIn = _GEN_75[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_76 = {{rob_uop_31_fp_ctrl_typeTagOut}, {rob_uop_30_fp_ctrl_typeTagOut}, {rob_uop_29_fp_ctrl_typeTagOut}, {rob_uop_28_fp_ctrl_typeTagOut}, {rob_uop_27_fp_ctrl_typeTagOut}, {rob_uop_26_fp_ctrl_typeTagOut}, {rob_uop_25_fp_ctrl_typeTagOut}, {rob_uop_24_fp_ctrl_typeTagOut}, {rob_uop_23_fp_ctrl_typeTagOut}, {rob_uop_22_fp_ctrl_typeTagOut}, {rob_uop_21_fp_ctrl_typeTagOut}, {rob_uop_20_fp_ctrl_typeTagOut}, {rob_uop_19_fp_ctrl_typeTagOut}, {rob_uop_18_fp_ctrl_typeTagOut}, {rob_uop_17_fp_ctrl_typeTagOut}, {rob_uop_16_fp_ctrl_typeTagOut}, {rob_uop_15_fp_ctrl_typeTagOut}, {rob_uop_14_fp_ctrl_typeTagOut}, {rob_uop_13_fp_ctrl_typeTagOut}, {rob_uop_12_fp_ctrl_typeTagOut}, {rob_uop_11_fp_ctrl_typeTagOut}, {rob_uop_10_fp_ctrl_typeTagOut}, {rob_uop_9_fp_ctrl_typeTagOut}, {rob_uop_8_fp_ctrl_typeTagOut}, {rob_uop_7_fp_ctrl_typeTagOut}, {rob_uop_6_fp_ctrl_typeTagOut}, {rob_uop_5_fp_ctrl_typeTagOut}, {rob_uop_4_fp_ctrl_typeTagOut}, {rob_uop_3_fp_ctrl_typeTagOut}, {rob_uop_2_fp_ctrl_typeTagOut}, {rob_uop_1_fp_ctrl_typeTagOut}, {rob_uop_0_fp_ctrl_typeTagOut}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_typeTagOut = _GEN_76[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_77 = {{rob_uop_31_fp_ctrl_fromint}, {rob_uop_30_fp_ctrl_fromint}, {rob_uop_29_fp_ctrl_fromint}, {rob_uop_28_fp_ctrl_fromint}, {rob_uop_27_fp_ctrl_fromint}, {rob_uop_26_fp_ctrl_fromint}, {rob_uop_25_fp_ctrl_fromint}, {rob_uop_24_fp_ctrl_fromint}, {rob_uop_23_fp_ctrl_fromint}, {rob_uop_22_fp_ctrl_fromint}, {rob_uop_21_fp_ctrl_fromint}, {rob_uop_20_fp_ctrl_fromint}, {rob_uop_19_fp_ctrl_fromint}, {rob_uop_18_fp_ctrl_fromint}, {rob_uop_17_fp_ctrl_fromint}, {rob_uop_16_fp_ctrl_fromint}, {rob_uop_15_fp_ctrl_fromint}, {rob_uop_14_fp_ctrl_fromint}, {rob_uop_13_fp_ctrl_fromint}, {rob_uop_12_fp_ctrl_fromint}, {rob_uop_11_fp_ctrl_fromint}, {rob_uop_10_fp_ctrl_fromint}, {rob_uop_9_fp_ctrl_fromint}, {rob_uop_8_fp_ctrl_fromint}, {rob_uop_7_fp_ctrl_fromint}, {rob_uop_6_fp_ctrl_fromint}, {rob_uop_5_fp_ctrl_fromint}, {rob_uop_4_fp_ctrl_fromint}, {rob_uop_3_fp_ctrl_fromint}, {rob_uop_2_fp_ctrl_fromint}, {rob_uop_1_fp_ctrl_fromint}, {rob_uop_0_fp_ctrl_fromint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_fromint = _GEN_77[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_78 = {{rob_uop_31_fp_ctrl_toint}, {rob_uop_30_fp_ctrl_toint}, {rob_uop_29_fp_ctrl_toint}, {rob_uop_28_fp_ctrl_toint}, {rob_uop_27_fp_ctrl_toint}, {rob_uop_26_fp_ctrl_toint}, {rob_uop_25_fp_ctrl_toint}, {rob_uop_24_fp_ctrl_toint}, {rob_uop_23_fp_ctrl_toint}, {rob_uop_22_fp_ctrl_toint}, {rob_uop_21_fp_ctrl_toint}, {rob_uop_20_fp_ctrl_toint}, {rob_uop_19_fp_ctrl_toint}, {rob_uop_18_fp_ctrl_toint}, {rob_uop_17_fp_ctrl_toint}, {rob_uop_16_fp_ctrl_toint}, {rob_uop_15_fp_ctrl_toint}, {rob_uop_14_fp_ctrl_toint}, {rob_uop_13_fp_ctrl_toint}, {rob_uop_12_fp_ctrl_toint}, {rob_uop_11_fp_ctrl_toint}, {rob_uop_10_fp_ctrl_toint}, {rob_uop_9_fp_ctrl_toint}, {rob_uop_8_fp_ctrl_toint}, {rob_uop_7_fp_ctrl_toint}, {rob_uop_6_fp_ctrl_toint}, {rob_uop_5_fp_ctrl_toint}, {rob_uop_4_fp_ctrl_toint}, {rob_uop_3_fp_ctrl_toint}, {rob_uop_2_fp_ctrl_toint}, {rob_uop_1_fp_ctrl_toint}, {rob_uop_0_fp_ctrl_toint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_toint = _GEN_78[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_79 = {{rob_uop_31_fp_ctrl_fastpipe}, {rob_uop_30_fp_ctrl_fastpipe}, {rob_uop_29_fp_ctrl_fastpipe}, {rob_uop_28_fp_ctrl_fastpipe}, {rob_uop_27_fp_ctrl_fastpipe}, {rob_uop_26_fp_ctrl_fastpipe}, {rob_uop_25_fp_ctrl_fastpipe}, {rob_uop_24_fp_ctrl_fastpipe}, {rob_uop_23_fp_ctrl_fastpipe}, {rob_uop_22_fp_ctrl_fastpipe}, {rob_uop_21_fp_ctrl_fastpipe}, {rob_uop_20_fp_ctrl_fastpipe}, {rob_uop_19_fp_ctrl_fastpipe}, {rob_uop_18_fp_ctrl_fastpipe}, {rob_uop_17_fp_ctrl_fastpipe}, {rob_uop_16_fp_ctrl_fastpipe}, {rob_uop_15_fp_ctrl_fastpipe}, {rob_uop_14_fp_ctrl_fastpipe}, {rob_uop_13_fp_ctrl_fastpipe}, {rob_uop_12_fp_ctrl_fastpipe}, {rob_uop_11_fp_ctrl_fastpipe}, {rob_uop_10_fp_ctrl_fastpipe}, {rob_uop_9_fp_ctrl_fastpipe}, {rob_uop_8_fp_ctrl_fastpipe}, {rob_uop_7_fp_ctrl_fastpipe}, {rob_uop_6_fp_ctrl_fastpipe}, {rob_uop_5_fp_ctrl_fastpipe}, {rob_uop_4_fp_ctrl_fastpipe}, {rob_uop_3_fp_ctrl_fastpipe}, {rob_uop_2_fp_ctrl_fastpipe}, {rob_uop_1_fp_ctrl_fastpipe}, {rob_uop_0_fp_ctrl_fastpipe}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_fastpipe = _GEN_79[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_80 = {{rob_uop_31_fp_ctrl_fma}, {rob_uop_30_fp_ctrl_fma}, {rob_uop_29_fp_ctrl_fma}, {rob_uop_28_fp_ctrl_fma}, {rob_uop_27_fp_ctrl_fma}, {rob_uop_26_fp_ctrl_fma}, {rob_uop_25_fp_ctrl_fma}, {rob_uop_24_fp_ctrl_fma}, {rob_uop_23_fp_ctrl_fma}, {rob_uop_22_fp_ctrl_fma}, {rob_uop_21_fp_ctrl_fma}, {rob_uop_20_fp_ctrl_fma}, {rob_uop_19_fp_ctrl_fma}, {rob_uop_18_fp_ctrl_fma}, {rob_uop_17_fp_ctrl_fma}, {rob_uop_16_fp_ctrl_fma}, {rob_uop_15_fp_ctrl_fma}, {rob_uop_14_fp_ctrl_fma}, {rob_uop_13_fp_ctrl_fma}, {rob_uop_12_fp_ctrl_fma}, {rob_uop_11_fp_ctrl_fma}, {rob_uop_10_fp_ctrl_fma}, {rob_uop_9_fp_ctrl_fma}, {rob_uop_8_fp_ctrl_fma}, {rob_uop_7_fp_ctrl_fma}, {rob_uop_6_fp_ctrl_fma}, {rob_uop_5_fp_ctrl_fma}, {rob_uop_4_fp_ctrl_fma}, {rob_uop_3_fp_ctrl_fma}, {rob_uop_2_fp_ctrl_fma}, {rob_uop_1_fp_ctrl_fma}, {rob_uop_0_fp_ctrl_fma}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_fma = _GEN_80[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_81 = {{rob_uop_31_fp_ctrl_div}, {rob_uop_30_fp_ctrl_div}, {rob_uop_29_fp_ctrl_div}, {rob_uop_28_fp_ctrl_div}, {rob_uop_27_fp_ctrl_div}, {rob_uop_26_fp_ctrl_div}, {rob_uop_25_fp_ctrl_div}, {rob_uop_24_fp_ctrl_div}, {rob_uop_23_fp_ctrl_div}, {rob_uop_22_fp_ctrl_div}, {rob_uop_21_fp_ctrl_div}, {rob_uop_20_fp_ctrl_div}, {rob_uop_19_fp_ctrl_div}, {rob_uop_18_fp_ctrl_div}, {rob_uop_17_fp_ctrl_div}, {rob_uop_16_fp_ctrl_div}, {rob_uop_15_fp_ctrl_div}, {rob_uop_14_fp_ctrl_div}, {rob_uop_13_fp_ctrl_div}, {rob_uop_12_fp_ctrl_div}, {rob_uop_11_fp_ctrl_div}, {rob_uop_10_fp_ctrl_div}, {rob_uop_9_fp_ctrl_div}, {rob_uop_8_fp_ctrl_div}, {rob_uop_7_fp_ctrl_div}, {rob_uop_6_fp_ctrl_div}, {rob_uop_5_fp_ctrl_div}, {rob_uop_4_fp_ctrl_div}, {rob_uop_3_fp_ctrl_div}, {rob_uop_2_fp_ctrl_div}, {rob_uop_1_fp_ctrl_div}, {rob_uop_0_fp_ctrl_div}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_div = _GEN_81[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_82 = {{rob_uop_31_fp_ctrl_sqrt}, {rob_uop_30_fp_ctrl_sqrt}, {rob_uop_29_fp_ctrl_sqrt}, {rob_uop_28_fp_ctrl_sqrt}, {rob_uop_27_fp_ctrl_sqrt}, {rob_uop_26_fp_ctrl_sqrt}, {rob_uop_25_fp_ctrl_sqrt}, {rob_uop_24_fp_ctrl_sqrt}, {rob_uop_23_fp_ctrl_sqrt}, {rob_uop_22_fp_ctrl_sqrt}, {rob_uop_21_fp_ctrl_sqrt}, {rob_uop_20_fp_ctrl_sqrt}, {rob_uop_19_fp_ctrl_sqrt}, {rob_uop_18_fp_ctrl_sqrt}, {rob_uop_17_fp_ctrl_sqrt}, {rob_uop_16_fp_ctrl_sqrt}, {rob_uop_15_fp_ctrl_sqrt}, {rob_uop_14_fp_ctrl_sqrt}, {rob_uop_13_fp_ctrl_sqrt}, {rob_uop_12_fp_ctrl_sqrt}, {rob_uop_11_fp_ctrl_sqrt}, {rob_uop_10_fp_ctrl_sqrt}, {rob_uop_9_fp_ctrl_sqrt}, {rob_uop_8_fp_ctrl_sqrt}, {rob_uop_7_fp_ctrl_sqrt}, {rob_uop_6_fp_ctrl_sqrt}, {rob_uop_5_fp_ctrl_sqrt}, {rob_uop_4_fp_ctrl_sqrt}, {rob_uop_3_fp_ctrl_sqrt}, {rob_uop_2_fp_ctrl_sqrt}, {rob_uop_1_fp_ctrl_sqrt}, {rob_uop_0_fp_ctrl_sqrt}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_sqrt = _GEN_82[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_83 = {{rob_uop_31_fp_ctrl_wflags}, {rob_uop_30_fp_ctrl_wflags}, {rob_uop_29_fp_ctrl_wflags}, {rob_uop_28_fp_ctrl_wflags}, {rob_uop_27_fp_ctrl_wflags}, {rob_uop_26_fp_ctrl_wflags}, {rob_uop_25_fp_ctrl_wflags}, {rob_uop_24_fp_ctrl_wflags}, {rob_uop_23_fp_ctrl_wflags}, {rob_uop_22_fp_ctrl_wflags}, {rob_uop_21_fp_ctrl_wflags}, {rob_uop_20_fp_ctrl_wflags}, {rob_uop_19_fp_ctrl_wflags}, {rob_uop_18_fp_ctrl_wflags}, {rob_uop_17_fp_ctrl_wflags}, {rob_uop_16_fp_ctrl_wflags}, {rob_uop_15_fp_ctrl_wflags}, {rob_uop_14_fp_ctrl_wflags}, {rob_uop_13_fp_ctrl_wflags}, {rob_uop_12_fp_ctrl_wflags}, {rob_uop_11_fp_ctrl_wflags}, {rob_uop_10_fp_ctrl_wflags}, {rob_uop_9_fp_ctrl_wflags}, {rob_uop_8_fp_ctrl_wflags}, {rob_uop_7_fp_ctrl_wflags}, {rob_uop_6_fp_ctrl_wflags}, {rob_uop_5_fp_ctrl_wflags}, {rob_uop_4_fp_ctrl_wflags}, {rob_uop_3_fp_ctrl_wflags}, {rob_uop_2_fp_ctrl_wflags}, {rob_uop_1_fp_ctrl_wflags}, {rob_uop_0_fp_ctrl_wflags}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_wflags = _GEN_83[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_84 = {{rob_uop_31_fp_ctrl_vec}, {rob_uop_30_fp_ctrl_vec}, {rob_uop_29_fp_ctrl_vec}, {rob_uop_28_fp_ctrl_vec}, {rob_uop_27_fp_ctrl_vec}, {rob_uop_26_fp_ctrl_vec}, {rob_uop_25_fp_ctrl_vec}, {rob_uop_24_fp_ctrl_vec}, {rob_uop_23_fp_ctrl_vec}, {rob_uop_22_fp_ctrl_vec}, {rob_uop_21_fp_ctrl_vec}, {rob_uop_20_fp_ctrl_vec}, {rob_uop_19_fp_ctrl_vec}, {rob_uop_18_fp_ctrl_vec}, {rob_uop_17_fp_ctrl_vec}, {rob_uop_16_fp_ctrl_vec}, {rob_uop_15_fp_ctrl_vec}, {rob_uop_14_fp_ctrl_vec}, {rob_uop_13_fp_ctrl_vec}, {rob_uop_12_fp_ctrl_vec}, {rob_uop_11_fp_ctrl_vec}, {rob_uop_10_fp_ctrl_vec}, {rob_uop_9_fp_ctrl_vec}, {rob_uop_8_fp_ctrl_vec}, {rob_uop_7_fp_ctrl_vec}, {rob_uop_6_fp_ctrl_vec}, {rob_uop_5_fp_ctrl_vec}, {rob_uop_4_fp_ctrl_vec}, {rob_uop_3_fp_ctrl_vec}, {rob_uop_2_fp_ctrl_vec}, {rob_uop_1_fp_ctrl_vec}, {rob_uop_0_fp_ctrl_vec}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_ctrl_vec = _GEN_84[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_85 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_rob_idx = _GEN_85[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_86 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_ldq_idx = _GEN_86[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_87 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_stq_idx = _GEN_87[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_88 = {{rob_uop_31_rxq_idx}, {rob_uop_30_rxq_idx}, {rob_uop_29_rxq_idx}, {rob_uop_28_rxq_idx}, {rob_uop_27_rxq_idx}, {rob_uop_26_rxq_idx}, {rob_uop_25_rxq_idx}, {rob_uop_24_rxq_idx}, {rob_uop_23_rxq_idx}, {rob_uop_22_rxq_idx}, {rob_uop_21_rxq_idx}, {rob_uop_20_rxq_idx}, {rob_uop_19_rxq_idx}, {rob_uop_18_rxq_idx}, {rob_uop_17_rxq_idx}, {rob_uop_16_rxq_idx}, {rob_uop_15_rxq_idx}, {rob_uop_14_rxq_idx}, {rob_uop_13_rxq_idx}, {rob_uop_12_rxq_idx}, {rob_uop_11_rxq_idx}, {rob_uop_10_rxq_idx}, {rob_uop_9_rxq_idx}, {rob_uop_8_rxq_idx}, {rob_uop_7_rxq_idx}, {rob_uop_6_rxq_idx}, {rob_uop_5_rxq_idx}, {rob_uop_4_rxq_idx}, {rob_uop_3_rxq_idx}, {rob_uop_2_rxq_idx}, {rob_uop_1_rxq_idx}, {rob_uop_0_rxq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_rxq_idx = _GEN_88[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_89 = {{rob_uop_31_prs1}, {rob_uop_30_prs1}, {rob_uop_29_prs1}, {rob_uop_28_prs1}, {rob_uop_27_prs1}, {rob_uop_26_prs1}, {rob_uop_25_prs1}, {rob_uop_24_prs1}, {rob_uop_23_prs1}, {rob_uop_22_prs1}, {rob_uop_21_prs1}, {rob_uop_20_prs1}, {rob_uop_19_prs1}, {rob_uop_18_prs1}, {rob_uop_17_prs1}, {rob_uop_16_prs1}, {rob_uop_15_prs1}, {rob_uop_14_prs1}, {rob_uop_13_prs1}, {rob_uop_12_prs1}, {rob_uop_11_prs1}, {rob_uop_10_prs1}, {rob_uop_9_prs1}, {rob_uop_8_prs1}, {rob_uop_7_prs1}, {rob_uop_6_prs1}, {rob_uop_5_prs1}, {rob_uop_4_prs1}, {rob_uop_3_prs1}, {rob_uop_2_prs1}, {rob_uop_1_prs1}, {rob_uop_0_prs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs1 = _GEN_89[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_90 = {{rob_uop_31_prs2}, {rob_uop_30_prs2}, {rob_uop_29_prs2}, {rob_uop_28_prs2}, {rob_uop_27_prs2}, {rob_uop_26_prs2}, {rob_uop_25_prs2}, {rob_uop_24_prs2}, {rob_uop_23_prs2}, {rob_uop_22_prs2}, {rob_uop_21_prs2}, {rob_uop_20_prs2}, {rob_uop_19_prs2}, {rob_uop_18_prs2}, {rob_uop_17_prs2}, {rob_uop_16_prs2}, {rob_uop_15_prs2}, {rob_uop_14_prs2}, {rob_uop_13_prs2}, {rob_uop_12_prs2}, {rob_uop_11_prs2}, {rob_uop_10_prs2}, {rob_uop_9_prs2}, {rob_uop_8_prs2}, {rob_uop_7_prs2}, {rob_uop_6_prs2}, {rob_uop_5_prs2}, {rob_uop_4_prs2}, {rob_uop_3_prs2}, {rob_uop_2_prs2}, {rob_uop_1_prs2}, {rob_uop_0_prs2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs2 = _GEN_90[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_91 = {{rob_uop_31_prs3}, {rob_uop_30_prs3}, {rob_uop_29_prs3}, {rob_uop_28_prs3}, {rob_uop_27_prs3}, {rob_uop_26_prs3}, {rob_uop_25_prs3}, {rob_uop_24_prs3}, {rob_uop_23_prs3}, {rob_uop_22_prs3}, {rob_uop_21_prs3}, {rob_uop_20_prs3}, {rob_uop_19_prs3}, {rob_uop_18_prs3}, {rob_uop_17_prs3}, {rob_uop_16_prs3}, {rob_uop_15_prs3}, {rob_uop_14_prs3}, {rob_uop_13_prs3}, {rob_uop_12_prs3}, {rob_uop_11_prs3}, {rob_uop_10_prs3}, {rob_uop_9_prs3}, {rob_uop_8_prs3}, {rob_uop_7_prs3}, {rob_uop_6_prs3}, {rob_uop_5_prs3}, {rob_uop_4_prs3}, {rob_uop_3_prs3}, {rob_uop_2_prs3}, {rob_uop_1_prs3}, {rob_uop_0_prs3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs3 = _GEN_91[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_92 = {{rob_uop_31_ppred}, {rob_uop_30_ppred}, {rob_uop_29_ppred}, {rob_uop_28_ppred}, {rob_uop_27_ppred}, {rob_uop_26_ppred}, {rob_uop_25_ppred}, {rob_uop_24_ppred}, {rob_uop_23_ppred}, {rob_uop_22_ppred}, {rob_uop_21_ppred}, {rob_uop_20_ppred}, {rob_uop_19_ppred}, {rob_uop_18_ppred}, {rob_uop_17_ppred}, {rob_uop_16_ppred}, {rob_uop_15_ppred}, {rob_uop_14_ppred}, {rob_uop_13_ppred}, {rob_uop_12_ppred}, {rob_uop_11_ppred}, {rob_uop_10_ppred}, {rob_uop_9_ppred}, {rob_uop_8_ppred}, {rob_uop_7_ppred}, {rob_uop_6_ppred}, {rob_uop_5_ppred}, {rob_uop_4_ppred}, {rob_uop_3_ppred}, {rob_uop_2_ppred}, {rob_uop_1_ppred}, {rob_uop_0_ppred}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_ppred = _GEN_92[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_93 = {{rob_uop_31_prs1_busy}, {rob_uop_30_prs1_busy}, {rob_uop_29_prs1_busy}, {rob_uop_28_prs1_busy}, {rob_uop_27_prs1_busy}, {rob_uop_26_prs1_busy}, {rob_uop_25_prs1_busy}, {rob_uop_24_prs1_busy}, {rob_uop_23_prs1_busy}, {rob_uop_22_prs1_busy}, {rob_uop_21_prs1_busy}, {rob_uop_20_prs1_busy}, {rob_uop_19_prs1_busy}, {rob_uop_18_prs1_busy}, {rob_uop_17_prs1_busy}, {rob_uop_16_prs1_busy}, {rob_uop_15_prs1_busy}, {rob_uop_14_prs1_busy}, {rob_uop_13_prs1_busy}, {rob_uop_12_prs1_busy}, {rob_uop_11_prs1_busy}, {rob_uop_10_prs1_busy}, {rob_uop_9_prs1_busy}, {rob_uop_8_prs1_busy}, {rob_uop_7_prs1_busy}, {rob_uop_6_prs1_busy}, {rob_uop_5_prs1_busy}, {rob_uop_4_prs1_busy}, {rob_uop_3_prs1_busy}, {rob_uop_2_prs1_busy}, {rob_uop_1_prs1_busy}, {rob_uop_0_prs1_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs1_busy = _GEN_93[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_94 = {{rob_uop_31_prs2_busy}, {rob_uop_30_prs2_busy}, {rob_uop_29_prs2_busy}, {rob_uop_28_prs2_busy}, {rob_uop_27_prs2_busy}, {rob_uop_26_prs2_busy}, {rob_uop_25_prs2_busy}, {rob_uop_24_prs2_busy}, {rob_uop_23_prs2_busy}, {rob_uop_22_prs2_busy}, {rob_uop_21_prs2_busy}, {rob_uop_20_prs2_busy}, {rob_uop_19_prs2_busy}, {rob_uop_18_prs2_busy}, {rob_uop_17_prs2_busy}, {rob_uop_16_prs2_busy}, {rob_uop_15_prs2_busy}, {rob_uop_14_prs2_busy}, {rob_uop_13_prs2_busy}, {rob_uop_12_prs2_busy}, {rob_uop_11_prs2_busy}, {rob_uop_10_prs2_busy}, {rob_uop_9_prs2_busy}, {rob_uop_8_prs2_busy}, {rob_uop_7_prs2_busy}, {rob_uop_6_prs2_busy}, {rob_uop_5_prs2_busy}, {rob_uop_4_prs2_busy}, {rob_uop_3_prs2_busy}, {rob_uop_2_prs2_busy}, {rob_uop_1_prs2_busy}, {rob_uop_0_prs2_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs2_busy = _GEN_94[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_95 = {{rob_uop_31_prs3_busy}, {rob_uop_30_prs3_busy}, {rob_uop_29_prs3_busy}, {rob_uop_28_prs3_busy}, {rob_uop_27_prs3_busy}, {rob_uop_26_prs3_busy}, {rob_uop_25_prs3_busy}, {rob_uop_24_prs3_busy}, {rob_uop_23_prs3_busy}, {rob_uop_22_prs3_busy}, {rob_uop_21_prs3_busy}, {rob_uop_20_prs3_busy}, {rob_uop_19_prs3_busy}, {rob_uop_18_prs3_busy}, {rob_uop_17_prs3_busy}, {rob_uop_16_prs3_busy}, {rob_uop_15_prs3_busy}, {rob_uop_14_prs3_busy}, {rob_uop_13_prs3_busy}, {rob_uop_12_prs3_busy}, {rob_uop_11_prs3_busy}, {rob_uop_10_prs3_busy}, {rob_uop_9_prs3_busy}, {rob_uop_8_prs3_busy}, {rob_uop_7_prs3_busy}, {rob_uop_6_prs3_busy}, {rob_uop_5_prs3_busy}, {rob_uop_4_prs3_busy}, {rob_uop_3_prs3_busy}, {rob_uop_2_prs3_busy}, {rob_uop_1_prs3_busy}, {rob_uop_0_prs3_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_prs3_busy = _GEN_95[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_96 = {{rob_uop_31_ppred_busy}, {rob_uop_30_ppred_busy}, {rob_uop_29_ppred_busy}, {rob_uop_28_ppred_busy}, {rob_uop_27_ppred_busy}, {rob_uop_26_ppred_busy}, {rob_uop_25_ppred_busy}, {rob_uop_24_ppred_busy}, {rob_uop_23_ppred_busy}, {rob_uop_22_ppred_busy}, {rob_uop_21_ppred_busy}, {rob_uop_20_ppred_busy}, {rob_uop_19_ppred_busy}, {rob_uop_18_ppred_busy}, {rob_uop_17_ppred_busy}, {rob_uop_16_ppred_busy}, {rob_uop_15_ppred_busy}, {rob_uop_14_ppred_busy}, {rob_uop_13_ppred_busy}, {rob_uop_12_ppred_busy}, {rob_uop_11_ppred_busy}, {rob_uop_10_ppred_busy}, {rob_uop_9_ppred_busy}, {rob_uop_8_ppred_busy}, {rob_uop_7_ppred_busy}, {rob_uop_6_ppred_busy}, {rob_uop_5_ppred_busy}, {rob_uop_4_ppred_busy}, {rob_uop_3_ppred_busy}, {rob_uop_2_ppred_busy}, {rob_uop_1_ppred_busy}, {rob_uop_0_ppred_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_ppred_busy = _GEN_96[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_97 = {{rob_uop_31_exception}, {rob_uop_30_exception}, {rob_uop_29_exception}, {rob_uop_28_exception}, {rob_uop_27_exception}, {rob_uop_26_exception}, {rob_uop_25_exception}, {rob_uop_24_exception}, {rob_uop_23_exception}, {rob_uop_22_exception}, {rob_uop_21_exception}, {rob_uop_20_exception}, {rob_uop_19_exception}, {rob_uop_18_exception}, {rob_uop_17_exception}, {rob_uop_16_exception}, {rob_uop_15_exception}, {rob_uop_14_exception}, {rob_uop_13_exception}, {rob_uop_12_exception}, {rob_uop_11_exception}, {rob_uop_10_exception}, {rob_uop_9_exception}, {rob_uop_8_exception}, {rob_uop_7_exception}, {rob_uop_6_exception}, {rob_uop_5_exception}, {rob_uop_4_exception}, {rob_uop_3_exception}, {rob_uop_2_exception}, {rob_uop_1_exception}, {rob_uop_0_exception}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_exception = _GEN_97[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][63:0] _GEN_98 = {{rob_uop_31_exc_cause}, {rob_uop_30_exc_cause}, {rob_uop_29_exc_cause}, {rob_uop_28_exc_cause}, {rob_uop_27_exc_cause}, {rob_uop_26_exc_cause}, {rob_uop_25_exc_cause}, {rob_uop_24_exc_cause}, {rob_uop_23_exc_cause}, {rob_uop_22_exc_cause}, {rob_uop_21_exc_cause}, {rob_uop_20_exc_cause}, {rob_uop_19_exc_cause}, {rob_uop_18_exc_cause}, {rob_uop_17_exc_cause}, {rob_uop_16_exc_cause}, {rob_uop_15_exc_cause}, {rob_uop_14_exc_cause}, {rob_uop_13_exc_cause}, {rob_uop_12_exc_cause}, {rob_uop_11_exc_cause}, {rob_uop_10_exc_cause}, {rob_uop_9_exc_cause}, {rob_uop_8_exc_cause}, {rob_uop_7_exc_cause}, {rob_uop_6_exc_cause}, {rob_uop_5_exc_cause}, {rob_uop_4_exc_cause}, {rob_uop_3_exc_cause}, {rob_uop_2_exc_cause}, {rob_uop_1_exc_cause}, {rob_uop_0_exc_cause}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_exc_cause = _GEN_98[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_99 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_mem_cmd = _GEN_99[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_100 = {{rob_uop_31_mem_size}, {rob_uop_30_mem_size}, {rob_uop_29_mem_size}, {rob_uop_28_mem_size}, {rob_uop_27_mem_size}, {rob_uop_26_mem_size}, {rob_uop_25_mem_size}, {rob_uop_24_mem_size}, {rob_uop_23_mem_size}, {rob_uop_22_mem_size}, {rob_uop_21_mem_size}, {rob_uop_20_mem_size}, {rob_uop_19_mem_size}, {rob_uop_18_mem_size}, {rob_uop_17_mem_size}, {rob_uop_16_mem_size}, {rob_uop_15_mem_size}, {rob_uop_14_mem_size}, {rob_uop_13_mem_size}, {rob_uop_12_mem_size}, {rob_uop_11_mem_size}, {rob_uop_10_mem_size}, {rob_uop_9_mem_size}, {rob_uop_8_mem_size}, {rob_uop_7_mem_size}, {rob_uop_6_mem_size}, {rob_uop_5_mem_size}, {rob_uop_4_mem_size}, {rob_uop_3_mem_size}, {rob_uop_2_mem_size}, {rob_uop_1_mem_size}, {rob_uop_0_mem_size}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_mem_size = _GEN_100[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_101 = {{rob_uop_31_mem_signed}, {rob_uop_30_mem_signed}, {rob_uop_29_mem_signed}, {rob_uop_28_mem_signed}, {rob_uop_27_mem_signed}, {rob_uop_26_mem_signed}, {rob_uop_25_mem_signed}, {rob_uop_24_mem_signed}, {rob_uop_23_mem_signed}, {rob_uop_22_mem_signed}, {rob_uop_21_mem_signed}, {rob_uop_20_mem_signed}, {rob_uop_19_mem_signed}, {rob_uop_18_mem_signed}, {rob_uop_17_mem_signed}, {rob_uop_16_mem_signed}, {rob_uop_15_mem_signed}, {rob_uop_14_mem_signed}, {rob_uop_13_mem_signed}, {rob_uop_12_mem_signed}, {rob_uop_11_mem_signed}, {rob_uop_10_mem_signed}, {rob_uop_9_mem_signed}, {rob_uop_8_mem_signed}, {rob_uop_7_mem_signed}, {rob_uop_6_mem_signed}, {rob_uop_5_mem_signed}, {rob_uop_4_mem_signed}, {rob_uop_3_mem_signed}, {rob_uop_2_mem_signed}, {rob_uop_1_mem_signed}, {rob_uop_0_mem_signed}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_mem_signed = _GEN_101[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_102 = {{rob_uop_31_is_unique}, {rob_uop_30_is_unique}, {rob_uop_29_is_unique}, {rob_uop_28_is_unique}, {rob_uop_27_is_unique}, {rob_uop_26_is_unique}, {rob_uop_25_is_unique}, {rob_uop_24_is_unique}, {rob_uop_23_is_unique}, {rob_uop_22_is_unique}, {rob_uop_21_is_unique}, {rob_uop_20_is_unique}, {rob_uop_19_is_unique}, {rob_uop_18_is_unique}, {rob_uop_17_is_unique}, {rob_uop_16_is_unique}, {rob_uop_15_is_unique}, {rob_uop_14_is_unique}, {rob_uop_13_is_unique}, {rob_uop_12_is_unique}, {rob_uop_11_is_unique}, {rob_uop_10_is_unique}, {rob_uop_9_is_unique}, {rob_uop_8_is_unique}, {rob_uop_7_is_unique}, {rob_uop_6_is_unique}, {rob_uop_5_is_unique}, {rob_uop_4_is_unique}, {rob_uop_3_is_unique}, {rob_uop_2_is_unique}, {rob_uop_1_is_unique}, {rob_uop_0_is_unique}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_is_unique = _GEN_102[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_103 = {{rob_uop_31_flush_on_commit}, {rob_uop_30_flush_on_commit}, {rob_uop_29_flush_on_commit}, {rob_uop_28_flush_on_commit}, {rob_uop_27_flush_on_commit}, {rob_uop_26_flush_on_commit}, {rob_uop_25_flush_on_commit}, {rob_uop_24_flush_on_commit}, {rob_uop_23_flush_on_commit}, {rob_uop_22_flush_on_commit}, {rob_uop_21_flush_on_commit}, {rob_uop_20_flush_on_commit}, {rob_uop_19_flush_on_commit}, {rob_uop_18_flush_on_commit}, {rob_uop_17_flush_on_commit}, {rob_uop_16_flush_on_commit}, {rob_uop_15_flush_on_commit}, {rob_uop_14_flush_on_commit}, {rob_uop_13_flush_on_commit}, {rob_uop_12_flush_on_commit}, {rob_uop_11_flush_on_commit}, {rob_uop_10_flush_on_commit}, {rob_uop_9_flush_on_commit}, {rob_uop_8_flush_on_commit}, {rob_uop_7_flush_on_commit}, {rob_uop_6_flush_on_commit}, {rob_uop_5_flush_on_commit}, {rob_uop_4_flush_on_commit}, {rob_uop_3_flush_on_commit}, {rob_uop_2_flush_on_commit}, {rob_uop_1_flush_on_commit}, {rob_uop_0_flush_on_commit}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_flush_on_commit = _GEN_103[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_104 = {{rob_uop_31_csr_cmd}, {rob_uop_30_csr_cmd}, {rob_uop_29_csr_cmd}, {rob_uop_28_csr_cmd}, {rob_uop_27_csr_cmd}, {rob_uop_26_csr_cmd}, {rob_uop_25_csr_cmd}, {rob_uop_24_csr_cmd}, {rob_uop_23_csr_cmd}, {rob_uop_22_csr_cmd}, {rob_uop_21_csr_cmd}, {rob_uop_20_csr_cmd}, {rob_uop_19_csr_cmd}, {rob_uop_18_csr_cmd}, {rob_uop_17_csr_cmd}, {rob_uop_16_csr_cmd}, {rob_uop_15_csr_cmd}, {rob_uop_14_csr_cmd}, {rob_uop_13_csr_cmd}, {rob_uop_12_csr_cmd}, {rob_uop_11_csr_cmd}, {rob_uop_10_csr_cmd}, {rob_uop_9_csr_cmd}, {rob_uop_8_csr_cmd}, {rob_uop_7_csr_cmd}, {rob_uop_6_csr_cmd}, {rob_uop_5_csr_cmd}, {rob_uop_4_csr_cmd}, {rob_uop_3_csr_cmd}, {rob_uop_2_csr_cmd}, {rob_uop_1_csr_cmd}, {rob_uop_0_csr_cmd}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_csr_cmd = _GEN_104[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_105 = {{rob_uop_31_ldst_is_rs1}, {rob_uop_30_ldst_is_rs1}, {rob_uop_29_ldst_is_rs1}, {rob_uop_28_ldst_is_rs1}, {rob_uop_27_ldst_is_rs1}, {rob_uop_26_ldst_is_rs1}, {rob_uop_25_ldst_is_rs1}, {rob_uop_24_ldst_is_rs1}, {rob_uop_23_ldst_is_rs1}, {rob_uop_22_ldst_is_rs1}, {rob_uop_21_ldst_is_rs1}, {rob_uop_20_ldst_is_rs1}, {rob_uop_19_ldst_is_rs1}, {rob_uop_18_ldst_is_rs1}, {rob_uop_17_ldst_is_rs1}, {rob_uop_16_ldst_is_rs1}, {rob_uop_15_ldst_is_rs1}, {rob_uop_14_ldst_is_rs1}, {rob_uop_13_ldst_is_rs1}, {rob_uop_12_ldst_is_rs1}, {rob_uop_11_ldst_is_rs1}, {rob_uop_10_ldst_is_rs1}, {rob_uop_9_ldst_is_rs1}, {rob_uop_8_ldst_is_rs1}, {rob_uop_7_ldst_is_rs1}, {rob_uop_6_ldst_is_rs1}, {rob_uop_5_ldst_is_rs1}, {rob_uop_4_ldst_is_rs1}, {rob_uop_3_ldst_is_rs1}, {rob_uop_2_ldst_is_rs1}, {rob_uop_1_ldst_is_rs1}, {rob_uop_0_ldst_is_rs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_ldst_is_rs1 = _GEN_105[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_106 = {{rob_uop_31_lrs1}, {rob_uop_30_lrs1}, {rob_uop_29_lrs1}, {rob_uop_28_lrs1}, {rob_uop_27_lrs1}, {rob_uop_26_lrs1}, {rob_uop_25_lrs1}, {rob_uop_24_lrs1}, {rob_uop_23_lrs1}, {rob_uop_22_lrs1}, {rob_uop_21_lrs1}, {rob_uop_20_lrs1}, {rob_uop_19_lrs1}, {rob_uop_18_lrs1}, {rob_uop_17_lrs1}, {rob_uop_16_lrs1}, {rob_uop_15_lrs1}, {rob_uop_14_lrs1}, {rob_uop_13_lrs1}, {rob_uop_12_lrs1}, {rob_uop_11_lrs1}, {rob_uop_10_lrs1}, {rob_uop_9_lrs1}, {rob_uop_8_lrs1}, {rob_uop_7_lrs1}, {rob_uop_6_lrs1}, {rob_uop_5_lrs1}, {rob_uop_4_lrs1}, {rob_uop_3_lrs1}, {rob_uop_2_lrs1}, {rob_uop_1_lrs1}, {rob_uop_0_lrs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_lrs1 = _GEN_106[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_107 = {{rob_uop_31_lrs2}, {rob_uop_30_lrs2}, {rob_uop_29_lrs2}, {rob_uop_28_lrs2}, {rob_uop_27_lrs2}, {rob_uop_26_lrs2}, {rob_uop_25_lrs2}, {rob_uop_24_lrs2}, {rob_uop_23_lrs2}, {rob_uop_22_lrs2}, {rob_uop_21_lrs2}, {rob_uop_20_lrs2}, {rob_uop_19_lrs2}, {rob_uop_18_lrs2}, {rob_uop_17_lrs2}, {rob_uop_16_lrs2}, {rob_uop_15_lrs2}, {rob_uop_14_lrs2}, {rob_uop_13_lrs2}, {rob_uop_12_lrs2}, {rob_uop_11_lrs2}, {rob_uop_10_lrs2}, {rob_uop_9_lrs2}, {rob_uop_8_lrs2}, {rob_uop_7_lrs2}, {rob_uop_6_lrs2}, {rob_uop_5_lrs2}, {rob_uop_4_lrs2}, {rob_uop_3_lrs2}, {rob_uop_2_lrs2}, {rob_uop_1_lrs2}, {rob_uop_0_lrs2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_lrs2 = _GEN_107[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_108 = {{rob_uop_31_lrs3}, {rob_uop_30_lrs3}, {rob_uop_29_lrs3}, {rob_uop_28_lrs3}, {rob_uop_27_lrs3}, {rob_uop_26_lrs3}, {rob_uop_25_lrs3}, {rob_uop_24_lrs3}, {rob_uop_23_lrs3}, {rob_uop_22_lrs3}, {rob_uop_21_lrs3}, {rob_uop_20_lrs3}, {rob_uop_19_lrs3}, {rob_uop_18_lrs3}, {rob_uop_17_lrs3}, {rob_uop_16_lrs3}, {rob_uop_15_lrs3}, {rob_uop_14_lrs3}, {rob_uop_13_lrs3}, {rob_uop_12_lrs3}, {rob_uop_11_lrs3}, {rob_uop_10_lrs3}, {rob_uop_9_lrs3}, {rob_uop_8_lrs3}, {rob_uop_7_lrs3}, {rob_uop_6_lrs3}, {rob_uop_5_lrs3}, {rob_uop_4_lrs3}, {rob_uop_3_lrs3}, {rob_uop_2_lrs3}, {rob_uop_1_lrs3}, {rob_uop_0_lrs3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_lrs3 = _GEN_108[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_109 = {{rob_uop_31_lrs1_rtype}, {rob_uop_30_lrs1_rtype}, {rob_uop_29_lrs1_rtype}, {rob_uop_28_lrs1_rtype}, {rob_uop_27_lrs1_rtype}, {rob_uop_26_lrs1_rtype}, {rob_uop_25_lrs1_rtype}, {rob_uop_24_lrs1_rtype}, {rob_uop_23_lrs1_rtype}, {rob_uop_22_lrs1_rtype}, {rob_uop_21_lrs1_rtype}, {rob_uop_20_lrs1_rtype}, {rob_uop_19_lrs1_rtype}, {rob_uop_18_lrs1_rtype}, {rob_uop_17_lrs1_rtype}, {rob_uop_16_lrs1_rtype}, {rob_uop_15_lrs1_rtype}, {rob_uop_14_lrs1_rtype}, {rob_uop_13_lrs1_rtype}, {rob_uop_12_lrs1_rtype}, {rob_uop_11_lrs1_rtype}, {rob_uop_10_lrs1_rtype}, {rob_uop_9_lrs1_rtype}, {rob_uop_8_lrs1_rtype}, {rob_uop_7_lrs1_rtype}, {rob_uop_6_lrs1_rtype}, {rob_uop_5_lrs1_rtype}, {rob_uop_4_lrs1_rtype}, {rob_uop_3_lrs1_rtype}, {rob_uop_2_lrs1_rtype}, {rob_uop_1_lrs1_rtype}, {rob_uop_0_lrs1_rtype}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_lrs1_rtype = _GEN_109[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_110 = {{rob_uop_31_lrs2_rtype}, {rob_uop_30_lrs2_rtype}, {rob_uop_29_lrs2_rtype}, {rob_uop_28_lrs2_rtype}, {rob_uop_27_lrs2_rtype}, {rob_uop_26_lrs2_rtype}, {rob_uop_25_lrs2_rtype}, {rob_uop_24_lrs2_rtype}, {rob_uop_23_lrs2_rtype}, {rob_uop_22_lrs2_rtype}, {rob_uop_21_lrs2_rtype}, {rob_uop_20_lrs2_rtype}, {rob_uop_19_lrs2_rtype}, {rob_uop_18_lrs2_rtype}, {rob_uop_17_lrs2_rtype}, {rob_uop_16_lrs2_rtype}, {rob_uop_15_lrs2_rtype}, {rob_uop_14_lrs2_rtype}, {rob_uop_13_lrs2_rtype}, {rob_uop_12_lrs2_rtype}, {rob_uop_11_lrs2_rtype}, {rob_uop_10_lrs2_rtype}, {rob_uop_9_lrs2_rtype}, {rob_uop_8_lrs2_rtype}, {rob_uop_7_lrs2_rtype}, {rob_uop_6_lrs2_rtype}, {rob_uop_5_lrs2_rtype}, {rob_uop_4_lrs2_rtype}, {rob_uop_3_lrs2_rtype}, {rob_uop_2_lrs2_rtype}, {rob_uop_1_lrs2_rtype}, {rob_uop_0_lrs2_rtype}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_lrs2_rtype = _GEN_110[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_111 = {{rob_uop_31_frs3_en}, {rob_uop_30_frs3_en}, {rob_uop_29_frs3_en}, {rob_uop_28_frs3_en}, {rob_uop_27_frs3_en}, {rob_uop_26_frs3_en}, {rob_uop_25_frs3_en}, {rob_uop_24_frs3_en}, {rob_uop_23_frs3_en}, {rob_uop_22_frs3_en}, {rob_uop_21_frs3_en}, {rob_uop_20_frs3_en}, {rob_uop_19_frs3_en}, {rob_uop_18_frs3_en}, {rob_uop_17_frs3_en}, {rob_uop_16_frs3_en}, {rob_uop_15_frs3_en}, {rob_uop_14_frs3_en}, {rob_uop_13_frs3_en}, {rob_uop_12_frs3_en}, {rob_uop_11_frs3_en}, {rob_uop_10_frs3_en}, {rob_uop_9_frs3_en}, {rob_uop_8_frs3_en}, {rob_uop_7_frs3_en}, {rob_uop_6_frs3_en}, {rob_uop_5_frs3_en}, {rob_uop_4_frs3_en}, {rob_uop_3_frs3_en}, {rob_uop_2_frs3_en}, {rob_uop_1_frs3_en}, {rob_uop_0_frs3_en}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_frs3_en = _GEN_111[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_112 = {{rob_uop_31_fcn_dw}, {rob_uop_30_fcn_dw}, {rob_uop_29_fcn_dw}, {rob_uop_28_fcn_dw}, {rob_uop_27_fcn_dw}, {rob_uop_26_fcn_dw}, {rob_uop_25_fcn_dw}, {rob_uop_24_fcn_dw}, {rob_uop_23_fcn_dw}, {rob_uop_22_fcn_dw}, {rob_uop_21_fcn_dw}, {rob_uop_20_fcn_dw}, {rob_uop_19_fcn_dw}, {rob_uop_18_fcn_dw}, {rob_uop_17_fcn_dw}, {rob_uop_16_fcn_dw}, {rob_uop_15_fcn_dw}, {rob_uop_14_fcn_dw}, {rob_uop_13_fcn_dw}, {rob_uop_12_fcn_dw}, {rob_uop_11_fcn_dw}, {rob_uop_10_fcn_dw}, {rob_uop_9_fcn_dw}, {rob_uop_8_fcn_dw}, {rob_uop_7_fcn_dw}, {rob_uop_6_fcn_dw}, {rob_uop_5_fcn_dw}, {rob_uop_4_fcn_dw}, {rob_uop_3_fcn_dw}, {rob_uop_2_fcn_dw}, {rob_uop_1_fcn_dw}, {rob_uop_0_fcn_dw}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fcn_dw = _GEN_112[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_113 = {{rob_uop_31_fcn_op}, {rob_uop_30_fcn_op}, {rob_uop_29_fcn_op}, {rob_uop_28_fcn_op}, {rob_uop_27_fcn_op}, {rob_uop_26_fcn_op}, {rob_uop_25_fcn_op}, {rob_uop_24_fcn_op}, {rob_uop_23_fcn_op}, {rob_uop_22_fcn_op}, {rob_uop_21_fcn_op}, {rob_uop_20_fcn_op}, {rob_uop_19_fcn_op}, {rob_uop_18_fcn_op}, {rob_uop_17_fcn_op}, {rob_uop_16_fcn_op}, {rob_uop_15_fcn_op}, {rob_uop_14_fcn_op}, {rob_uop_13_fcn_op}, {rob_uop_12_fcn_op}, {rob_uop_11_fcn_op}, {rob_uop_10_fcn_op}, {rob_uop_9_fcn_op}, {rob_uop_8_fcn_op}, {rob_uop_7_fcn_op}, {rob_uop_6_fcn_op}, {rob_uop_5_fcn_op}, {rob_uop_4_fcn_op}, {rob_uop_3_fcn_op}, {rob_uop_2_fcn_op}, {rob_uop_1_fcn_op}, {rob_uop_0_fcn_op}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fcn_op = _GEN_113[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_114 = {{rob_uop_31_fp_val}, {rob_uop_30_fp_val}, {rob_uop_29_fp_val}, {rob_uop_28_fp_val}, {rob_uop_27_fp_val}, {rob_uop_26_fp_val}, {rob_uop_25_fp_val}, {rob_uop_24_fp_val}, {rob_uop_23_fp_val}, {rob_uop_22_fp_val}, {rob_uop_21_fp_val}, {rob_uop_20_fp_val}, {rob_uop_19_fp_val}, {rob_uop_18_fp_val}, {rob_uop_17_fp_val}, {rob_uop_16_fp_val}, {rob_uop_15_fp_val}, {rob_uop_14_fp_val}, {rob_uop_13_fp_val}, {rob_uop_12_fp_val}, {rob_uop_11_fp_val}, {rob_uop_10_fp_val}, {rob_uop_9_fp_val}, {rob_uop_8_fp_val}, {rob_uop_7_fp_val}, {rob_uop_6_fp_val}, {rob_uop_5_fp_val}, {rob_uop_4_fp_val}, {rob_uop_3_fp_val}, {rob_uop_2_fp_val}, {rob_uop_1_fp_val}, {rob_uop_0_fp_val}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_val = _GEN_114[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_115 = {{rob_uop_31_fp_rm}, {rob_uop_30_fp_rm}, {rob_uop_29_fp_rm}, {rob_uop_28_fp_rm}, {rob_uop_27_fp_rm}, {rob_uop_26_fp_rm}, {rob_uop_25_fp_rm}, {rob_uop_24_fp_rm}, {rob_uop_23_fp_rm}, {rob_uop_22_fp_rm}, {rob_uop_21_fp_rm}, {rob_uop_20_fp_rm}, {rob_uop_19_fp_rm}, {rob_uop_18_fp_rm}, {rob_uop_17_fp_rm}, {rob_uop_16_fp_rm}, {rob_uop_15_fp_rm}, {rob_uop_14_fp_rm}, {rob_uop_13_fp_rm}, {rob_uop_12_fp_rm}, {rob_uop_11_fp_rm}, {rob_uop_10_fp_rm}, {rob_uop_9_fp_rm}, {rob_uop_8_fp_rm}, {rob_uop_7_fp_rm}, {rob_uop_6_fp_rm}, {rob_uop_5_fp_rm}, {rob_uop_4_fp_rm}, {rob_uop_3_fp_rm}, {rob_uop_2_fp_rm}, {rob_uop_1_fp_rm}, {rob_uop_0_fp_rm}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_rm = _GEN_115[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_116 = {{rob_uop_31_fp_typ}, {rob_uop_30_fp_typ}, {rob_uop_29_fp_typ}, {rob_uop_28_fp_typ}, {rob_uop_27_fp_typ}, {rob_uop_26_fp_typ}, {rob_uop_25_fp_typ}, {rob_uop_24_fp_typ}, {rob_uop_23_fp_typ}, {rob_uop_22_fp_typ}, {rob_uop_21_fp_typ}, {rob_uop_20_fp_typ}, {rob_uop_19_fp_typ}, {rob_uop_18_fp_typ}, {rob_uop_17_fp_typ}, {rob_uop_16_fp_typ}, {rob_uop_15_fp_typ}, {rob_uop_14_fp_typ}, {rob_uop_13_fp_typ}, {rob_uop_12_fp_typ}, {rob_uop_11_fp_typ}, {rob_uop_10_fp_typ}, {rob_uop_9_fp_typ}, {rob_uop_8_fp_typ}, {rob_uop_7_fp_typ}, {rob_uop_6_fp_typ}, {rob_uop_5_fp_typ}, {rob_uop_4_fp_typ}, {rob_uop_3_fp_typ}, {rob_uop_2_fp_typ}, {rob_uop_1_fp_typ}, {rob_uop_0_fp_typ}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_fp_typ = _GEN_116[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_117 = {{rob_uop_31_xcpt_pf_if}, {rob_uop_30_xcpt_pf_if}, {rob_uop_29_xcpt_pf_if}, {rob_uop_28_xcpt_pf_if}, {rob_uop_27_xcpt_pf_if}, {rob_uop_26_xcpt_pf_if}, {rob_uop_25_xcpt_pf_if}, {rob_uop_24_xcpt_pf_if}, {rob_uop_23_xcpt_pf_if}, {rob_uop_22_xcpt_pf_if}, {rob_uop_21_xcpt_pf_if}, {rob_uop_20_xcpt_pf_if}, {rob_uop_19_xcpt_pf_if}, {rob_uop_18_xcpt_pf_if}, {rob_uop_17_xcpt_pf_if}, {rob_uop_16_xcpt_pf_if}, {rob_uop_15_xcpt_pf_if}, {rob_uop_14_xcpt_pf_if}, {rob_uop_13_xcpt_pf_if}, {rob_uop_12_xcpt_pf_if}, {rob_uop_11_xcpt_pf_if}, {rob_uop_10_xcpt_pf_if}, {rob_uop_9_xcpt_pf_if}, {rob_uop_8_xcpt_pf_if}, {rob_uop_7_xcpt_pf_if}, {rob_uop_6_xcpt_pf_if}, {rob_uop_5_xcpt_pf_if}, {rob_uop_4_xcpt_pf_if}, {rob_uop_3_xcpt_pf_if}, {rob_uop_2_xcpt_pf_if}, {rob_uop_1_xcpt_pf_if}, {rob_uop_0_xcpt_pf_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_xcpt_pf_if = _GEN_117[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_118 = {{rob_uop_31_xcpt_ae_if}, {rob_uop_30_xcpt_ae_if}, {rob_uop_29_xcpt_ae_if}, {rob_uop_28_xcpt_ae_if}, {rob_uop_27_xcpt_ae_if}, {rob_uop_26_xcpt_ae_if}, {rob_uop_25_xcpt_ae_if}, {rob_uop_24_xcpt_ae_if}, {rob_uop_23_xcpt_ae_if}, {rob_uop_22_xcpt_ae_if}, {rob_uop_21_xcpt_ae_if}, {rob_uop_20_xcpt_ae_if}, {rob_uop_19_xcpt_ae_if}, {rob_uop_18_xcpt_ae_if}, {rob_uop_17_xcpt_ae_if}, {rob_uop_16_xcpt_ae_if}, {rob_uop_15_xcpt_ae_if}, {rob_uop_14_xcpt_ae_if}, {rob_uop_13_xcpt_ae_if}, {rob_uop_12_xcpt_ae_if}, {rob_uop_11_xcpt_ae_if}, {rob_uop_10_xcpt_ae_if}, {rob_uop_9_xcpt_ae_if}, {rob_uop_8_xcpt_ae_if}, {rob_uop_7_xcpt_ae_if}, {rob_uop_6_xcpt_ae_if}, {rob_uop_5_xcpt_ae_if}, {rob_uop_4_xcpt_ae_if}, {rob_uop_3_xcpt_ae_if}, {rob_uop_2_xcpt_ae_if}, {rob_uop_1_xcpt_ae_if}, {rob_uop_0_xcpt_ae_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_xcpt_ae_if = _GEN_118[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_119 = {{rob_uop_31_xcpt_ma_if}, {rob_uop_30_xcpt_ma_if}, {rob_uop_29_xcpt_ma_if}, {rob_uop_28_xcpt_ma_if}, {rob_uop_27_xcpt_ma_if}, {rob_uop_26_xcpt_ma_if}, {rob_uop_25_xcpt_ma_if}, {rob_uop_24_xcpt_ma_if}, {rob_uop_23_xcpt_ma_if}, {rob_uop_22_xcpt_ma_if}, {rob_uop_21_xcpt_ma_if}, {rob_uop_20_xcpt_ma_if}, {rob_uop_19_xcpt_ma_if}, {rob_uop_18_xcpt_ma_if}, {rob_uop_17_xcpt_ma_if}, {rob_uop_16_xcpt_ma_if}, {rob_uop_15_xcpt_ma_if}, {rob_uop_14_xcpt_ma_if}, {rob_uop_13_xcpt_ma_if}, {rob_uop_12_xcpt_ma_if}, {rob_uop_11_xcpt_ma_if}, {rob_uop_10_xcpt_ma_if}, {rob_uop_9_xcpt_ma_if}, {rob_uop_8_xcpt_ma_if}, {rob_uop_7_xcpt_ma_if}, {rob_uop_6_xcpt_ma_if}, {rob_uop_5_xcpt_ma_if}, {rob_uop_4_xcpt_ma_if}, {rob_uop_3_xcpt_ma_if}, {rob_uop_2_xcpt_ma_if}, {rob_uop_1_xcpt_ma_if}, {rob_uop_0_xcpt_ma_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_xcpt_ma_if = _GEN_119[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_120 = {{rob_uop_31_bp_debug_if}, {rob_uop_30_bp_debug_if}, {rob_uop_29_bp_debug_if}, {rob_uop_28_bp_debug_if}, {rob_uop_27_bp_debug_if}, {rob_uop_26_bp_debug_if}, {rob_uop_25_bp_debug_if}, {rob_uop_24_bp_debug_if}, {rob_uop_23_bp_debug_if}, {rob_uop_22_bp_debug_if}, {rob_uop_21_bp_debug_if}, {rob_uop_20_bp_debug_if}, {rob_uop_19_bp_debug_if}, {rob_uop_18_bp_debug_if}, {rob_uop_17_bp_debug_if}, {rob_uop_16_bp_debug_if}, {rob_uop_15_bp_debug_if}, {rob_uop_14_bp_debug_if}, {rob_uop_13_bp_debug_if}, {rob_uop_12_bp_debug_if}, {rob_uop_11_bp_debug_if}, {rob_uop_10_bp_debug_if}, {rob_uop_9_bp_debug_if}, {rob_uop_8_bp_debug_if}, {rob_uop_7_bp_debug_if}, {rob_uop_6_bp_debug_if}, {rob_uop_5_bp_debug_if}, {rob_uop_4_bp_debug_if}, {rob_uop_3_bp_debug_if}, {rob_uop_2_bp_debug_if}, {rob_uop_1_bp_debug_if}, {rob_uop_0_bp_debug_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_bp_debug_if = _GEN_120[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_121 = {{rob_uop_31_bp_xcpt_if}, {rob_uop_30_bp_xcpt_if}, {rob_uop_29_bp_xcpt_if}, {rob_uop_28_bp_xcpt_if}, {rob_uop_27_bp_xcpt_if}, {rob_uop_26_bp_xcpt_if}, {rob_uop_25_bp_xcpt_if}, {rob_uop_24_bp_xcpt_if}, {rob_uop_23_bp_xcpt_if}, {rob_uop_22_bp_xcpt_if}, {rob_uop_21_bp_xcpt_if}, {rob_uop_20_bp_xcpt_if}, {rob_uop_19_bp_xcpt_if}, {rob_uop_18_bp_xcpt_if}, {rob_uop_17_bp_xcpt_if}, {rob_uop_16_bp_xcpt_if}, {rob_uop_15_bp_xcpt_if}, {rob_uop_14_bp_xcpt_if}, {rob_uop_13_bp_xcpt_if}, {rob_uop_12_bp_xcpt_if}, {rob_uop_11_bp_xcpt_if}, {rob_uop_10_bp_xcpt_if}, {rob_uop_9_bp_xcpt_if}, {rob_uop_8_bp_xcpt_if}, {rob_uop_7_bp_xcpt_if}, {rob_uop_6_bp_xcpt_if}, {rob_uop_5_bp_xcpt_if}, {rob_uop_4_bp_xcpt_if}, {rob_uop_3_bp_xcpt_if}, {rob_uop_2_bp_xcpt_if}, {rob_uop_1_bp_xcpt_if}, {rob_uop_0_bp_xcpt_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_bp_xcpt_if = _GEN_121[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_122 = {{rob_uop_31_debug_fsrc}, {rob_uop_30_debug_fsrc}, {rob_uop_29_debug_fsrc}, {rob_uop_28_debug_fsrc}, {rob_uop_27_debug_fsrc}, {rob_uop_26_debug_fsrc}, {rob_uop_25_debug_fsrc}, {rob_uop_24_debug_fsrc}, {rob_uop_23_debug_fsrc}, {rob_uop_22_debug_fsrc}, {rob_uop_21_debug_fsrc}, {rob_uop_20_debug_fsrc}, {rob_uop_19_debug_fsrc}, {rob_uop_18_debug_fsrc}, {rob_uop_17_debug_fsrc}, {rob_uop_16_debug_fsrc}, {rob_uop_15_debug_fsrc}, {rob_uop_14_debug_fsrc}, {rob_uop_13_debug_fsrc}, {rob_uop_12_debug_fsrc}, {rob_uop_11_debug_fsrc}, {rob_uop_10_debug_fsrc}, {rob_uop_9_debug_fsrc}, {rob_uop_8_debug_fsrc}, {rob_uop_7_debug_fsrc}, {rob_uop_6_debug_fsrc}, {rob_uop_5_debug_fsrc}, {rob_uop_4_debug_fsrc}, {rob_uop_3_debug_fsrc}, {rob_uop_2_debug_fsrc}, {rob_uop_1_debug_fsrc}, {rob_uop_0_debug_fsrc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_debug_fsrc = _GEN_122[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_123 = {{rob_uop_31_debug_tsrc}, {rob_uop_30_debug_tsrc}, {rob_uop_29_debug_tsrc}, {rob_uop_28_debug_tsrc}, {rob_uop_27_debug_tsrc}, {rob_uop_26_debug_tsrc}, {rob_uop_25_debug_tsrc}, {rob_uop_24_debug_tsrc}, {rob_uop_23_debug_tsrc}, {rob_uop_22_debug_tsrc}, {rob_uop_21_debug_tsrc}, {rob_uop_20_debug_tsrc}, {rob_uop_19_debug_tsrc}, {rob_uop_18_debug_tsrc}, {rob_uop_17_debug_tsrc}, {rob_uop_16_debug_tsrc}, {rob_uop_15_debug_tsrc}, {rob_uop_14_debug_tsrc}, {rob_uop_13_debug_tsrc}, {rob_uop_12_debug_tsrc}, {rob_uop_11_debug_tsrc}, {rob_uop_10_debug_tsrc}, {rob_uop_9_debug_tsrc}, {rob_uop_8_debug_tsrc}, {rob_uop_7_debug_tsrc}, {rob_uop_6_debug_tsrc}, {rob_uop_5_debug_tsrc}, {rob_uop_4_debug_tsrc}, {rob_uop_3_debug_tsrc}, {rob_uop_2_debug_tsrc}, {rob_uop_1_debug_tsrc}, {rob_uop_0_debug_tsrc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_0_out_debug_tsrc = _GEN_123[rob_head]; // @[rob.scala:210:29, :313:23]
wire _T_145 = io_brupdate_b2_mispredict_0 & ~brupdate_b2_rob_bank_idx & io_brupdate_b2_uop_rob_idx_0[5:1] == rob_head; // @[rob.scala:199:7, :210:29, :254:25, :258:36, :355:53, :463:37, :464:57, :465:45]
assign io_commit_uops_0_debug_fsrc_0 = _T_145 ? 3'h4 : io_commit_uops_0_out_debug_fsrc; // @[rob.scala:199:7, :313:23, :458:30, :463:37, :464:57, :465:59, :466:36]
assign io_commit_uops_0_taken_0 = _T_145 ? io_brupdate_b2_taken_0 : io_commit_uops_0_out_taken; // @[rob.scala:199:7, :313:23, :458:30, :463:37, :464:57, :465:59, :467:36]
assign rob_head_fflags_0_valid = _GEN_4[rob_head]; // @[rob.scala:210:29, :238:33, :402:18, :518:26]
wire [31:0][4:0] _GEN_124 = {{rob_fflags_31_bits}, {rob_fflags_30_bits}, {rob_fflags_29_bits}, {rob_fflags_28_bits}, {rob_fflags_27_bits}, {rob_fflags_26_bits}, {rob_fflags_25_bits}, {rob_fflags_24_bits}, {rob_fflags_23_bits}, {rob_fflags_22_bits}, {rob_fflags_21_bits}, {rob_fflags_20_bits}, {rob_fflags_19_bits}, {rob_fflags_18_bits}, {rob_fflags_17_bits}, {rob_fflags_16_bits}, {rob_fflags_15_bits}, {rob_fflags_14_bits}, {rob_fflags_13_bits}, {rob_fflags_12_bits}, {rob_fflags_11_bits}, {rob_fflags_10_bits}, {rob_fflags_9_bits}, {rob_fflags_8_bits}, {rob_fflags_7_bits}, {rob_fflags_6_bits}, {rob_fflags_5_bits}, {rob_fflags_4_bits}, {rob_fflags_3_bits}, {rob_fflags_2_bits}, {rob_fflags_1_bits}, {rob_fflags_0_bits}}; // @[rob.scala:364:28, :518:26]
assign rob_head_fflags_0_bits = _GEN_124[rob_head]; // @[rob.scala:210:29, :238:33, :518:26]
wire _rob_unsafe_masked_0_T = rob_unsafe_0 | rob_exception_0; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_0_T_1 = rob_val_0 & _rob_unsafe_masked_0_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_0 = _rob_unsafe_masked_0_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_2_T = rob_unsafe_1 | rob_exception_1; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_2_T_1 = rob_val_1 & _rob_unsafe_masked_2_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_2 = _rob_unsafe_masked_2_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_4_T = rob_unsafe_2 | rob_exception_2; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_4_T_1 = rob_val_2 & _rob_unsafe_masked_4_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_4 = _rob_unsafe_masked_4_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_6_T = rob_unsafe_3 | rob_exception_3; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_6_T_1 = rob_val_3 & _rob_unsafe_masked_6_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_6 = _rob_unsafe_masked_6_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_8_T = rob_unsafe_4 | rob_exception_4; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_8_T_1 = rob_val_4 & _rob_unsafe_masked_8_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_8 = _rob_unsafe_masked_8_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_10_T = rob_unsafe_5 | rob_exception_5; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_10_T_1 = rob_val_5 & _rob_unsafe_masked_10_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_10 = _rob_unsafe_masked_10_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_12_T = rob_unsafe_6 | rob_exception_6; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_12_T_1 = rob_val_6 & _rob_unsafe_masked_12_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_12 = _rob_unsafe_masked_12_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_14_T = rob_unsafe_7 | rob_exception_7; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_14_T_1 = rob_val_7 & _rob_unsafe_masked_14_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_14 = _rob_unsafe_masked_14_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_16_T = rob_unsafe_8 | rob_exception_8; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_16_T_1 = rob_val_8 & _rob_unsafe_masked_16_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_16 = _rob_unsafe_masked_16_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_18_T = rob_unsafe_9 | rob_exception_9; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_18_T_1 = rob_val_9 & _rob_unsafe_masked_18_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_18 = _rob_unsafe_masked_18_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_20_T = rob_unsafe_10 | rob_exception_10; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_20_T_1 = rob_val_10 & _rob_unsafe_masked_20_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_20 = _rob_unsafe_masked_20_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_22_T = rob_unsafe_11 | rob_exception_11; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_22_T_1 = rob_val_11 & _rob_unsafe_masked_22_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_22 = _rob_unsafe_masked_22_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_24_T = rob_unsafe_12 | rob_exception_12; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_24_T_1 = rob_val_12 & _rob_unsafe_masked_24_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_24 = _rob_unsafe_masked_24_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_26_T = rob_unsafe_13 | rob_exception_13; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_26_T_1 = rob_val_13 & _rob_unsafe_masked_26_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_26 = _rob_unsafe_masked_26_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_28_T = rob_unsafe_14 | rob_exception_14; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_28_T_1 = rob_val_14 & _rob_unsafe_masked_28_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_28 = _rob_unsafe_masked_28_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_30_T = rob_unsafe_15 | rob_exception_15; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_30_T_1 = rob_val_15 & _rob_unsafe_masked_30_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_30 = _rob_unsafe_masked_30_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_32_T = rob_unsafe_16 | rob_exception_16; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_32_T_1 = rob_val_16 & _rob_unsafe_masked_32_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_32 = _rob_unsafe_masked_32_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_34_T = rob_unsafe_17 | rob_exception_17; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_34_T_1 = rob_val_17 & _rob_unsafe_masked_34_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_34 = _rob_unsafe_masked_34_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_36_T = rob_unsafe_18 | rob_exception_18; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_36_T_1 = rob_val_18 & _rob_unsafe_masked_36_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_36 = _rob_unsafe_masked_36_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_38_T = rob_unsafe_19 | rob_exception_19; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_38_T_1 = rob_val_19 & _rob_unsafe_masked_38_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_38 = _rob_unsafe_masked_38_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_40_T = rob_unsafe_20 | rob_exception_20; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_40_T_1 = rob_val_20 & _rob_unsafe_masked_40_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_40 = _rob_unsafe_masked_40_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_42_T = rob_unsafe_21 | rob_exception_21; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_42_T_1 = rob_val_21 & _rob_unsafe_masked_42_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_42 = _rob_unsafe_masked_42_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_44_T = rob_unsafe_22 | rob_exception_22; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_44_T_1 = rob_val_22 & _rob_unsafe_masked_44_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_44 = _rob_unsafe_masked_44_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_46_T = rob_unsafe_23 | rob_exception_23; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_46_T_1 = rob_val_23 & _rob_unsafe_masked_46_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_46 = _rob_unsafe_masked_46_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_48_T = rob_unsafe_24 | rob_exception_24; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_48_T_1 = rob_val_24 & _rob_unsafe_masked_48_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_48 = _rob_unsafe_masked_48_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_50_T = rob_unsafe_25 | rob_exception_25; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_50_T_1 = rob_val_25 & _rob_unsafe_masked_50_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_50 = _rob_unsafe_masked_50_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_52_T = rob_unsafe_26 | rob_exception_26; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_52_T_1 = rob_val_26 & _rob_unsafe_masked_52_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_52 = _rob_unsafe_masked_52_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_54_T = rob_unsafe_27 | rob_exception_27; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_54_T_1 = rob_val_27 & _rob_unsafe_masked_54_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_54 = _rob_unsafe_masked_54_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_56_T = rob_unsafe_28 | rob_exception_28; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_56_T_1 = rob_val_28 & _rob_unsafe_masked_56_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_56 = _rob_unsafe_masked_56_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_58_T = rob_unsafe_29 | rob_exception_29; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_58_T_1 = rob_val_29 & _rob_unsafe_masked_58_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_58 = _rob_unsafe_masked_58_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_60_T = rob_unsafe_30 | rob_exception_30; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_60_T_1 = rob_val_30 & _rob_unsafe_masked_60_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_60 = _rob_unsafe_masked_60_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_62_T = rob_unsafe_31 | rob_exception_31; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_62_T_1 = rob_val_31 & _rob_unsafe_masked_62_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_62 = _rob_unsafe_masked_62_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_pnr_unsafe_0_T = _GEN_17[rob_pnr] | _GEN_19[rob_pnr]; // @[rob.scala:218:29, :437:15, :444:49, :528:67]
assign _rob_pnr_unsafe_0_T_1 = _GEN_2[rob_pnr] & _rob_pnr_unsafe_0_T; // @[rob.scala:218:29, :375:31, :528:{43,67}]
assign rob_pnr_unsafe_0 = _rob_pnr_unsafe_0_T_1; // @[rob.scala:233:33, :528:43]
wire [4:0] _temp_uop_T_1 = _temp_uop_T[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_3 = _temp_uop_T_2[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_5 = _temp_uop_T_4[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_7 = _temp_uop_T_6[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_9 = _temp_uop_T_8[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_11 = _temp_uop_T_10[4:0]; // @[rob.scala:254:25]
reg rob_val_1_0; // @[rob.scala:358:32]
reg rob_val_1_1; // @[rob.scala:358:32]
reg rob_val_1_2; // @[rob.scala:358:32]
reg rob_val_1_3; // @[rob.scala:358:32]
reg rob_val_1_4; // @[rob.scala:358:32]
reg rob_val_1_5; // @[rob.scala:358:32]
reg rob_val_1_6; // @[rob.scala:358:32]
reg rob_val_1_7; // @[rob.scala:358:32]
reg rob_val_1_8; // @[rob.scala:358:32]
reg rob_val_1_9; // @[rob.scala:358:32]
reg rob_val_1_10; // @[rob.scala:358:32]
reg rob_val_1_11; // @[rob.scala:358:32]
reg rob_val_1_12; // @[rob.scala:358:32]
reg rob_val_1_13; // @[rob.scala:358:32]
reg rob_val_1_14; // @[rob.scala:358:32]
reg rob_val_1_15; // @[rob.scala:358:32]
reg rob_val_1_16; // @[rob.scala:358:32]
reg rob_val_1_17; // @[rob.scala:358:32]
reg rob_val_1_18; // @[rob.scala:358:32]
reg rob_val_1_19; // @[rob.scala:358:32]
reg rob_val_1_20; // @[rob.scala:358:32]
reg rob_val_1_21; // @[rob.scala:358:32]
reg rob_val_1_22; // @[rob.scala:358:32]
reg rob_val_1_23; // @[rob.scala:358:32]
reg rob_val_1_24; // @[rob.scala:358:32]
reg rob_val_1_25; // @[rob.scala:358:32]
reg rob_val_1_26; // @[rob.scala:358:32]
reg rob_val_1_27; // @[rob.scala:358:32]
reg rob_val_1_28; // @[rob.scala:358:32]
reg rob_val_1_29; // @[rob.scala:358:32]
reg rob_val_1_30; // @[rob.scala:358:32]
reg rob_val_1_31; // @[rob.scala:358:32]
reg rob_bsy_1_0; // @[rob.scala:359:28]
reg rob_bsy_1_1; // @[rob.scala:359:28]
reg rob_bsy_1_2; // @[rob.scala:359:28]
reg rob_bsy_1_3; // @[rob.scala:359:28]
reg rob_bsy_1_4; // @[rob.scala:359:28]
reg rob_bsy_1_5; // @[rob.scala:359:28]
reg rob_bsy_1_6; // @[rob.scala:359:28]
reg rob_bsy_1_7; // @[rob.scala:359:28]
reg rob_bsy_1_8; // @[rob.scala:359:28]
reg rob_bsy_1_9; // @[rob.scala:359:28]
reg rob_bsy_1_10; // @[rob.scala:359:28]
reg rob_bsy_1_11; // @[rob.scala:359:28]
reg rob_bsy_1_12; // @[rob.scala:359:28]
reg rob_bsy_1_13; // @[rob.scala:359:28]
reg rob_bsy_1_14; // @[rob.scala:359:28]
reg rob_bsy_1_15; // @[rob.scala:359:28]
reg rob_bsy_1_16; // @[rob.scala:359:28]
reg rob_bsy_1_17; // @[rob.scala:359:28]
reg rob_bsy_1_18; // @[rob.scala:359:28]
reg rob_bsy_1_19; // @[rob.scala:359:28]
reg rob_bsy_1_20; // @[rob.scala:359:28]
reg rob_bsy_1_21; // @[rob.scala:359:28]
reg rob_bsy_1_22; // @[rob.scala:359:28]
reg rob_bsy_1_23; // @[rob.scala:359:28]
reg rob_bsy_1_24; // @[rob.scala:359:28]
reg rob_bsy_1_25; // @[rob.scala:359:28]
reg rob_bsy_1_26; // @[rob.scala:359:28]
reg rob_bsy_1_27; // @[rob.scala:359:28]
reg rob_bsy_1_28; // @[rob.scala:359:28]
reg rob_bsy_1_29; // @[rob.scala:359:28]
reg rob_bsy_1_30; // @[rob.scala:359:28]
reg rob_bsy_1_31; // @[rob.scala:359:28]
reg rob_unsafe_1_0; // @[rob.scala:360:28]
reg rob_unsafe_1_1; // @[rob.scala:360:28]
reg rob_unsafe_1_2; // @[rob.scala:360:28]
reg rob_unsafe_1_3; // @[rob.scala:360:28]
reg rob_unsafe_1_4; // @[rob.scala:360:28]
reg rob_unsafe_1_5; // @[rob.scala:360:28]
reg rob_unsafe_1_6; // @[rob.scala:360:28]
reg rob_unsafe_1_7; // @[rob.scala:360:28]
reg rob_unsafe_1_8; // @[rob.scala:360:28]
reg rob_unsafe_1_9; // @[rob.scala:360:28]
reg rob_unsafe_1_10; // @[rob.scala:360:28]
reg rob_unsafe_1_11; // @[rob.scala:360:28]
reg rob_unsafe_1_12; // @[rob.scala:360:28]
reg rob_unsafe_1_13; // @[rob.scala:360:28]
reg rob_unsafe_1_14; // @[rob.scala:360:28]
reg rob_unsafe_1_15; // @[rob.scala:360:28]
reg rob_unsafe_1_16; // @[rob.scala:360:28]
reg rob_unsafe_1_17; // @[rob.scala:360:28]
reg rob_unsafe_1_18; // @[rob.scala:360:28]
reg rob_unsafe_1_19; // @[rob.scala:360:28]
reg rob_unsafe_1_20; // @[rob.scala:360:28]
reg rob_unsafe_1_21; // @[rob.scala:360:28]
reg rob_unsafe_1_22; // @[rob.scala:360:28]
reg rob_unsafe_1_23; // @[rob.scala:360:28]
reg rob_unsafe_1_24; // @[rob.scala:360:28]
reg rob_unsafe_1_25; // @[rob.scala:360:28]
reg rob_unsafe_1_26; // @[rob.scala:360:28]
reg rob_unsafe_1_27; // @[rob.scala:360:28]
reg rob_unsafe_1_28; // @[rob.scala:360:28]
reg rob_unsafe_1_29; // @[rob.scala:360:28]
reg rob_unsafe_1_30; // @[rob.scala:360:28]
reg rob_unsafe_1_31; // @[rob.scala:360:28]
reg [31:0] rob_uop_1_0_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_0_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_0_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_0_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_0_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_0_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_0_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_0_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_0_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_0_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_0_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_0_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_0_br_type; // @[rob.scala:361:28]
reg rob_uop_1_0_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_0_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_0_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_0_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_0_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_0_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_0_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_0_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_0_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_0_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_0_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_0_taken; // @[rob.scala:361:28]
reg rob_uop_1_0_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_0_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_0_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_0_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_0_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_0_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_0_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_0_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_0_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_0_ppred; // @[rob.scala:361:28]
reg rob_uop_1_0_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_0_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_0_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_0_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_0_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_0_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_0_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_0_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_0_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_0_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_0_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_0_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_0_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_0_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_0_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_0_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_0_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_0_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_0_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_0_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_0_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_0_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_0_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_0_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_0_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_0_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_1_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_1_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_1_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_1_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_1_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_1_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_1_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_1_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_1_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_1_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_1_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_1_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_1_br_type; // @[rob.scala:361:28]
reg rob_uop_1_1_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_1_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_1_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_1_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_1_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_1_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_1_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_1_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_1_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_1_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_1_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_1_taken; // @[rob.scala:361:28]
reg rob_uop_1_1_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_1_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_1_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_1_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_1_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_1_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_1_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_1_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_1_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_1_ppred; // @[rob.scala:361:28]
reg rob_uop_1_1_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_1_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_1_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_1_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_1_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_1_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_1_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_1_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_1_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_1_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_1_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_1_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_1_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_1_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_1_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_1_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_1_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_1_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_1_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_1_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_1_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_1_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_1_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_1_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_1_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_1_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_2_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_2_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_2_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_2_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_2_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_2_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_2_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_2_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_2_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_2_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_2_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_2_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_2_br_type; // @[rob.scala:361:28]
reg rob_uop_1_2_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_2_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_2_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_2_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_2_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_2_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_2_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_2_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_2_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_2_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_2_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_2_taken; // @[rob.scala:361:28]
reg rob_uop_1_2_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_2_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_2_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_2_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_2_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_2_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_2_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_2_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_2_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_2_ppred; // @[rob.scala:361:28]
reg rob_uop_1_2_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_2_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_2_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_2_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_2_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_2_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_2_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_2_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_2_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_2_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_2_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_2_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_2_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_2_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_2_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_2_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_2_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_2_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_2_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_2_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_2_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_2_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_2_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_2_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_2_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_2_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_3_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_3_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_3_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_3_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_3_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_3_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_3_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_3_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_3_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_3_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_3_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_3_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_3_br_type; // @[rob.scala:361:28]
reg rob_uop_1_3_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_3_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_3_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_3_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_3_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_3_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_3_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_3_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_3_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_3_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_3_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_3_taken; // @[rob.scala:361:28]
reg rob_uop_1_3_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_3_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_3_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_3_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_3_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_3_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_3_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_3_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_3_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_3_ppred; // @[rob.scala:361:28]
reg rob_uop_1_3_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_3_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_3_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_3_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_3_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_3_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_3_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_3_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_3_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_3_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_3_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_3_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_3_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_3_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_3_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_3_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_3_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_3_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_3_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_3_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_3_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_3_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_3_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_3_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_3_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_3_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_4_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_4_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_4_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_4_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_4_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_4_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_4_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_4_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_4_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_4_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_4_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_4_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_4_br_type; // @[rob.scala:361:28]
reg rob_uop_1_4_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_4_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_4_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_4_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_4_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_4_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_4_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_4_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_4_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_4_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_4_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_4_taken; // @[rob.scala:361:28]
reg rob_uop_1_4_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_4_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_4_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_4_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_4_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_4_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_4_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_4_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_4_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_4_ppred; // @[rob.scala:361:28]
reg rob_uop_1_4_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_4_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_4_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_4_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_4_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_4_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_4_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_4_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_4_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_4_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_4_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_4_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_4_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_4_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_4_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_4_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_4_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_4_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_4_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_4_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_4_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_4_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_4_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_4_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_4_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_4_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_5_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_5_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_5_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_5_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_5_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_5_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_5_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_5_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_5_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_5_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_5_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_5_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_5_br_type; // @[rob.scala:361:28]
reg rob_uop_1_5_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_5_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_5_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_5_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_5_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_5_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_5_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_5_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_5_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_5_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_5_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_5_taken; // @[rob.scala:361:28]
reg rob_uop_1_5_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_5_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_5_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_5_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_5_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_5_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_5_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_5_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_5_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_5_ppred; // @[rob.scala:361:28]
reg rob_uop_1_5_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_5_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_5_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_5_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_5_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_5_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_5_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_5_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_5_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_5_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_5_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_5_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_5_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_5_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_5_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_5_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_5_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_5_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_5_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_5_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_5_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_5_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_5_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_5_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_5_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_5_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_6_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_6_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_6_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_6_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_6_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_6_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_6_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_6_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_6_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_6_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_6_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_6_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_6_br_type; // @[rob.scala:361:28]
reg rob_uop_1_6_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_6_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_6_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_6_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_6_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_6_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_6_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_6_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_6_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_6_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_6_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_6_taken; // @[rob.scala:361:28]
reg rob_uop_1_6_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_6_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_6_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_6_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_6_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_6_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_6_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_6_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_6_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_6_ppred; // @[rob.scala:361:28]
reg rob_uop_1_6_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_6_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_6_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_6_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_6_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_6_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_6_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_6_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_6_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_6_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_6_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_6_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_6_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_6_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_6_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_6_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_6_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_6_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_6_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_6_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_6_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_6_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_6_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_6_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_6_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_6_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_7_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_7_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_7_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_7_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_7_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_7_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_7_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_7_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_7_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_7_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_7_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_7_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_7_br_type; // @[rob.scala:361:28]
reg rob_uop_1_7_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_7_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_7_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_7_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_7_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_7_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_7_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_7_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_7_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_7_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_7_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_7_taken; // @[rob.scala:361:28]
reg rob_uop_1_7_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_7_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_7_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_7_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_7_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_7_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_7_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_7_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_7_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_7_ppred; // @[rob.scala:361:28]
reg rob_uop_1_7_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_7_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_7_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_7_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_7_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_7_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_7_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_7_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_7_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_7_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_7_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_7_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_7_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_7_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_7_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_7_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_7_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_7_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_7_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_7_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_7_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_7_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_7_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_7_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_7_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_7_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_8_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_8_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_8_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_8_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_8_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_8_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_8_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_8_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_8_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_8_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_8_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_8_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_8_br_type; // @[rob.scala:361:28]
reg rob_uop_1_8_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_8_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_8_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_8_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_8_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_8_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_8_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_8_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_8_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_8_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_8_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_8_taken; // @[rob.scala:361:28]
reg rob_uop_1_8_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_8_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_8_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_8_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_8_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_8_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_8_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_8_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_8_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_8_ppred; // @[rob.scala:361:28]
reg rob_uop_1_8_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_8_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_8_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_8_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_8_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_8_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_8_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_8_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_8_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_8_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_8_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_8_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_8_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_8_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_8_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_8_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_8_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_8_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_8_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_8_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_8_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_8_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_8_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_8_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_8_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_8_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_9_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_9_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_9_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_9_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_9_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_9_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_9_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_9_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_9_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_9_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_9_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_9_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_9_br_type; // @[rob.scala:361:28]
reg rob_uop_1_9_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_9_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_9_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_9_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_9_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_9_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_9_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_9_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_9_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_9_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_9_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_9_taken; // @[rob.scala:361:28]
reg rob_uop_1_9_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_9_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_9_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_9_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_9_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_9_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_9_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_9_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_9_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_9_ppred; // @[rob.scala:361:28]
reg rob_uop_1_9_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_9_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_9_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_9_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_9_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_9_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_9_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_9_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_9_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_9_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_9_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_9_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_9_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_9_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_9_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_9_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_9_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_9_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_9_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_9_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_9_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_9_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_9_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_9_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_9_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_9_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_10_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_10_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_10_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_10_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_10_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_10_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_10_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_10_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_10_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_10_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_10_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_10_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_10_br_type; // @[rob.scala:361:28]
reg rob_uop_1_10_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_10_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_10_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_10_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_10_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_10_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_10_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_10_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_10_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_10_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_10_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_10_taken; // @[rob.scala:361:28]
reg rob_uop_1_10_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_10_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_10_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_10_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_10_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_10_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_10_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_10_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_10_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_10_ppred; // @[rob.scala:361:28]
reg rob_uop_1_10_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_10_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_10_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_10_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_10_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_10_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_10_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_10_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_10_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_10_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_10_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_10_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_10_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_10_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_10_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_10_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_10_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_10_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_10_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_10_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_10_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_10_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_10_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_10_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_10_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_10_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_11_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_11_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_11_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_11_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_11_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_11_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_11_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_11_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_11_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_11_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_11_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_11_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_11_br_type; // @[rob.scala:361:28]
reg rob_uop_1_11_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_11_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_11_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_11_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_11_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_11_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_11_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_11_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_11_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_11_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_11_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_11_taken; // @[rob.scala:361:28]
reg rob_uop_1_11_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_11_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_11_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_11_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_11_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_11_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_11_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_11_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_11_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_11_ppred; // @[rob.scala:361:28]
reg rob_uop_1_11_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_11_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_11_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_11_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_11_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_11_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_11_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_11_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_11_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_11_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_11_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_11_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_11_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_11_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_11_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_11_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_11_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_11_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_11_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_11_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_11_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_11_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_11_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_11_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_11_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_11_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_12_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_12_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_12_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_12_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_12_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_12_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_12_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_12_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_12_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_12_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_12_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_12_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_12_br_type; // @[rob.scala:361:28]
reg rob_uop_1_12_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_12_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_12_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_12_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_12_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_12_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_12_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_12_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_12_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_12_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_12_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_12_taken; // @[rob.scala:361:28]
reg rob_uop_1_12_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_12_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_12_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_12_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_12_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_12_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_12_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_12_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_12_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_12_ppred; // @[rob.scala:361:28]
reg rob_uop_1_12_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_12_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_12_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_12_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_12_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_12_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_12_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_12_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_12_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_12_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_12_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_12_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_12_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_12_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_12_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_12_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_12_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_12_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_12_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_12_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_12_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_12_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_12_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_12_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_12_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_12_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_13_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_13_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_13_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_13_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_13_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_13_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_13_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_13_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_13_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_13_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_13_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_13_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_13_br_type; // @[rob.scala:361:28]
reg rob_uop_1_13_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_13_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_13_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_13_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_13_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_13_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_13_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_13_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_13_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_13_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_13_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_13_taken; // @[rob.scala:361:28]
reg rob_uop_1_13_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_13_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_13_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_13_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_13_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_13_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_13_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_13_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_13_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_13_ppred; // @[rob.scala:361:28]
reg rob_uop_1_13_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_13_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_13_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_13_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_13_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_13_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_13_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_13_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_13_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_13_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_13_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_13_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_13_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_13_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_13_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_13_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_13_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_13_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_13_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_13_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_13_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_13_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_13_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_13_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_13_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_13_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_14_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_14_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_14_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_14_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_14_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_14_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_14_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_14_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_14_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_14_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_14_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_14_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_14_br_type; // @[rob.scala:361:28]
reg rob_uop_1_14_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_14_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_14_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_14_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_14_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_14_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_14_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_14_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_14_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_14_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_14_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_14_taken; // @[rob.scala:361:28]
reg rob_uop_1_14_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_14_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_14_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_14_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_14_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_14_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_14_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_14_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_14_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_14_ppred; // @[rob.scala:361:28]
reg rob_uop_1_14_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_14_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_14_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_14_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_14_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_14_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_14_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_14_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_14_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_14_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_14_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_14_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_14_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_14_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_14_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_14_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_14_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_14_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_14_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_14_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_14_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_14_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_14_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_14_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_14_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_14_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_15_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_15_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_15_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_15_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_15_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_15_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_15_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_15_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_15_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_15_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_15_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_15_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_15_br_type; // @[rob.scala:361:28]
reg rob_uop_1_15_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_15_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_15_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_15_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_15_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_15_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_15_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_15_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_15_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_15_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_15_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_15_taken; // @[rob.scala:361:28]
reg rob_uop_1_15_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_15_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_15_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_15_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_15_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_15_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_15_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_15_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_15_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_15_ppred; // @[rob.scala:361:28]
reg rob_uop_1_15_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_15_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_15_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_15_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_15_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_15_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_15_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_15_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_15_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_15_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_15_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_15_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_15_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_15_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_15_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_15_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_15_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_15_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_15_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_15_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_15_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_15_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_15_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_15_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_15_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_15_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_16_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_16_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_16_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_16_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_16_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_16_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_16_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_16_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_16_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_16_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_16_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_16_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_16_br_type; // @[rob.scala:361:28]
reg rob_uop_1_16_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_16_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_16_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_16_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_16_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_16_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_16_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_16_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_16_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_16_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_16_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_16_taken; // @[rob.scala:361:28]
reg rob_uop_1_16_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_16_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_16_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_16_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_16_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_16_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_16_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_16_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_16_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_16_ppred; // @[rob.scala:361:28]
reg rob_uop_1_16_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_16_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_16_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_16_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_16_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_16_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_16_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_16_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_16_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_16_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_16_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_16_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_16_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_16_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_16_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_16_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_16_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_16_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_16_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_16_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_16_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_16_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_16_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_16_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_16_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_16_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_17_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_17_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_17_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_17_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_17_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_17_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_17_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_17_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_17_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_17_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_17_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_17_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_17_br_type; // @[rob.scala:361:28]
reg rob_uop_1_17_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_17_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_17_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_17_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_17_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_17_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_17_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_17_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_17_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_17_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_17_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_17_taken; // @[rob.scala:361:28]
reg rob_uop_1_17_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_17_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_17_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_17_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_17_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_17_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_17_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_17_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_17_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_17_ppred; // @[rob.scala:361:28]
reg rob_uop_1_17_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_17_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_17_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_17_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_17_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_17_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_17_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_17_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_17_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_17_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_17_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_17_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_17_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_17_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_17_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_17_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_17_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_17_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_17_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_17_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_17_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_17_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_17_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_17_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_17_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_17_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_18_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_18_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_18_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_18_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_18_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_18_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_18_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_18_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_18_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_18_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_18_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_18_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_18_br_type; // @[rob.scala:361:28]
reg rob_uop_1_18_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_18_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_18_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_18_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_18_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_18_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_18_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_18_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_18_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_18_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_18_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_18_taken; // @[rob.scala:361:28]
reg rob_uop_1_18_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_18_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_18_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_18_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_18_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_18_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_18_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_18_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_18_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_18_ppred; // @[rob.scala:361:28]
reg rob_uop_1_18_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_18_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_18_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_18_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_18_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_18_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_18_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_18_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_18_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_18_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_18_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_18_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_18_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_18_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_18_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_18_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_18_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_18_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_18_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_18_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_18_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_18_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_18_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_18_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_18_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_18_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_19_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_19_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_19_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_19_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_19_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_19_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_19_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_19_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_19_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_19_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_19_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_19_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_19_br_type; // @[rob.scala:361:28]
reg rob_uop_1_19_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_19_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_19_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_19_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_19_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_19_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_19_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_19_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_19_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_19_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_19_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_19_taken; // @[rob.scala:361:28]
reg rob_uop_1_19_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_19_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_19_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_19_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_19_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_19_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_19_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_19_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_19_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_19_ppred; // @[rob.scala:361:28]
reg rob_uop_1_19_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_19_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_19_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_19_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_19_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_19_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_19_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_19_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_19_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_19_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_19_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_19_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_19_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_19_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_19_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_19_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_19_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_19_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_19_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_19_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_19_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_19_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_19_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_19_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_19_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_19_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_20_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_20_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_20_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_20_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_20_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_20_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_20_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_20_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_20_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_20_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_20_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_20_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_20_br_type; // @[rob.scala:361:28]
reg rob_uop_1_20_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_20_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_20_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_20_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_20_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_20_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_20_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_20_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_20_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_20_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_20_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_20_taken; // @[rob.scala:361:28]
reg rob_uop_1_20_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_20_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_20_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_20_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_20_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_20_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_20_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_20_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_20_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_20_ppred; // @[rob.scala:361:28]
reg rob_uop_1_20_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_20_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_20_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_20_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_20_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_20_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_20_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_20_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_20_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_20_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_20_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_20_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_20_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_20_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_20_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_20_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_20_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_20_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_20_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_20_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_20_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_20_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_20_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_20_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_20_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_20_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_21_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_21_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_21_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_21_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_21_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_21_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_21_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_21_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_21_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_21_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_21_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_21_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_21_br_type; // @[rob.scala:361:28]
reg rob_uop_1_21_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_21_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_21_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_21_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_21_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_21_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_21_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_21_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_21_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_21_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_21_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_21_taken; // @[rob.scala:361:28]
reg rob_uop_1_21_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_21_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_21_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_21_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_21_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_21_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_21_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_21_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_21_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_21_ppred; // @[rob.scala:361:28]
reg rob_uop_1_21_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_21_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_21_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_21_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_21_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_21_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_21_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_21_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_21_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_21_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_21_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_21_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_21_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_21_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_21_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_21_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_21_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_21_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_21_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_21_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_21_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_21_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_21_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_21_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_21_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_21_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_22_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_22_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_22_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_22_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_22_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_22_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_22_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_22_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_22_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_22_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_22_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_22_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_22_br_type; // @[rob.scala:361:28]
reg rob_uop_1_22_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_22_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_22_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_22_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_22_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_22_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_22_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_22_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_22_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_22_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_22_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_22_taken; // @[rob.scala:361:28]
reg rob_uop_1_22_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_22_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_22_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_22_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_22_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_22_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_22_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_22_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_22_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_22_ppred; // @[rob.scala:361:28]
reg rob_uop_1_22_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_22_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_22_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_22_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_22_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_22_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_22_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_22_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_22_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_22_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_22_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_22_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_22_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_22_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_22_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_22_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_22_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_22_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_22_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_22_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_22_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_22_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_22_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_22_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_22_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_22_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_23_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_23_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_23_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_23_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_23_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_23_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_23_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_23_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_23_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_23_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_23_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_23_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_23_br_type; // @[rob.scala:361:28]
reg rob_uop_1_23_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_23_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_23_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_23_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_23_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_23_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_23_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_23_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_23_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_23_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_23_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_23_taken; // @[rob.scala:361:28]
reg rob_uop_1_23_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_23_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_23_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_23_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_23_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_23_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_23_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_23_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_23_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_23_ppred; // @[rob.scala:361:28]
reg rob_uop_1_23_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_23_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_23_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_23_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_23_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_23_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_23_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_23_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_23_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_23_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_23_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_23_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_23_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_23_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_23_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_23_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_23_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_23_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_23_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_23_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_23_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_23_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_23_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_23_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_23_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_23_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_24_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_24_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_24_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_24_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_24_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_24_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_24_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_24_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_24_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_24_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_24_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_24_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_24_br_type; // @[rob.scala:361:28]
reg rob_uop_1_24_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_24_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_24_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_24_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_24_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_24_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_24_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_24_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_24_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_24_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_24_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_24_taken; // @[rob.scala:361:28]
reg rob_uop_1_24_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_24_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_24_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_24_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_24_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_24_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_24_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_24_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_24_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_24_ppred; // @[rob.scala:361:28]
reg rob_uop_1_24_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_24_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_24_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_24_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_24_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_24_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_24_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_24_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_24_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_24_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_24_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_24_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_24_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_24_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_24_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_24_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_24_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_24_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_24_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_24_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_24_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_24_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_24_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_24_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_24_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_24_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_25_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_25_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_25_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_25_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_25_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_25_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_25_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_25_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_25_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_25_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_25_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_25_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_25_br_type; // @[rob.scala:361:28]
reg rob_uop_1_25_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_25_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_25_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_25_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_25_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_25_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_25_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_25_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_25_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_25_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_25_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_25_taken; // @[rob.scala:361:28]
reg rob_uop_1_25_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_25_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_25_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_25_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_25_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_25_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_25_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_25_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_25_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_25_ppred; // @[rob.scala:361:28]
reg rob_uop_1_25_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_25_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_25_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_25_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_25_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_25_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_25_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_25_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_25_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_25_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_25_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_25_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_25_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_25_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_25_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_25_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_25_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_25_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_25_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_25_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_25_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_25_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_25_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_25_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_25_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_25_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_26_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_26_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_26_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_26_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_26_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_26_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_26_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_26_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_26_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_26_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_26_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_26_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_26_br_type; // @[rob.scala:361:28]
reg rob_uop_1_26_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_26_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_26_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_26_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_26_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_26_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_26_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_26_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_26_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_26_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_26_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_26_taken; // @[rob.scala:361:28]
reg rob_uop_1_26_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_26_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_26_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_26_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_26_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_26_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_26_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_26_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_26_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_26_ppred; // @[rob.scala:361:28]
reg rob_uop_1_26_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_26_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_26_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_26_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_26_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_26_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_26_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_26_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_26_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_26_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_26_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_26_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_26_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_26_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_26_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_26_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_26_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_26_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_26_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_26_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_26_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_26_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_26_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_26_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_26_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_26_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_27_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_27_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_27_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_27_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_27_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_27_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_27_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_27_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_27_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_27_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_27_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_27_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_27_br_type; // @[rob.scala:361:28]
reg rob_uop_1_27_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_27_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_27_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_27_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_27_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_27_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_27_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_27_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_27_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_27_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_27_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_27_taken; // @[rob.scala:361:28]
reg rob_uop_1_27_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_27_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_27_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_27_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_27_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_27_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_27_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_27_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_27_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_27_ppred; // @[rob.scala:361:28]
reg rob_uop_1_27_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_27_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_27_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_27_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_27_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_27_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_27_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_27_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_27_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_27_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_27_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_27_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_27_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_27_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_27_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_27_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_27_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_27_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_27_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_27_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_27_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_27_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_27_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_27_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_27_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_27_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_28_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_28_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_28_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_28_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_28_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_28_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_28_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_28_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_28_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_28_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_28_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_28_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_28_br_type; // @[rob.scala:361:28]
reg rob_uop_1_28_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_28_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_28_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_28_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_28_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_28_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_28_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_28_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_28_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_28_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_28_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_28_taken; // @[rob.scala:361:28]
reg rob_uop_1_28_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_28_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_28_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_28_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_28_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_28_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_28_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_28_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_28_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_28_ppred; // @[rob.scala:361:28]
reg rob_uop_1_28_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_28_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_28_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_28_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_28_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_28_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_28_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_28_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_28_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_28_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_28_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_28_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_28_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_28_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_28_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_28_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_28_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_28_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_28_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_28_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_28_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_28_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_28_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_28_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_28_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_28_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_29_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_29_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_29_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_29_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_29_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_29_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_29_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_29_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_29_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_29_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_29_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_29_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_29_br_type; // @[rob.scala:361:28]
reg rob_uop_1_29_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_29_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_29_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_29_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_29_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_29_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_29_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_29_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_29_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_29_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_29_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_29_taken; // @[rob.scala:361:28]
reg rob_uop_1_29_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_29_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_29_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_29_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_29_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_29_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_29_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_29_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_29_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_29_ppred; // @[rob.scala:361:28]
reg rob_uop_1_29_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_29_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_29_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_29_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_29_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_29_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_29_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_29_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_29_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_29_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_29_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_29_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_29_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_29_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_29_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_29_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_29_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_29_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_29_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_29_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_29_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_29_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_29_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_29_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_29_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_29_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_30_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_30_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_30_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_30_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_30_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_30_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_30_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_30_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_30_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_30_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_30_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_30_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_30_br_type; // @[rob.scala:361:28]
reg rob_uop_1_30_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_30_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_30_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_30_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_30_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_30_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_30_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_30_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_30_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_30_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_30_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_30_taken; // @[rob.scala:361:28]
reg rob_uop_1_30_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_30_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_30_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_30_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_30_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_30_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_30_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_30_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_30_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_30_ppred; // @[rob.scala:361:28]
reg rob_uop_1_30_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_30_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_30_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_30_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_30_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_30_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_30_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_30_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_30_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_30_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_30_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_30_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_30_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_30_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_30_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_30_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_30_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_30_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_30_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_30_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_30_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_30_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_30_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_30_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_30_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_30_debug_tsrc; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_31_inst; // @[rob.scala:361:28]
reg [31:0] rob_uop_1_31_debug_inst; // @[rob.scala:361:28]
reg rob_uop_1_31_is_rvc; // @[rob.scala:361:28]
reg [39:0] rob_uop_1_31_debug_pc; // @[rob.scala:361:28]
reg rob_uop_1_31_iq_type_0; // @[rob.scala:361:28]
reg rob_uop_1_31_iq_type_1; // @[rob.scala:361:28]
reg rob_uop_1_31_iq_type_2; // @[rob.scala:361:28]
reg rob_uop_1_31_iq_type_3; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_0; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_1; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_2; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_3; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_4; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_5; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_6; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_7; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_8; // @[rob.scala:361:28]
reg rob_uop_1_31_fu_code_9; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_issued; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_issued_partial_agen; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_issued_partial_dgen; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_iw_p1_speculative_child; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_iw_p2_speculative_child; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_p1_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_p2_bypass_hint; // @[rob.scala:361:28]
reg rob_uop_1_31_iw_p3_bypass_hint; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_dis_col_sel; // @[rob.scala:361:28]
reg [11:0] rob_uop_1_31_br_mask; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_31_br_tag; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_31_br_type; // @[rob.scala:361:28]
reg rob_uop_1_31_is_sfb; // @[rob.scala:361:28]
reg rob_uop_1_31_is_fence; // @[rob.scala:361:28]
reg rob_uop_1_31_is_fencei; // @[rob.scala:361:28]
reg rob_uop_1_31_is_sfence; // @[rob.scala:361:28]
reg rob_uop_1_31_is_amo; // @[rob.scala:361:28]
reg rob_uop_1_31_is_eret; // @[rob.scala:361:28]
reg rob_uop_1_31_is_sys_pc2epc; // @[rob.scala:361:28]
reg rob_uop_1_31_is_rocc; // @[rob.scala:361:28]
reg rob_uop_1_31_is_mov; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_31_ftq_idx; // @[rob.scala:361:28]
reg rob_uop_1_31_edge_inst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_pc_lob; // @[rob.scala:361:28]
reg rob_uop_1_31_taken; // @[rob.scala:361:28]
reg rob_uop_1_31_imm_rename; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_imm_sel; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_31_pimm; // @[rob.scala:361:28]
reg [19:0] rob_uop_1_31_imm_packed; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_op1_sel; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_op2_sel; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_ldst; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_wen; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_ren1; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_ren2; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_ren3; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_swap12; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_swap23; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_fp_ctrl_typeTagIn; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_fp_ctrl_typeTagOut; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_fromint; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_toint; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_fastpipe; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_fma; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_div; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_sqrt; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_wflags; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_ctrl_vec; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_rob_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_31_ldq_idx; // @[rob.scala:361:28]
reg [3:0] rob_uop_1_31_stq_idx; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_rxq_idx; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_31_pdst; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_31_prs1; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_31_prs2; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_31_prs3; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_31_ppred; // @[rob.scala:361:28]
reg rob_uop_1_31_prs1_busy; // @[rob.scala:361:28]
reg rob_uop_1_31_prs2_busy; // @[rob.scala:361:28]
reg rob_uop_1_31_prs3_busy; // @[rob.scala:361:28]
reg rob_uop_1_31_ppred_busy; // @[rob.scala:361:28]
reg [6:0] rob_uop_1_31_stale_pdst; // @[rob.scala:361:28]
reg rob_uop_1_31_exception; // @[rob.scala:361:28]
reg [63:0] rob_uop_1_31_exc_cause; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_31_mem_cmd; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_mem_size; // @[rob.scala:361:28]
reg rob_uop_1_31_mem_signed; // @[rob.scala:361:28]
reg rob_uop_1_31_uses_ldq; // @[rob.scala:361:28]
reg rob_uop_1_31_uses_stq; // @[rob.scala:361:28]
reg rob_uop_1_31_is_unique; // @[rob.scala:361:28]
reg rob_uop_1_31_flush_on_commit; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_csr_cmd; // @[rob.scala:361:28]
reg rob_uop_1_31_ldst_is_rs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_ldst; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_lrs1; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_lrs2; // @[rob.scala:361:28]
reg [5:0] rob_uop_1_31_lrs3; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_dst_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_lrs1_rtype; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_lrs2_rtype; // @[rob.scala:361:28]
reg rob_uop_1_31_frs3_en; // @[rob.scala:361:28]
reg rob_uop_1_31_fcn_dw; // @[rob.scala:361:28]
reg [4:0] rob_uop_1_31_fcn_op; // @[rob.scala:361:28]
reg rob_uop_1_31_fp_val; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_fp_rm; // @[rob.scala:361:28]
reg [1:0] rob_uop_1_31_fp_typ; // @[rob.scala:361:28]
reg rob_uop_1_31_xcpt_pf_if; // @[rob.scala:361:28]
reg rob_uop_1_31_xcpt_ae_if; // @[rob.scala:361:28]
reg rob_uop_1_31_xcpt_ma_if; // @[rob.scala:361:28]
reg rob_uop_1_31_bp_debug_if; // @[rob.scala:361:28]
reg rob_uop_1_31_bp_xcpt_if; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_debug_fsrc; // @[rob.scala:361:28]
reg [2:0] rob_uop_1_31_debug_tsrc; // @[rob.scala:361:28]
reg rob_exception_1_0; // @[rob.scala:362:28]
reg rob_exception_1_1; // @[rob.scala:362:28]
reg rob_exception_1_2; // @[rob.scala:362:28]
reg rob_exception_1_3; // @[rob.scala:362:28]
reg rob_exception_1_4; // @[rob.scala:362:28]
reg rob_exception_1_5; // @[rob.scala:362:28]
reg rob_exception_1_6; // @[rob.scala:362:28]
reg rob_exception_1_7; // @[rob.scala:362:28]
reg rob_exception_1_8; // @[rob.scala:362:28]
reg rob_exception_1_9; // @[rob.scala:362:28]
reg rob_exception_1_10; // @[rob.scala:362:28]
reg rob_exception_1_11; // @[rob.scala:362:28]
reg rob_exception_1_12; // @[rob.scala:362:28]
reg rob_exception_1_13; // @[rob.scala:362:28]
reg rob_exception_1_14; // @[rob.scala:362:28]
reg rob_exception_1_15; // @[rob.scala:362:28]
reg rob_exception_1_16; // @[rob.scala:362:28]
reg rob_exception_1_17; // @[rob.scala:362:28]
reg rob_exception_1_18; // @[rob.scala:362:28]
reg rob_exception_1_19; // @[rob.scala:362:28]
reg rob_exception_1_20; // @[rob.scala:362:28]
reg rob_exception_1_21; // @[rob.scala:362:28]
reg rob_exception_1_22; // @[rob.scala:362:28]
reg rob_exception_1_23; // @[rob.scala:362:28]
reg rob_exception_1_24; // @[rob.scala:362:28]
reg rob_exception_1_25; // @[rob.scala:362:28]
reg rob_exception_1_26; // @[rob.scala:362:28]
reg rob_exception_1_27; // @[rob.scala:362:28]
reg rob_exception_1_28; // @[rob.scala:362:28]
reg rob_exception_1_29; // @[rob.scala:362:28]
reg rob_exception_1_30; // @[rob.scala:362:28]
reg rob_exception_1_31; // @[rob.scala:362:28]
reg rob_predicated_1_0; // @[rob.scala:363:29]
reg rob_predicated_1_1; // @[rob.scala:363:29]
reg rob_predicated_1_2; // @[rob.scala:363:29]
reg rob_predicated_1_3; // @[rob.scala:363:29]
reg rob_predicated_1_4; // @[rob.scala:363:29]
reg rob_predicated_1_5; // @[rob.scala:363:29]
reg rob_predicated_1_6; // @[rob.scala:363:29]
reg rob_predicated_1_7; // @[rob.scala:363:29]
reg rob_predicated_1_8; // @[rob.scala:363:29]
reg rob_predicated_1_9; // @[rob.scala:363:29]
reg rob_predicated_1_10; // @[rob.scala:363:29]
reg rob_predicated_1_11; // @[rob.scala:363:29]
reg rob_predicated_1_12; // @[rob.scala:363:29]
reg rob_predicated_1_13; // @[rob.scala:363:29]
reg rob_predicated_1_14; // @[rob.scala:363:29]
reg rob_predicated_1_15; // @[rob.scala:363:29]
reg rob_predicated_1_16; // @[rob.scala:363:29]
reg rob_predicated_1_17; // @[rob.scala:363:29]
reg rob_predicated_1_18; // @[rob.scala:363:29]
reg rob_predicated_1_19; // @[rob.scala:363:29]
reg rob_predicated_1_20; // @[rob.scala:363:29]
reg rob_predicated_1_21; // @[rob.scala:363:29]
reg rob_predicated_1_22; // @[rob.scala:363:29]
reg rob_predicated_1_23; // @[rob.scala:363:29]
reg rob_predicated_1_24; // @[rob.scala:363:29]
reg rob_predicated_1_25; // @[rob.scala:363:29]
reg rob_predicated_1_26; // @[rob.scala:363:29]
reg rob_predicated_1_27; // @[rob.scala:363:29]
reg rob_predicated_1_28; // @[rob.scala:363:29]
reg rob_predicated_1_29; // @[rob.scala:363:29]
reg rob_predicated_1_30; // @[rob.scala:363:29]
reg rob_predicated_1_31; // @[rob.scala:363:29]
reg rob_fflags_2_0_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_0_bits; // @[rob.scala:364:28]
reg rob_fflags_2_1_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_1_bits; // @[rob.scala:364:28]
reg rob_fflags_2_2_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_2_bits; // @[rob.scala:364:28]
reg rob_fflags_2_3_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_3_bits; // @[rob.scala:364:28]
reg rob_fflags_2_4_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_4_bits; // @[rob.scala:364:28]
reg rob_fflags_2_5_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_5_bits; // @[rob.scala:364:28]
reg rob_fflags_2_6_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_6_bits; // @[rob.scala:364:28]
reg rob_fflags_2_7_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_7_bits; // @[rob.scala:364:28]
reg rob_fflags_2_8_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_8_bits; // @[rob.scala:364:28]
reg rob_fflags_2_9_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_9_bits; // @[rob.scala:364:28]
reg rob_fflags_2_10_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_10_bits; // @[rob.scala:364:28]
reg rob_fflags_2_11_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_11_bits; // @[rob.scala:364:28]
reg rob_fflags_2_12_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_12_bits; // @[rob.scala:364:28]
reg rob_fflags_2_13_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_13_bits; // @[rob.scala:364:28]
reg rob_fflags_2_14_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_14_bits; // @[rob.scala:364:28]
reg rob_fflags_2_15_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_15_bits; // @[rob.scala:364:28]
reg rob_fflags_2_16_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_16_bits; // @[rob.scala:364:28]
reg rob_fflags_2_17_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_17_bits; // @[rob.scala:364:28]
reg rob_fflags_2_18_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_18_bits; // @[rob.scala:364:28]
reg rob_fflags_2_19_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_19_bits; // @[rob.scala:364:28]
reg rob_fflags_2_20_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_20_bits; // @[rob.scala:364:28]
reg rob_fflags_2_21_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_21_bits; // @[rob.scala:364:28]
reg rob_fflags_2_22_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_22_bits; // @[rob.scala:364:28]
reg rob_fflags_2_23_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_23_bits; // @[rob.scala:364:28]
reg rob_fflags_2_24_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_24_bits; // @[rob.scala:364:28]
reg rob_fflags_2_25_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_25_bits; // @[rob.scala:364:28]
reg rob_fflags_2_26_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_26_bits; // @[rob.scala:364:28]
reg rob_fflags_2_27_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_27_bits; // @[rob.scala:364:28]
reg rob_fflags_2_28_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_28_bits; // @[rob.scala:364:28]
reg rob_fflags_2_29_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_29_bits; // @[rob.scala:364:28]
reg rob_fflags_2_30_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_30_bits; // @[rob.scala:364:28]
reg rob_fflags_2_31_valid; // @[rob.scala:364:28]
reg [4:0] rob_fflags_2_31_bits; // @[rob.scala:364:28]
wire [31:0] _GEN_125 = {{rob_val_1_31}, {rob_val_1_30}, {rob_val_1_29}, {rob_val_1_28}, {rob_val_1_27}, {rob_val_1_26}, {rob_val_1_25}, {rob_val_1_24}, {rob_val_1_23}, {rob_val_1_22}, {rob_val_1_21}, {rob_val_1_20}, {rob_val_1_19}, {rob_val_1_18}, {rob_val_1_17}, {rob_val_1_16}, {rob_val_1_15}, {rob_val_1_14}, {rob_val_1_13}, {rob_val_1_12}, {rob_val_1_11}, {rob_val_1_10}, {rob_val_1_9}, {rob_val_1_8}, {rob_val_1_7}, {rob_val_1_6}, {rob_val_1_5}, {rob_val_1_4}, {rob_val_1_3}, {rob_val_1_2}, {rob_val_1_1}, {rob_val_1_0}}; // @[rob.scala:358:32, :375:31]
assign rob_tail_vals_1 = _GEN_125[rob_tail]; // @[rob.scala:214:29, :235:33, :375:31]
wire _rob_bsy_T_2 = io_enq_uops_1_is_fence_0 | io_enq_uops_1_is_fencei_0; // @[rob.scala:199:7]
wire _rob_bsy_T_3 = ~_rob_bsy_T_2; // @[micro-op.scala:162:{26,37}]
wire _rob_unsafe_T_17 = ~io_enq_uops_1_is_fence_0; // @[rob.scala:199:7]
wire _rob_unsafe_T_18 = io_enq_uops_1_uses_stq_0 & _rob_unsafe_T_17; // @[rob.scala:199:7]
wire _rob_unsafe_T_19 = io_enq_uops_1_uses_ldq_0 | _rob_unsafe_T_18; // @[rob.scala:199:7]
wire _rob_unsafe_T_20 = io_enq_uops_1_br_type_0 == 4'h1; // @[package.scala:16:47]
wire _rob_unsafe_T_21 = io_enq_uops_1_br_type_0 == 4'h2; // @[package.scala:16:47]
wire _rob_unsafe_T_22 = io_enq_uops_1_br_type_0 == 4'h3; // @[package.scala:16:47]
wire _rob_unsafe_T_23 = io_enq_uops_1_br_type_0 == 4'h4; // @[package.scala:16:47]
wire _rob_unsafe_T_24 = io_enq_uops_1_br_type_0 == 4'h5; // @[package.scala:16:47]
wire _rob_unsafe_T_25 = io_enq_uops_1_br_type_0 == 4'h6; // @[package.scala:16:47]
wire _rob_unsafe_T_26 = _rob_unsafe_T_20 | _rob_unsafe_T_21; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_27 = _rob_unsafe_T_26 | _rob_unsafe_T_22; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_28 = _rob_unsafe_T_27 | _rob_unsafe_T_23; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_29 = _rob_unsafe_T_28 | _rob_unsafe_T_24; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_30 = _rob_unsafe_T_29 | _rob_unsafe_T_25; // @[package.scala:16:47, :81:59]
wire _rob_unsafe_T_31 = _rob_unsafe_T_19 | _rob_unsafe_T_30; // @[package.scala:81:59]
wire _rob_unsafe_T_32 = io_enq_uops_1_br_type_0 == 4'h8; // @[rob.scala:199:7]
wire _rob_unsafe_T_33 = _rob_unsafe_T_31 | _rob_unsafe_T_32; // @[micro-op.scala:119:34, :164:{62,71}]
wire _T_588 = io_wb_resps_0_valid_0 & io_wb_resps_0_bits_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36, :397:27]
wire [31:0] _GEN_126 = {{rob_fflags_2_31_valid}, {rob_fflags_2_30_valid}, {rob_fflags_2_29_valid}, {rob_fflags_2_28_valid}, {rob_fflags_2_27_valid}, {rob_fflags_2_26_valid}, {rob_fflags_2_25_valid}, {rob_fflags_2_24_valid}, {rob_fflags_2_23_valid}, {rob_fflags_2_22_valid}, {rob_fflags_2_21_valid}, {rob_fflags_2_20_valid}, {rob_fflags_2_19_valid}, {rob_fflags_2_18_valid}, {rob_fflags_2_17_valid}, {rob_fflags_2_16_valid}, {rob_fflags_2_15_valid}, {rob_fflags_2_14_valid}, {rob_fflags_2_13_valid}, {rob_fflags_2_12_valid}, {rob_fflags_2_11_valid}, {rob_fflags_2_10_valid}, {rob_fflags_2_9_valid}, {rob_fflags_2_8_valid}, {rob_fflags_2_7_valid}, {rob_fflags_2_6_valid}, {rob_fflags_2_5_valid}, {rob_fflags_2_4_valid}, {rob_fflags_2_3_valid}, {rob_fflags_2_2_valid}, {rob_fflags_2_1_valid}, {rob_fflags_2_0_valid}}; // @[rob.scala:364:28, :402:18]
wire _T_601 = io_wb_resps_1_valid_0 & io_wb_resps_1_bits_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36, :397:27]
wire _GEN_127 = _T_601 & io_wb_resps_1_bits_fflags_valid_0; // @[rob.scala:199:7, :397:27, :401:42]
wire _T_640 = io_wb_resps_4_valid_0 & io_wb_resps_4_bits_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36, :397:27]
wire _T_653 = io_wb_resps_5_valid_0 & io_wb_resps_5_bits_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36, :397:27]
wire _GEN_128 = _T_653 & io_wb_resps_5_bits_fflags_valid_0; // @[rob.scala:199:7, :397:27, :401:42]
wire _T_666 = io_lsu_clr_bsy_0_valid_0 & io_lsu_clr_bsy_0_bits_0[0]; // @[rob.scala:199:7, :258:36, :413:31]
wire [31:0] _GEN_129 = {{rob_bsy_1_31}, {rob_bsy_1_30}, {rob_bsy_1_29}, {rob_bsy_1_28}, {rob_bsy_1_27}, {rob_bsy_1_26}, {rob_bsy_1_25}, {rob_bsy_1_24}, {rob_bsy_1_23}, {rob_bsy_1_22}, {rob_bsy_1_21}, {rob_bsy_1_20}, {rob_bsy_1_19}, {rob_bsy_1_18}, {rob_bsy_1_17}, {rob_bsy_1_16}, {rob_bsy_1_15}, {rob_bsy_1_14}, {rob_bsy_1_13}, {rob_bsy_1_12}, {rob_bsy_1_11}, {rob_bsy_1_10}, {rob_bsy_1_9}, {rob_bsy_1_8}, {rob_bsy_1_7}, {rob_bsy_1_6}, {rob_bsy_1_5}, {rob_bsy_1_4}, {rob_bsy_1_3}, {rob_bsy_1_2}, {rob_bsy_1_1}, {rob_bsy_1_0}}; // @[rob.scala:359:28, :418:31]
wire _T_681 = io_lsu_clr_bsy_1_valid_0 & io_lsu_clr_bsy_1_bits_0[0]; // @[rob.scala:199:7, :258:36, :413:31]
wire _T_700 = io_lxcpt_valid_0 & io_lxcpt_bits_uop_rob_idx_0[0]; // @[rob.scala:199:7, :258:36, :433:26]
wire _GEN_130 = _T_700 & io_lxcpt_bits_cause_0 != 5'h10 & ~reset; // @[rob.scala:199:7, :433:26, :435:{33,66}, :437:15]
wire [31:0] _GEN_131 = {{rob_unsafe_1_31}, {rob_unsafe_1_30}, {rob_unsafe_1_29}, {rob_unsafe_1_28}, {rob_unsafe_1_27}, {rob_unsafe_1_26}, {rob_unsafe_1_25}, {rob_unsafe_1_24}, {rob_unsafe_1_23}, {rob_unsafe_1_22}, {rob_unsafe_1_21}, {rob_unsafe_1_20}, {rob_unsafe_1_19}, {rob_unsafe_1_18}, {rob_unsafe_1_17}, {rob_unsafe_1_16}, {rob_unsafe_1_15}, {rob_unsafe_1_14}, {rob_unsafe_1_13}, {rob_unsafe_1_12}, {rob_unsafe_1_11}, {rob_unsafe_1_10}, {rob_unsafe_1_9}, {rob_unsafe_1_8}, {rob_unsafe_1_7}, {rob_unsafe_1_6}, {rob_unsafe_1_5}, {rob_unsafe_1_4}, {rob_unsafe_1_3}, {rob_unsafe_1_2}, {rob_unsafe_1_1}, {rob_unsafe_1_0}}; // @[rob.scala:360:28, :437:15]
wire _GEN_132 = _GEN_131[io_lxcpt_bits_uop_rob_idx_0[5:1]]; // @[rob.scala:199:7, :254:25, :437:15]
assign rob_head_vals_1 = _GEN_125[rob_head]; // @[rob.scala:210:29, :234:33, :375:31, :444:49]
wire [31:0] _GEN_133 = {{rob_exception_1_31}, {rob_exception_1_30}, {rob_exception_1_29}, {rob_exception_1_28}, {rob_exception_1_27}, {rob_exception_1_26}, {rob_exception_1_25}, {rob_exception_1_24}, {rob_exception_1_23}, {rob_exception_1_22}, {rob_exception_1_21}, {rob_exception_1_20}, {rob_exception_1_19}, {rob_exception_1_18}, {rob_exception_1_17}, {rob_exception_1_16}, {rob_exception_1_15}, {rob_exception_1_14}, {rob_exception_1_13}, {rob_exception_1_12}, {rob_exception_1_11}, {rob_exception_1_10}, {rob_exception_1_9}, {rob_exception_1_8}, {rob_exception_1_7}, {rob_exception_1_6}, {rob_exception_1_5}, {rob_exception_1_4}, {rob_exception_1_3}, {rob_exception_1_2}, {rob_exception_1_1}, {rob_exception_1_0}}; // @[rob.scala:362:28, :444:49]
assign _can_throw_exception_1_T = rob_head_vals_1 & _GEN_133[rob_head]; // @[rob.scala:210:29, :234:33, :444:49]
assign can_throw_exception_1 = _can_throw_exception_1_T; // @[rob.scala:231:33, :444:49]
wire _can_commit_1_T = ~_GEN_129[rob_head]; // @[rob.scala:210:29, :418:31, :451:43]
wire _can_commit_1_T_1 = rob_head_vals_1 & _can_commit_1_T; // @[rob.scala:234:33, :451:{40,43}]
wire _can_commit_1_T_2 = ~io_csr_stall_0; // @[rob.scala:199:7, :451:67]
wire _can_commit_1_T_3 = _can_commit_1_T_1 & _can_commit_1_T_2; // @[rob.scala:451:{40,64,67}]
wire _can_commit_1_T_4 = ~io_brupdate_b2_mispredict_0; // @[rob.scala:199:7, :451:84]
assign _can_commit_1_T_5 = _can_commit_1_T_3 & _can_commit_1_T_4; // @[rob.scala:451:{64,81,84}]
assign can_commit_1 = _can_commit_1_T_5; // @[rob.scala:230:33, :451:81]
wire [31:0] _GEN_134 = {{rob_predicated_1_31}, {rob_predicated_1_30}, {rob_predicated_1_29}, {rob_predicated_1_28}, {rob_predicated_1_27}, {rob_predicated_1_26}, {rob_predicated_1_25}, {rob_predicated_1_24}, {rob_predicated_1_23}, {rob_predicated_1_22}, {rob_predicated_1_21}, {rob_predicated_1_20}, {rob_predicated_1_19}, {rob_predicated_1_18}, {rob_predicated_1_17}, {rob_predicated_1_16}, {rob_predicated_1_15}, {rob_predicated_1_14}, {rob_predicated_1_13}, {rob_predicated_1_12}, {rob_predicated_1_11}, {rob_predicated_1_10}, {rob_predicated_1_9}, {rob_predicated_1_8}, {rob_predicated_1_7}, {rob_predicated_1_6}, {rob_predicated_1_5}, {rob_predicated_1_4}, {rob_predicated_1_3}, {rob_predicated_1_2}, {rob_predicated_1_1}, {rob_predicated_1_0}}; // @[rob.scala:363:29, :457:51]
wire _io_commit_arch_valids_1_T = ~_GEN_134[rob_head]; // @[rob.scala:210:29, :457:51]
assign _io_commit_arch_valids_1_T_1 = will_commit_1 & _io_commit_arch_valids_1_T; // @[rob.scala:229:33, :457:{48,51}]
assign io_commit_arch_valids_1_0 = _io_commit_arch_valids_1_T_1; // @[rob.scala:199:7, :457:48]
assign io_commit_uops_1_inst_0 = io_commit_uops_1_out_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_debug_inst_0 = io_commit_uops_1_out_debug_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_rvc_0 = io_commit_uops_1_out_is_rvc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_debug_pc_0 = io_commit_uops_1_out_debug_pc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iq_type_0_0 = io_commit_uops_1_out_iq_type_0; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iq_type_1_0 = io_commit_uops_1_out_iq_type_1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iq_type_2_0 = io_commit_uops_1_out_iq_type_2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iq_type_3_0 = io_commit_uops_1_out_iq_type_3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_0_0 = io_commit_uops_1_out_fu_code_0; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_1_0 = io_commit_uops_1_out_fu_code_1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_2_0 = io_commit_uops_1_out_fu_code_2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_3_0 = io_commit_uops_1_out_fu_code_3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_4_0 = io_commit_uops_1_out_fu_code_4; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_5_0 = io_commit_uops_1_out_fu_code_5; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_6_0 = io_commit_uops_1_out_fu_code_6; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_7_0 = io_commit_uops_1_out_fu_code_7; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_8_0 = io_commit_uops_1_out_fu_code_8; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fu_code_9_0 = io_commit_uops_1_out_fu_code_9; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_issued_0 = io_commit_uops_1_out_iw_issued; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_issued_partial_agen_0 = io_commit_uops_1_out_iw_issued_partial_agen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_issued_partial_dgen_0 = io_commit_uops_1_out_iw_issued_partial_dgen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_p1_speculative_child_0 = io_commit_uops_1_out_iw_p1_speculative_child; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_p2_speculative_child_0 = io_commit_uops_1_out_iw_p2_speculative_child; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_p1_bypass_hint_0 = io_commit_uops_1_out_iw_p1_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_p2_bypass_hint_0 = io_commit_uops_1_out_iw_p2_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_iw_p3_bypass_hint_0 = io_commit_uops_1_out_iw_p3_bypass_hint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_dis_col_sel_0 = io_commit_uops_1_out_dis_col_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_br_mask_0 = io_commit_uops_1_out_br_mask; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_br_tag_0 = io_commit_uops_1_out_br_tag; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_br_type_0 = io_commit_uops_1_out_br_type; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_sfb_0 = io_commit_uops_1_out_is_sfb; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_fence_0 = io_commit_uops_1_out_is_fence; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_fencei_0 = io_commit_uops_1_out_is_fencei; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_sfence_0 = io_commit_uops_1_out_is_sfence; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_amo_0 = io_commit_uops_1_out_is_amo; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_eret_0 = io_commit_uops_1_out_is_eret; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_sys_pc2epc_0 = io_commit_uops_1_out_is_sys_pc2epc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_rocc_0 = io_commit_uops_1_out_is_rocc; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_mov_0 = io_commit_uops_1_out_is_mov; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ftq_idx_0 = io_commit_uops_1_out_ftq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_edge_inst_0 = io_commit_uops_1_out_edge_inst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_pc_lob_0 = io_commit_uops_1_out_pc_lob; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_imm_rename_0 = io_commit_uops_1_out_imm_rename; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_imm_sel_0 = io_commit_uops_1_out_imm_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_pimm_0 = io_commit_uops_1_out_pimm; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_imm_packed_0 = io_commit_uops_1_out_imm_packed; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_op1_sel_0 = io_commit_uops_1_out_op1_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_op2_sel_0 = io_commit_uops_1_out_op2_sel; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_ldst_0 = io_commit_uops_1_out_fp_ctrl_ldst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_wen_0 = io_commit_uops_1_out_fp_ctrl_wen; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_ren1_0 = io_commit_uops_1_out_fp_ctrl_ren1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_ren2_0 = io_commit_uops_1_out_fp_ctrl_ren2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_ren3_0 = io_commit_uops_1_out_fp_ctrl_ren3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_swap12_0 = io_commit_uops_1_out_fp_ctrl_swap12; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_swap23_0 = io_commit_uops_1_out_fp_ctrl_swap23; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_typeTagIn_0 = io_commit_uops_1_out_fp_ctrl_typeTagIn; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_typeTagOut_0 = io_commit_uops_1_out_fp_ctrl_typeTagOut; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_fromint_0 = io_commit_uops_1_out_fp_ctrl_fromint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_toint_0 = io_commit_uops_1_out_fp_ctrl_toint; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_fastpipe_0 = io_commit_uops_1_out_fp_ctrl_fastpipe; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_fma_0 = io_commit_uops_1_out_fp_ctrl_fma; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_div_0 = io_commit_uops_1_out_fp_ctrl_div; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_sqrt_0 = io_commit_uops_1_out_fp_ctrl_sqrt; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_wflags_0 = io_commit_uops_1_out_fp_ctrl_wflags; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_ctrl_vec_0 = io_commit_uops_1_out_fp_ctrl_vec; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_rob_idx_0 = io_commit_uops_1_out_rob_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ldq_idx_0 = io_commit_uops_1_out_ldq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_stq_idx_0 = io_commit_uops_1_out_stq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_rxq_idx_0 = io_commit_uops_1_out_rxq_idx; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_pdst_0 = io_commit_uops_1_out_pdst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs1_0 = io_commit_uops_1_out_prs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs2_0 = io_commit_uops_1_out_prs2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs3_0 = io_commit_uops_1_out_prs3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ppred_0 = io_commit_uops_1_out_ppred; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs1_busy_0 = io_commit_uops_1_out_prs1_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs2_busy_0 = io_commit_uops_1_out_prs2_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_prs3_busy_0 = io_commit_uops_1_out_prs3_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ppred_busy_0 = io_commit_uops_1_out_ppred_busy; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_stale_pdst_0 = io_commit_uops_1_out_stale_pdst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_exception_0 = io_commit_uops_1_out_exception; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_exc_cause_0 = io_commit_uops_1_out_exc_cause; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_mem_cmd_0 = io_commit_uops_1_out_mem_cmd; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_mem_size_0 = io_commit_uops_1_out_mem_size; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_mem_signed_0 = io_commit_uops_1_out_mem_signed; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_uses_ldq_0 = io_commit_uops_1_out_uses_ldq; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_uses_stq_0 = io_commit_uops_1_out_uses_stq; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_is_unique_0 = io_commit_uops_1_out_is_unique; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_flush_on_commit_0 = io_commit_uops_1_out_flush_on_commit; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_csr_cmd_0 = io_commit_uops_1_out_csr_cmd; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ldst_is_rs1_0 = io_commit_uops_1_out_ldst_is_rs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_ldst_0 = io_commit_uops_1_out_ldst; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_lrs1_0 = io_commit_uops_1_out_lrs1; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_lrs2_0 = io_commit_uops_1_out_lrs2; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_lrs3_0 = io_commit_uops_1_out_lrs3; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_dst_rtype_0 = io_commit_uops_1_out_dst_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_lrs1_rtype_0 = io_commit_uops_1_out_lrs1_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_lrs2_rtype_0 = io_commit_uops_1_out_lrs2_rtype; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_frs3_en_0 = io_commit_uops_1_out_frs3_en; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fcn_dw_0 = io_commit_uops_1_out_fcn_dw; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fcn_op_0 = io_commit_uops_1_out_fcn_op; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_val_0 = io_commit_uops_1_out_fp_val; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_rm_0 = io_commit_uops_1_out_fp_rm; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_fp_typ_0 = io_commit_uops_1_out_fp_typ; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_xcpt_pf_if_0 = io_commit_uops_1_out_xcpt_pf_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_xcpt_ae_if_0 = io_commit_uops_1_out_xcpt_ae_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_xcpt_ma_if_0 = io_commit_uops_1_out_xcpt_ma_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_bp_debug_if_0 = io_commit_uops_1_out_bp_debug_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_bp_xcpt_if_0 = io_commit_uops_1_out_bp_xcpt_if; // @[rob.scala:199:7, :313:23]
assign io_commit_uops_1_debug_tsrc_0 = io_commit_uops_1_out_debug_tsrc; // @[rob.scala:199:7, :313:23]
wire io_commit_uops_1_out_taken; // @[rob.scala:313:23]
wire [2:0] io_commit_uops_1_out_debug_fsrc; // @[rob.scala:313:23]
wire [31:0][31:0] _GEN_135 = {{rob_uop_1_31_inst}, {rob_uop_1_30_inst}, {rob_uop_1_29_inst}, {rob_uop_1_28_inst}, {rob_uop_1_27_inst}, {rob_uop_1_26_inst}, {rob_uop_1_25_inst}, {rob_uop_1_24_inst}, {rob_uop_1_23_inst}, {rob_uop_1_22_inst}, {rob_uop_1_21_inst}, {rob_uop_1_20_inst}, {rob_uop_1_19_inst}, {rob_uop_1_18_inst}, {rob_uop_1_17_inst}, {rob_uop_1_16_inst}, {rob_uop_1_15_inst}, {rob_uop_1_14_inst}, {rob_uop_1_13_inst}, {rob_uop_1_12_inst}, {rob_uop_1_11_inst}, {rob_uop_1_10_inst}, {rob_uop_1_9_inst}, {rob_uop_1_8_inst}, {rob_uop_1_7_inst}, {rob_uop_1_6_inst}, {rob_uop_1_5_inst}, {rob_uop_1_4_inst}, {rob_uop_1_3_inst}, {rob_uop_1_2_inst}, {rob_uop_1_1_inst}, {rob_uop_1_0_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_inst = _GEN_135[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][31:0] _GEN_136 = {{rob_uop_1_31_debug_inst}, {rob_uop_1_30_debug_inst}, {rob_uop_1_29_debug_inst}, {rob_uop_1_28_debug_inst}, {rob_uop_1_27_debug_inst}, {rob_uop_1_26_debug_inst}, {rob_uop_1_25_debug_inst}, {rob_uop_1_24_debug_inst}, {rob_uop_1_23_debug_inst}, {rob_uop_1_22_debug_inst}, {rob_uop_1_21_debug_inst}, {rob_uop_1_20_debug_inst}, {rob_uop_1_19_debug_inst}, {rob_uop_1_18_debug_inst}, {rob_uop_1_17_debug_inst}, {rob_uop_1_16_debug_inst}, {rob_uop_1_15_debug_inst}, {rob_uop_1_14_debug_inst}, {rob_uop_1_13_debug_inst}, {rob_uop_1_12_debug_inst}, {rob_uop_1_11_debug_inst}, {rob_uop_1_10_debug_inst}, {rob_uop_1_9_debug_inst}, {rob_uop_1_8_debug_inst}, {rob_uop_1_7_debug_inst}, {rob_uop_1_6_debug_inst}, {rob_uop_1_5_debug_inst}, {rob_uop_1_4_debug_inst}, {rob_uop_1_3_debug_inst}, {rob_uop_1_2_debug_inst}, {rob_uop_1_1_debug_inst}, {rob_uop_1_0_debug_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_debug_inst = _GEN_136[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_137 = {{rob_uop_1_31_is_rvc}, {rob_uop_1_30_is_rvc}, {rob_uop_1_29_is_rvc}, {rob_uop_1_28_is_rvc}, {rob_uop_1_27_is_rvc}, {rob_uop_1_26_is_rvc}, {rob_uop_1_25_is_rvc}, {rob_uop_1_24_is_rvc}, {rob_uop_1_23_is_rvc}, {rob_uop_1_22_is_rvc}, {rob_uop_1_21_is_rvc}, {rob_uop_1_20_is_rvc}, {rob_uop_1_19_is_rvc}, {rob_uop_1_18_is_rvc}, {rob_uop_1_17_is_rvc}, {rob_uop_1_16_is_rvc}, {rob_uop_1_15_is_rvc}, {rob_uop_1_14_is_rvc}, {rob_uop_1_13_is_rvc}, {rob_uop_1_12_is_rvc}, {rob_uop_1_11_is_rvc}, {rob_uop_1_10_is_rvc}, {rob_uop_1_9_is_rvc}, {rob_uop_1_8_is_rvc}, {rob_uop_1_7_is_rvc}, {rob_uop_1_6_is_rvc}, {rob_uop_1_5_is_rvc}, {rob_uop_1_4_is_rvc}, {rob_uop_1_3_is_rvc}, {rob_uop_1_2_is_rvc}, {rob_uop_1_1_is_rvc}, {rob_uop_1_0_is_rvc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_rvc = _GEN_137[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][39:0] _GEN_138 = {{rob_uop_1_31_debug_pc}, {rob_uop_1_30_debug_pc}, {rob_uop_1_29_debug_pc}, {rob_uop_1_28_debug_pc}, {rob_uop_1_27_debug_pc}, {rob_uop_1_26_debug_pc}, {rob_uop_1_25_debug_pc}, {rob_uop_1_24_debug_pc}, {rob_uop_1_23_debug_pc}, {rob_uop_1_22_debug_pc}, {rob_uop_1_21_debug_pc}, {rob_uop_1_20_debug_pc}, {rob_uop_1_19_debug_pc}, {rob_uop_1_18_debug_pc}, {rob_uop_1_17_debug_pc}, {rob_uop_1_16_debug_pc}, {rob_uop_1_15_debug_pc}, {rob_uop_1_14_debug_pc}, {rob_uop_1_13_debug_pc}, {rob_uop_1_12_debug_pc}, {rob_uop_1_11_debug_pc}, {rob_uop_1_10_debug_pc}, {rob_uop_1_9_debug_pc}, {rob_uop_1_8_debug_pc}, {rob_uop_1_7_debug_pc}, {rob_uop_1_6_debug_pc}, {rob_uop_1_5_debug_pc}, {rob_uop_1_4_debug_pc}, {rob_uop_1_3_debug_pc}, {rob_uop_1_2_debug_pc}, {rob_uop_1_1_debug_pc}, {rob_uop_1_0_debug_pc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_debug_pc = _GEN_138[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_139 = {{rob_uop_1_31_iq_type_0}, {rob_uop_1_30_iq_type_0}, {rob_uop_1_29_iq_type_0}, {rob_uop_1_28_iq_type_0}, {rob_uop_1_27_iq_type_0}, {rob_uop_1_26_iq_type_0}, {rob_uop_1_25_iq_type_0}, {rob_uop_1_24_iq_type_0}, {rob_uop_1_23_iq_type_0}, {rob_uop_1_22_iq_type_0}, {rob_uop_1_21_iq_type_0}, {rob_uop_1_20_iq_type_0}, {rob_uop_1_19_iq_type_0}, {rob_uop_1_18_iq_type_0}, {rob_uop_1_17_iq_type_0}, {rob_uop_1_16_iq_type_0}, {rob_uop_1_15_iq_type_0}, {rob_uop_1_14_iq_type_0}, {rob_uop_1_13_iq_type_0}, {rob_uop_1_12_iq_type_0}, {rob_uop_1_11_iq_type_0}, {rob_uop_1_10_iq_type_0}, {rob_uop_1_9_iq_type_0}, {rob_uop_1_8_iq_type_0}, {rob_uop_1_7_iq_type_0}, {rob_uop_1_6_iq_type_0}, {rob_uop_1_5_iq_type_0}, {rob_uop_1_4_iq_type_0}, {rob_uop_1_3_iq_type_0}, {rob_uop_1_2_iq_type_0}, {rob_uop_1_1_iq_type_0}, {rob_uop_1_0_iq_type_0}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iq_type_0 = _GEN_139[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_140 = {{rob_uop_1_31_iq_type_1}, {rob_uop_1_30_iq_type_1}, {rob_uop_1_29_iq_type_1}, {rob_uop_1_28_iq_type_1}, {rob_uop_1_27_iq_type_1}, {rob_uop_1_26_iq_type_1}, {rob_uop_1_25_iq_type_1}, {rob_uop_1_24_iq_type_1}, {rob_uop_1_23_iq_type_1}, {rob_uop_1_22_iq_type_1}, {rob_uop_1_21_iq_type_1}, {rob_uop_1_20_iq_type_1}, {rob_uop_1_19_iq_type_1}, {rob_uop_1_18_iq_type_1}, {rob_uop_1_17_iq_type_1}, {rob_uop_1_16_iq_type_1}, {rob_uop_1_15_iq_type_1}, {rob_uop_1_14_iq_type_1}, {rob_uop_1_13_iq_type_1}, {rob_uop_1_12_iq_type_1}, {rob_uop_1_11_iq_type_1}, {rob_uop_1_10_iq_type_1}, {rob_uop_1_9_iq_type_1}, {rob_uop_1_8_iq_type_1}, {rob_uop_1_7_iq_type_1}, {rob_uop_1_6_iq_type_1}, {rob_uop_1_5_iq_type_1}, {rob_uop_1_4_iq_type_1}, {rob_uop_1_3_iq_type_1}, {rob_uop_1_2_iq_type_1}, {rob_uop_1_1_iq_type_1}, {rob_uop_1_0_iq_type_1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iq_type_1 = _GEN_140[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_141 = {{rob_uop_1_31_iq_type_2}, {rob_uop_1_30_iq_type_2}, {rob_uop_1_29_iq_type_2}, {rob_uop_1_28_iq_type_2}, {rob_uop_1_27_iq_type_2}, {rob_uop_1_26_iq_type_2}, {rob_uop_1_25_iq_type_2}, {rob_uop_1_24_iq_type_2}, {rob_uop_1_23_iq_type_2}, {rob_uop_1_22_iq_type_2}, {rob_uop_1_21_iq_type_2}, {rob_uop_1_20_iq_type_2}, {rob_uop_1_19_iq_type_2}, {rob_uop_1_18_iq_type_2}, {rob_uop_1_17_iq_type_2}, {rob_uop_1_16_iq_type_2}, {rob_uop_1_15_iq_type_2}, {rob_uop_1_14_iq_type_2}, {rob_uop_1_13_iq_type_2}, {rob_uop_1_12_iq_type_2}, {rob_uop_1_11_iq_type_2}, {rob_uop_1_10_iq_type_2}, {rob_uop_1_9_iq_type_2}, {rob_uop_1_8_iq_type_2}, {rob_uop_1_7_iq_type_2}, {rob_uop_1_6_iq_type_2}, {rob_uop_1_5_iq_type_2}, {rob_uop_1_4_iq_type_2}, {rob_uop_1_3_iq_type_2}, {rob_uop_1_2_iq_type_2}, {rob_uop_1_1_iq_type_2}, {rob_uop_1_0_iq_type_2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iq_type_2 = _GEN_141[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_142 = {{rob_uop_1_31_iq_type_3}, {rob_uop_1_30_iq_type_3}, {rob_uop_1_29_iq_type_3}, {rob_uop_1_28_iq_type_3}, {rob_uop_1_27_iq_type_3}, {rob_uop_1_26_iq_type_3}, {rob_uop_1_25_iq_type_3}, {rob_uop_1_24_iq_type_3}, {rob_uop_1_23_iq_type_3}, {rob_uop_1_22_iq_type_3}, {rob_uop_1_21_iq_type_3}, {rob_uop_1_20_iq_type_3}, {rob_uop_1_19_iq_type_3}, {rob_uop_1_18_iq_type_3}, {rob_uop_1_17_iq_type_3}, {rob_uop_1_16_iq_type_3}, {rob_uop_1_15_iq_type_3}, {rob_uop_1_14_iq_type_3}, {rob_uop_1_13_iq_type_3}, {rob_uop_1_12_iq_type_3}, {rob_uop_1_11_iq_type_3}, {rob_uop_1_10_iq_type_3}, {rob_uop_1_9_iq_type_3}, {rob_uop_1_8_iq_type_3}, {rob_uop_1_7_iq_type_3}, {rob_uop_1_6_iq_type_3}, {rob_uop_1_5_iq_type_3}, {rob_uop_1_4_iq_type_3}, {rob_uop_1_3_iq_type_3}, {rob_uop_1_2_iq_type_3}, {rob_uop_1_1_iq_type_3}, {rob_uop_1_0_iq_type_3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iq_type_3 = _GEN_142[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_143 = {{rob_uop_1_31_fu_code_0}, {rob_uop_1_30_fu_code_0}, {rob_uop_1_29_fu_code_0}, {rob_uop_1_28_fu_code_0}, {rob_uop_1_27_fu_code_0}, {rob_uop_1_26_fu_code_0}, {rob_uop_1_25_fu_code_0}, {rob_uop_1_24_fu_code_0}, {rob_uop_1_23_fu_code_0}, {rob_uop_1_22_fu_code_0}, {rob_uop_1_21_fu_code_0}, {rob_uop_1_20_fu_code_0}, {rob_uop_1_19_fu_code_0}, {rob_uop_1_18_fu_code_0}, {rob_uop_1_17_fu_code_0}, {rob_uop_1_16_fu_code_0}, {rob_uop_1_15_fu_code_0}, {rob_uop_1_14_fu_code_0}, {rob_uop_1_13_fu_code_0}, {rob_uop_1_12_fu_code_0}, {rob_uop_1_11_fu_code_0}, {rob_uop_1_10_fu_code_0}, {rob_uop_1_9_fu_code_0}, {rob_uop_1_8_fu_code_0}, {rob_uop_1_7_fu_code_0}, {rob_uop_1_6_fu_code_0}, {rob_uop_1_5_fu_code_0}, {rob_uop_1_4_fu_code_0}, {rob_uop_1_3_fu_code_0}, {rob_uop_1_2_fu_code_0}, {rob_uop_1_1_fu_code_0}, {rob_uop_1_0_fu_code_0}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_0 = _GEN_143[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_144 = {{rob_uop_1_31_fu_code_1}, {rob_uop_1_30_fu_code_1}, {rob_uop_1_29_fu_code_1}, {rob_uop_1_28_fu_code_1}, {rob_uop_1_27_fu_code_1}, {rob_uop_1_26_fu_code_1}, {rob_uop_1_25_fu_code_1}, {rob_uop_1_24_fu_code_1}, {rob_uop_1_23_fu_code_1}, {rob_uop_1_22_fu_code_1}, {rob_uop_1_21_fu_code_1}, {rob_uop_1_20_fu_code_1}, {rob_uop_1_19_fu_code_1}, {rob_uop_1_18_fu_code_1}, {rob_uop_1_17_fu_code_1}, {rob_uop_1_16_fu_code_1}, {rob_uop_1_15_fu_code_1}, {rob_uop_1_14_fu_code_1}, {rob_uop_1_13_fu_code_1}, {rob_uop_1_12_fu_code_1}, {rob_uop_1_11_fu_code_1}, {rob_uop_1_10_fu_code_1}, {rob_uop_1_9_fu_code_1}, {rob_uop_1_8_fu_code_1}, {rob_uop_1_7_fu_code_1}, {rob_uop_1_6_fu_code_1}, {rob_uop_1_5_fu_code_1}, {rob_uop_1_4_fu_code_1}, {rob_uop_1_3_fu_code_1}, {rob_uop_1_2_fu_code_1}, {rob_uop_1_1_fu_code_1}, {rob_uop_1_0_fu_code_1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_1 = _GEN_144[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_145 = {{rob_uop_1_31_fu_code_2}, {rob_uop_1_30_fu_code_2}, {rob_uop_1_29_fu_code_2}, {rob_uop_1_28_fu_code_2}, {rob_uop_1_27_fu_code_2}, {rob_uop_1_26_fu_code_2}, {rob_uop_1_25_fu_code_2}, {rob_uop_1_24_fu_code_2}, {rob_uop_1_23_fu_code_2}, {rob_uop_1_22_fu_code_2}, {rob_uop_1_21_fu_code_2}, {rob_uop_1_20_fu_code_2}, {rob_uop_1_19_fu_code_2}, {rob_uop_1_18_fu_code_2}, {rob_uop_1_17_fu_code_2}, {rob_uop_1_16_fu_code_2}, {rob_uop_1_15_fu_code_2}, {rob_uop_1_14_fu_code_2}, {rob_uop_1_13_fu_code_2}, {rob_uop_1_12_fu_code_2}, {rob_uop_1_11_fu_code_2}, {rob_uop_1_10_fu_code_2}, {rob_uop_1_9_fu_code_2}, {rob_uop_1_8_fu_code_2}, {rob_uop_1_7_fu_code_2}, {rob_uop_1_6_fu_code_2}, {rob_uop_1_5_fu_code_2}, {rob_uop_1_4_fu_code_2}, {rob_uop_1_3_fu_code_2}, {rob_uop_1_2_fu_code_2}, {rob_uop_1_1_fu_code_2}, {rob_uop_1_0_fu_code_2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_2 = _GEN_145[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_146 = {{rob_uop_1_31_fu_code_3}, {rob_uop_1_30_fu_code_3}, {rob_uop_1_29_fu_code_3}, {rob_uop_1_28_fu_code_3}, {rob_uop_1_27_fu_code_3}, {rob_uop_1_26_fu_code_3}, {rob_uop_1_25_fu_code_3}, {rob_uop_1_24_fu_code_3}, {rob_uop_1_23_fu_code_3}, {rob_uop_1_22_fu_code_3}, {rob_uop_1_21_fu_code_3}, {rob_uop_1_20_fu_code_3}, {rob_uop_1_19_fu_code_3}, {rob_uop_1_18_fu_code_3}, {rob_uop_1_17_fu_code_3}, {rob_uop_1_16_fu_code_3}, {rob_uop_1_15_fu_code_3}, {rob_uop_1_14_fu_code_3}, {rob_uop_1_13_fu_code_3}, {rob_uop_1_12_fu_code_3}, {rob_uop_1_11_fu_code_3}, {rob_uop_1_10_fu_code_3}, {rob_uop_1_9_fu_code_3}, {rob_uop_1_8_fu_code_3}, {rob_uop_1_7_fu_code_3}, {rob_uop_1_6_fu_code_3}, {rob_uop_1_5_fu_code_3}, {rob_uop_1_4_fu_code_3}, {rob_uop_1_3_fu_code_3}, {rob_uop_1_2_fu_code_3}, {rob_uop_1_1_fu_code_3}, {rob_uop_1_0_fu_code_3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_3 = _GEN_146[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_147 = {{rob_uop_1_31_fu_code_4}, {rob_uop_1_30_fu_code_4}, {rob_uop_1_29_fu_code_4}, {rob_uop_1_28_fu_code_4}, {rob_uop_1_27_fu_code_4}, {rob_uop_1_26_fu_code_4}, {rob_uop_1_25_fu_code_4}, {rob_uop_1_24_fu_code_4}, {rob_uop_1_23_fu_code_4}, {rob_uop_1_22_fu_code_4}, {rob_uop_1_21_fu_code_4}, {rob_uop_1_20_fu_code_4}, {rob_uop_1_19_fu_code_4}, {rob_uop_1_18_fu_code_4}, {rob_uop_1_17_fu_code_4}, {rob_uop_1_16_fu_code_4}, {rob_uop_1_15_fu_code_4}, {rob_uop_1_14_fu_code_4}, {rob_uop_1_13_fu_code_4}, {rob_uop_1_12_fu_code_4}, {rob_uop_1_11_fu_code_4}, {rob_uop_1_10_fu_code_4}, {rob_uop_1_9_fu_code_4}, {rob_uop_1_8_fu_code_4}, {rob_uop_1_7_fu_code_4}, {rob_uop_1_6_fu_code_4}, {rob_uop_1_5_fu_code_4}, {rob_uop_1_4_fu_code_4}, {rob_uop_1_3_fu_code_4}, {rob_uop_1_2_fu_code_4}, {rob_uop_1_1_fu_code_4}, {rob_uop_1_0_fu_code_4}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_4 = _GEN_147[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_148 = {{rob_uop_1_31_fu_code_5}, {rob_uop_1_30_fu_code_5}, {rob_uop_1_29_fu_code_5}, {rob_uop_1_28_fu_code_5}, {rob_uop_1_27_fu_code_5}, {rob_uop_1_26_fu_code_5}, {rob_uop_1_25_fu_code_5}, {rob_uop_1_24_fu_code_5}, {rob_uop_1_23_fu_code_5}, {rob_uop_1_22_fu_code_5}, {rob_uop_1_21_fu_code_5}, {rob_uop_1_20_fu_code_5}, {rob_uop_1_19_fu_code_5}, {rob_uop_1_18_fu_code_5}, {rob_uop_1_17_fu_code_5}, {rob_uop_1_16_fu_code_5}, {rob_uop_1_15_fu_code_5}, {rob_uop_1_14_fu_code_5}, {rob_uop_1_13_fu_code_5}, {rob_uop_1_12_fu_code_5}, {rob_uop_1_11_fu_code_5}, {rob_uop_1_10_fu_code_5}, {rob_uop_1_9_fu_code_5}, {rob_uop_1_8_fu_code_5}, {rob_uop_1_7_fu_code_5}, {rob_uop_1_6_fu_code_5}, {rob_uop_1_5_fu_code_5}, {rob_uop_1_4_fu_code_5}, {rob_uop_1_3_fu_code_5}, {rob_uop_1_2_fu_code_5}, {rob_uop_1_1_fu_code_5}, {rob_uop_1_0_fu_code_5}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_5 = _GEN_148[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_149 = {{rob_uop_1_31_fu_code_6}, {rob_uop_1_30_fu_code_6}, {rob_uop_1_29_fu_code_6}, {rob_uop_1_28_fu_code_6}, {rob_uop_1_27_fu_code_6}, {rob_uop_1_26_fu_code_6}, {rob_uop_1_25_fu_code_6}, {rob_uop_1_24_fu_code_6}, {rob_uop_1_23_fu_code_6}, {rob_uop_1_22_fu_code_6}, {rob_uop_1_21_fu_code_6}, {rob_uop_1_20_fu_code_6}, {rob_uop_1_19_fu_code_6}, {rob_uop_1_18_fu_code_6}, {rob_uop_1_17_fu_code_6}, {rob_uop_1_16_fu_code_6}, {rob_uop_1_15_fu_code_6}, {rob_uop_1_14_fu_code_6}, {rob_uop_1_13_fu_code_6}, {rob_uop_1_12_fu_code_6}, {rob_uop_1_11_fu_code_6}, {rob_uop_1_10_fu_code_6}, {rob_uop_1_9_fu_code_6}, {rob_uop_1_8_fu_code_6}, {rob_uop_1_7_fu_code_6}, {rob_uop_1_6_fu_code_6}, {rob_uop_1_5_fu_code_6}, {rob_uop_1_4_fu_code_6}, {rob_uop_1_3_fu_code_6}, {rob_uop_1_2_fu_code_6}, {rob_uop_1_1_fu_code_6}, {rob_uop_1_0_fu_code_6}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_6 = _GEN_149[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_150 = {{rob_uop_1_31_fu_code_7}, {rob_uop_1_30_fu_code_7}, {rob_uop_1_29_fu_code_7}, {rob_uop_1_28_fu_code_7}, {rob_uop_1_27_fu_code_7}, {rob_uop_1_26_fu_code_7}, {rob_uop_1_25_fu_code_7}, {rob_uop_1_24_fu_code_7}, {rob_uop_1_23_fu_code_7}, {rob_uop_1_22_fu_code_7}, {rob_uop_1_21_fu_code_7}, {rob_uop_1_20_fu_code_7}, {rob_uop_1_19_fu_code_7}, {rob_uop_1_18_fu_code_7}, {rob_uop_1_17_fu_code_7}, {rob_uop_1_16_fu_code_7}, {rob_uop_1_15_fu_code_7}, {rob_uop_1_14_fu_code_7}, {rob_uop_1_13_fu_code_7}, {rob_uop_1_12_fu_code_7}, {rob_uop_1_11_fu_code_7}, {rob_uop_1_10_fu_code_7}, {rob_uop_1_9_fu_code_7}, {rob_uop_1_8_fu_code_7}, {rob_uop_1_7_fu_code_7}, {rob_uop_1_6_fu_code_7}, {rob_uop_1_5_fu_code_7}, {rob_uop_1_4_fu_code_7}, {rob_uop_1_3_fu_code_7}, {rob_uop_1_2_fu_code_7}, {rob_uop_1_1_fu_code_7}, {rob_uop_1_0_fu_code_7}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_7 = _GEN_150[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_151 = {{rob_uop_1_31_fu_code_8}, {rob_uop_1_30_fu_code_8}, {rob_uop_1_29_fu_code_8}, {rob_uop_1_28_fu_code_8}, {rob_uop_1_27_fu_code_8}, {rob_uop_1_26_fu_code_8}, {rob_uop_1_25_fu_code_8}, {rob_uop_1_24_fu_code_8}, {rob_uop_1_23_fu_code_8}, {rob_uop_1_22_fu_code_8}, {rob_uop_1_21_fu_code_8}, {rob_uop_1_20_fu_code_8}, {rob_uop_1_19_fu_code_8}, {rob_uop_1_18_fu_code_8}, {rob_uop_1_17_fu_code_8}, {rob_uop_1_16_fu_code_8}, {rob_uop_1_15_fu_code_8}, {rob_uop_1_14_fu_code_8}, {rob_uop_1_13_fu_code_8}, {rob_uop_1_12_fu_code_8}, {rob_uop_1_11_fu_code_8}, {rob_uop_1_10_fu_code_8}, {rob_uop_1_9_fu_code_8}, {rob_uop_1_8_fu_code_8}, {rob_uop_1_7_fu_code_8}, {rob_uop_1_6_fu_code_8}, {rob_uop_1_5_fu_code_8}, {rob_uop_1_4_fu_code_8}, {rob_uop_1_3_fu_code_8}, {rob_uop_1_2_fu_code_8}, {rob_uop_1_1_fu_code_8}, {rob_uop_1_0_fu_code_8}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_8 = _GEN_151[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_152 = {{rob_uop_1_31_fu_code_9}, {rob_uop_1_30_fu_code_9}, {rob_uop_1_29_fu_code_9}, {rob_uop_1_28_fu_code_9}, {rob_uop_1_27_fu_code_9}, {rob_uop_1_26_fu_code_9}, {rob_uop_1_25_fu_code_9}, {rob_uop_1_24_fu_code_9}, {rob_uop_1_23_fu_code_9}, {rob_uop_1_22_fu_code_9}, {rob_uop_1_21_fu_code_9}, {rob_uop_1_20_fu_code_9}, {rob_uop_1_19_fu_code_9}, {rob_uop_1_18_fu_code_9}, {rob_uop_1_17_fu_code_9}, {rob_uop_1_16_fu_code_9}, {rob_uop_1_15_fu_code_9}, {rob_uop_1_14_fu_code_9}, {rob_uop_1_13_fu_code_9}, {rob_uop_1_12_fu_code_9}, {rob_uop_1_11_fu_code_9}, {rob_uop_1_10_fu_code_9}, {rob_uop_1_9_fu_code_9}, {rob_uop_1_8_fu_code_9}, {rob_uop_1_7_fu_code_9}, {rob_uop_1_6_fu_code_9}, {rob_uop_1_5_fu_code_9}, {rob_uop_1_4_fu_code_9}, {rob_uop_1_3_fu_code_9}, {rob_uop_1_2_fu_code_9}, {rob_uop_1_1_fu_code_9}, {rob_uop_1_0_fu_code_9}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fu_code_9 = _GEN_152[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_153 = {{rob_uop_1_31_iw_issued}, {rob_uop_1_30_iw_issued}, {rob_uop_1_29_iw_issued}, {rob_uop_1_28_iw_issued}, {rob_uop_1_27_iw_issued}, {rob_uop_1_26_iw_issued}, {rob_uop_1_25_iw_issued}, {rob_uop_1_24_iw_issued}, {rob_uop_1_23_iw_issued}, {rob_uop_1_22_iw_issued}, {rob_uop_1_21_iw_issued}, {rob_uop_1_20_iw_issued}, {rob_uop_1_19_iw_issued}, {rob_uop_1_18_iw_issued}, {rob_uop_1_17_iw_issued}, {rob_uop_1_16_iw_issued}, {rob_uop_1_15_iw_issued}, {rob_uop_1_14_iw_issued}, {rob_uop_1_13_iw_issued}, {rob_uop_1_12_iw_issued}, {rob_uop_1_11_iw_issued}, {rob_uop_1_10_iw_issued}, {rob_uop_1_9_iw_issued}, {rob_uop_1_8_iw_issued}, {rob_uop_1_7_iw_issued}, {rob_uop_1_6_iw_issued}, {rob_uop_1_5_iw_issued}, {rob_uop_1_4_iw_issued}, {rob_uop_1_3_iw_issued}, {rob_uop_1_2_iw_issued}, {rob_uop_1_1_iw_issued}, {rob_uop_1_0_iw_issued}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_issued = _GEN_153[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_154 = {{rob_uop_1_31_iw_issued_partial_agen}, {rob_uop_1_30_iw_issued_partial_agen}, {rob_uop_1_29_iw_issued_partial_agen}, {rob_uop_1_28_iw_issued_partial_agen}, {rob_uop_1_27_iw_issued_partial_agen}, {rob_uop_1_26_iw_issued_partial_agen}, {rob_uop_1_25_iw_issued_partial_agen}, {rob_uop_1_24_iw_issued_partial_agen}, {rob_uop_1_23_iw_issued_partial_agen}, {rob_uop_1_22_iw_issued_partial_agen}, {rob_uop_1_21_iw_issued_partial_agen}, {rob_uop_1_20_iw_issued_partial_agen}, {rob_uop_1_19_iw_issued_partial_agen}, {rob_uop_1_18_iw_issued_partial_agen}, {rob_uop_1_17_iw_issued_partial_agen}, {rob_uop_1_16_iw_issued_partial_agen}, {rob_uop_1_15_iw_issued_partial_agen}, {rob_uop_1_14_iw_issued_partial_agen}, {rob_uop_1_13_iw_issued_partial_agen}, {rob_uop_1_12_iw_issued_partial_agen}, {rob_uop_1_11_iw_issued_partial_agen}, {rob_uop_1_10_iw_issued_partial_agen}, {rob_uop_1_9_iw_issued_partial_agen}, {rob_uop_1_8_iw_issued_partial_agen}, {rob_uop_1_7_iw_issued_partial_agen}, {rob_uop_1_6_iw_issued_partial_agen}, {rob_uop_1_5_iw_issued_partial_agen}, {rob_uop_1_4_iw_issued_partial_agen}, {rob_uop_1_3_iw_issued_partial_agen}, {rob_uop_1_2_iw_issued_partial_agen}, {rob_uop_1_1_iw_issued_partial_agen}, {rob_uop_1_0_iw_issued_partial_agen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_issued_partial_agen = _GEN_154[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_155 = {{rob_uop_1_31_iw_issued_partial_dgen}, {rob_uop_1_30_iw_issued_partial_dgen}, {rob_uop_1_29_iw_issued_partial_dgen}, {rob_uop_1_28_iw_issued_partial_dgen}, {rob_uop_1_27_iw_issued_partial_dgen}, {rob_uop_1_26_iw_issued_partial_dgen}, {rob_uop_1_25_iw_issued_partial_dgen}, {rob_uop_1_24_iw_issued_partial_dgen}, {rob_uop_1_23_iw_issued_partial_dgen}, {rob_uop_1_22_iw_issued_partial_dgen}, {rob_uop_1_21_iw_issued_partial_dgen}, {rob_uop_1_20_iw_issued_partial_dgen}, {rob_uop_1_19_iw_issued_partial_dgen}, {rob_uop_1_18_iw_issued_partial_dgen}, {rob_uop_1_17_iw_issued_partial_dgen}, {rob_uop_1_16_iw_issued_partial_dgen}, {rob_uop_1_15_iw_issued_partial_dgen}, {rob_uop_1_14_iw_issued_partial_dgen}, {rob_uop_1_13_iw_issued_partial_dgen}, {rob_uop_1_12_iw_issued_partial_dgen}, {rob_uop_1_11_iw_issued_partial_dgen}, {rob_uop_1_10_iw_issued_partial_dgen}, {rob_uop_1_9_iw_issued_partial_dgen}, {rob_uop_1_8_iw_issued_partial_dgen}, {rob_uop_1_7_iw_issued_partial_dgen}, {rob_uop_1_6_iw_issued_partial_dgen}, {rob_uop_1_5_iw_issued_partial_dgen}, {rob_uop_1_4_iw_issued_partial_dgen}, {rob_uop_1_3_iw_issued_partial_dgen}, {rob_uop_1_2_iw_issued_partial_dgen}, {rob_uop_1_1_iw_issued_partial_dgen}, {rob_uop_1_0_iw_issued_partial_dgen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_issued_partial_dgen = _GEN_155[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_156 = {{rob_uop_1_31_iw_p1_speculative_child}, {rob_uop_1_30_iw_p1_speculative_child}, {rob_uop_1_29_iw_p1_speculative_child}, {rob_uop_1_28_iw_p1_speculative_child}, {rob_uop_1_27_iw_p1_speculative_child}, {rob_uop_1_26_iw_p1_speculative_child}, {rob_uop_1_25_iw_p1_speculative_child}, {rob_uop_1_24_iw_p1_speculative_child}, {rob_uop_1_23_iw_p1_speculative_child}, {rob_uop_1_22_iw_p1_speculative_child}, {rob_uop_1_21_iw_p1_speculative_child}, {rob_uop_1_20_iw_p1_speculative_child}, {rob_uop_1_19_iw_p1_speculative_child}, {rob_uop_1_18_iw_p1_speculative_child}, {rob_uop_1_17_iw_p1_speculative_child}, {rob_uop_1_16_iw_p1_speculative_child}, {rob_uop_1_15_iw_p1_speculative_child}, {rob_uop_1_14_iw_p1_speculative_child}, {rob_uop_1_13_iw_p1_speculative_child}, {rob_uop_1_12_iw_p1_speculative_child}, {rob_uop_1_11_iw_p1_speculative_child}, {rob_uop_1_10_iw_p1_speculative_child}, {rob_uop_1_9_iw_p1_speculative_child}, {rob_uop_1_8_iw_p1_speculative_child}, {rob_uop_1_7_iw_p1_speculative_child}, {rob_uop_1_6_iw_p1_speculative_child}, {rob_uop_1_5_iw_p1_speculative_child}, {rob_uop_1_4_iw_p1_speculative_child}, {rob_uop_1_3_iw_p1_speculative_child}, {rob_uop_1_2_iw_p1_speculative_child}, {rob_uop_1_1_iw_p1_speculative_child}, {rob_uop_1_0_iw_p1_speculative_child}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_p1_speculative_child = _GEN_156[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_157 = {{rob_uop_1_31_iw_p2_speculative_child}, {rob_uop_1_30_iw_p2_speculative_child}, {rob_uop_1_29_iw_p2_speculative_child}, {rob_uop_1_28_iw_p2_speculative_child}, {rob_uop_1_27_iw_p2_speculative_child}, {rob_uop_1_26_iw_p2_speculative_child}, {rob_uop_1_25_iw_p2_speculative_child}, {rob_uop_1_24_iw_p2_speculative_child}, {rob_uop_1_23_iw_p2_speculative_child}, {rob_uop_1_22_iw_p2_speculative_child}, {rob_uop_1_21_iw_p2_speculative_child}, {rob_uop_1_20_iw_p2_speculative_child}, {rob_uop_1_19_iw_p2_speculative_child}, {rob_uop_1_18_iw_p2_speculative_child}, {rob_uop_1_17_iw_p2_speculative_child}, {rob_uop_1_16_iw_p2_speculative_child}, {rob_uop_1_15_iw_p2_speculative_child}, {rob_uop_1_14_iw_p2_speculative_child}, {rob_uop_1_13_iw_p2_speculative_child}, {rob_uop_1_12_iw_p2_speculative_child}, {rob_uop_1_11_iw_p2_speculative_child}, {rob_uop_1_10_iw_p2_speculative_child}, {rob_uop_1_9_iw_p2_speculative_child}, {rob_uop_1_8_iw_p2_speculative_child}, {rob_uop_1_7_iw_p2_speculative_child}, {rob_uop_1_6_iw_p2_speculative_child}, {rob_uop_1_5_iw_p2_speculative_child}, {rob_uop_1_4_iw_p2_speculative_child}, {rob_uop_1_3_iw_p2_speculative_child}, {rob_uop_1_2_iw_p2_speculative_child}, {rob_uop_1_1_iw_p2_speculative_child}, {rob_uop_1_0_iw_p2_speculative_child}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_p2_speculative_child = _GEN_157[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_158 = {{rob_uop_1_31_iw_p1_bypass_hint}, {rob_uop_1_30_iw_p1_bypass_hint}, {rob_uop_1_29_iw_p1_bypass_hint}, {rob_uop_1_28_iw_p1_bypass_hint}, {rob_uop_1_27_iw_p1_bypass_hint}, {rob_uop_1_26_iw_p1_bypass_hint}, {rob_uop_1_25_iw_p1_bypass_hint}, {rob_uop_1_24_iw_p1_bypass_hint}, {rob_uop_1_23_iw_p1_bypass_hint}, {rob_uop_1_22_iw_p1_bypass_hint}, {rob_uop_1_21_iw_p1_bypass_hint}, {rob_uop_1_20_iw_p1_bypass_hint}, {rob_uop_1_19_iw_p1_bypass_hint}, {rob_uop_1_18_iw_p1_bypass_hint}, {rob_uop_1_17_iw_p1_bypass_hint}, {rob_uop_1_16_iw_p1_bypass_hint}, {rob_uop_1_15_iw_p1_bypass_hint}, {rob_uop_1_14_iw_p1_bypass_hint}, {rob_uop_1_13_iw_p1_bypass_hint}, {rob_uop_1_12_iw_p1_bypass_hint}, {rob_uop_1_11_iw_p1_bypass_hint}, {rob_uop_1_10_iw_p1_bypass_hint}, {rob_uop_1_9_iw_p1_bypass_hint}, {rob_uop_1_8_iw_p1_bypass_hint}, {rob_uop_1_7_iw_p1_bypass_hint}, {rob_uop_1_6_iw_p1_bypass_hint}, {rob_uop_1_5_iw_p1_bypass_hint}, {rob_uop_1_4_iw_p1_bypass_hint}, {rob_uop_1_3_iw_p1_bypass_hint}, {rob_uop_1_2_iw_p1_bypass_hint}, {rob_uop_1_1_iw_p1_bypass_hint}, {rob_uop_1_0_iw_p1_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_p1_bypass_hint = _GEN_158[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_159 = {{rob_uop_1_31_iw_p2_bypass_hint}, {rob_uop_1_30_iw_p2_bypass_hint}, {rob_uop_1_29_iw_p2_bypass_hint}, {rob_uop_1_28_iw_p2_bypass_hint}, {rob_uop_1_27_iw_p2_bypass_hint}, {rob_uop_1_26_iw_p2_bypass_hint}, {rob_uop_1_25_iw_p2_bypass_hint}, {rob_uop_1_24_iw_p2_bypass_hint}, {rob_uop_1_23_iw_p2_bypass_hint}, {rob_uop_1_22_iw_p2_bypass_hint}, {rob_uop_1_21_iw_p2_bypass_hint}, {rob_uop_1_20_iw_p2_bypass_hint}, {rob_uop_1_19_iw_p2_bypass_hint}, {rob_uop_1_18_iw_p2_bypass_hint}, {rob_uop_1_17_iw_p2_bypass_hint}, {rob_uop_1_16_iw_p2_bypass_hint}, {rob_uop_1_15_iw_p2_bypass_hint}, {rob_uop_1_14_iw_p2_bypass_hint}, {rob_uop_1_13_iw_p2_bypass_hint}, {rob_uop_1_12_iw_p2_bypass_hint}, {rob_uop_1_11_iw_p2_bypass_hint}, {rob_uop_1_10_iw_p2_bypass_hint}, {rob_uop_1_9_iw_p2_bypass_hint}, {rob_uop_1_8_iw_p2_bypass_hint}, {rob_uop_1_7_iw_p2_bypass_hint}, {rob_uop_1_6_iw_p2_bypass_hint}, {rob_uop_1_5_iw_p2_bypass_hint}, {rob_uop_1_4_iw_p2_bypass_hint}, {rob_uop_1_3_iw_p2_bypass_hint}, {rob_uop_1_2_iw_p2_bypass_hint}, {rob_uop_1_1_iw_p2_bypass_hint}, {rob_uop_1_0_iw_p2_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_p2_bypass_hint = _GEN_159[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_160 = {{rob_uop_1_31_iw_p3_bypass_hint}, {rob_uop_1_30_iw_p3_bypass_hint}, {rob_uop_1_29_iw_p3_bypass_hint}, {rob_uop_1_28_iw_p3_bypass_hint}, {rob_uop_1_27_iw_p3_bypass_hint}, {rob_uop_1_26_iw_p3_bypass_hint}, {rob_uop_1_25_iw_p3_bypass_hint}, {rob_uop_1_24_iw_p3_bypass_hint}, {rob_uop_1_23_iw_p3_bypass_hint}, {rob_uop_1_22_iw_p3_bypass_hint}, {rob_uop_1_21_iw_p3_bypass_hint}, {rob_uop_1_20_iw_p3_bypass_hint}, {rob_uop_1_19_iw_p3_bypass_hint}, {rob_uop_1_18_iw_p3_bypass_hint}, {rob_uop_1_17_iw_p3_bypass_hint}, {rob_uop_1_16_iw_p3_bypass_hint}, {rob_uop_1_15_iw_p3_bypass_hint}, {rob_uop_1_14_iw_p3_bypass_hint}, {rob_uop_1_13_iw_p3_bypass_hint}, {rob_uop_1_12_iw_p3_bypass_hint}, {rob_uop_1_11_iw_p3_bypass_hint}, {rob_uop_1_10_iw_p3_bypass_hint}, {rob_uop_1_9_iw_p3_bypass_hint}, {rob_uop_1_8_iw_p3_bypass_hint}, {rob_uop_1_7_iw_p3_bypass_hint}, {rob_uop_1_6_iw_p3_bypass_hint}, {rob_uop_1_5_iw_p3_bypass_hint}, {rob_uop_1_4_iw_p3_bypass_hint}, {rob_uop_1_3_iw_p3_bypass_hint}, {rob_uop_1_2_iw_p3_bypass_hint}, {rob_uop_1_1_iw_p3_bypass_hint}, {rob_uop_1_0_iw_p3_bypass_hint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_iw_p3_bypass_hint = _GEN_160[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_161 = {{rob_uop_1_31_dis_col_sel}, {rob_uop_1_30_dis_col_sel}, {rob_uop_1_29_dis_col_sel}, {rob_uop_1_28_dis_col_sel}, {rob_uop_1_27_dis_col_sel}, {rob_uop_1_26_dis_col_sel}, {rob_uop_1_25_dis_col_sel}, {rob_uop_1_24_dis_col_sel}, {rob_uop_1_23_dis_col_sel}, {rob_uop_1_22_dis_col_sel}, {rob_uop_1_21_dis_col_sel}, {rob_uop_1_20_dis_col_sel}, {rob_uop_1_19_dis_col_sel}, {rob_uop_1_18_dis_col_sel}, {rob_uop_1_17_dis_col_sel}, {rob_uop_1_16_dis_col_sel}, {rob_uop_1_15_dis_col_sel}, {rob_uop_1_14_dis_col_sel}, {rob_uop_1_13_dis_col_sel}, {rob_uop_1_12_dis_col_sel}, {rob_uop_1_11_dis_col_sel}, {rob_uop_1_10_dis_col_sel}, {rob_uop_1_9_dis_col_sel}, {rob_uop_1_8_dis_col_sel}, {rob_uop_1_7_dis_col_sel}, {rob_uop_1_6_dis_col_sel}, {rob_uop_1_5_dis_col_sel}, {rob_uop_1_4_dis_col_sel}, {rob_uop_1_3_dis_col_sel}, {rob_uop_1_2_dis_col_sel}, {rob_uop_1_1_dis_col_sel}, {rob_uop_1_0_dis_col_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_dis_col_sel = _GEN_161[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][11:0] _GEN_162 = {{rob_uop_1_31_br_mask}, {rob_uop_1_30_br_mask}, {rob_uop_1_29_br_mask}, {rob_uop_1_28_br_mask}, {rob_uop_1_27_br_mask}, {rob_uop_1_26_br_mask}, {rob_uop_1_25_br_mask}, {rob_uop_1_24_br_mask}, {rob_uop_1_23_br_mask}, {rob_uop_1_22_br_mask}, {rob_uop_1_21_br_mask}, {rob_uop_1_20_br_mask}, {rob_uop_1_19_br_mask}, {rob_uop_1_18_br_mask}, {rob_uop_1_17_br_mask}, {rob_uop_1_16_br_mask}, {rob_uop_1_15_br_mask}, {rob_uop_1_14_br_mask}, {rob_uop_1_13_br_mask}, {rob_uop_1_12_br_mask}, {rob_uop_1_11_br_mask}, {rob_uop_1_10_br_mask}, {rob_uop_1_9_br_mask}, {rob_uop_1_8_br_mask}, {rob_uop_1_7_br_mask}, {rob_uop_1_6_br_mask}, {rob_uop_1_5_br_mask}, {rob_uop_1_4_br_mask}, {rob_uop_1_3_br_mask}, {rob_uop_1_2_br_mask}, {rob_uop_1_1_br_mask}, {rob_uop_1_0_br_mask}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_br_mask = _GEN_162[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_163 = {{rob_uop_1_31_br_tag}, {rob_uop_1_30_br_tag}, {rob_uop_1_29_br_tag}, {rob_uop_1_28_br_tag}, {rob_uop_1_27_br_tag}, {rob_uop_1_26_br_tag}, {rob_uop_1_25_br_tag}, {rob_uop_1_24_br_tag}, {rob_uop_1_23_br_tag}, {rob_uop_1_22_br_tag}, {rob_uop_1_21_br_tag}, {rob_uop_1_20_br_tag}, {rob_uop_1_19_br_tag}, {rob_uop_1_18_br_tag}, {rob_uop_1_17_br_tag}, {rob_uop_1_16_br_tag}, {rob_uop_1_15_br_tag}, {rob_uop_1_14_br_tag}, {rob_uop_1_13_br_tag}, {rob_uop_1_12_br_tag}, {rob_uop_1_11_br_tag}, {rob_uop_1_10_br_tag}, {rob_uop_1_9_br_tag}, {rob_uop_1_8_br_tag}, {rob_uop_1_7_br_tag}, {rob_uop_1_6_br_tag}, {rob_uop_1_5_br_tag}, {rob_uop_1_4_br_tag}, {rob_uop_1_3_br_tag}, {rob_uop_1_2_br_tag}, {rob_uop_1_1_br_tag}, {rob_uop_1_0_br_tag}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_br_tag = _GEN_163[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_164 = {{rob_uop_1_31_br_type}, {rob_uop_1_30_br_type}, {rob_uop_1_29_br_type}, {rob_uop_1_28_br_type}, {rob_uop_1_27_br_type}, {rob_uop_1_26_br_type}, {rob_uop_1_25_br_type}, {rob_uop_1_24_br_type}, {rob_uop_1_23_br_type}, {rob_uop_1_22_br_type}, {rob_uop_1_21_br_type}, {rob_uop_1_20_br_type}, {rob_uop_1_19_br_type}, {rob_uop_1_18_br_type}, {rob_uop_1_17_br_type}, {rob_uop_1_16_br_type}, {rob_uop_1_15_br_type}, {rob_uop_1_14_br_type}, {rob_uop_1_13_br_type}, {rob_uop_1_12_br_type}, {rob_uop_1_11_br_type}, {rob_uop_1_10_br_type}, {rob_uop_1_9_br_type}, {rob_uop_1_8_br_type}, {rob_uop_1_7_br_type}, {rob_uop_1_6_br_type}, {rob_uop_1_5_br_type}, {rob_uop_1_4_br_type}, {rob_uop_1_3_br_type}, {rob_uop_1_2_br_type}, {rob_uop_1_1_br_type}, {rob_uop_1_0_br_type}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_br_type = _GEN_164[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_165 = {{rob_uop_1_31_is_sfb}, {rob_uop_1_30_is_sfb}, {rob_uop_1_29_is_sfb}, {rob_uop_1_28_is_sfb}, {rob_uop_1_27_is_sfb}, {rob_uop_1_26_is_sfb}, {rob_uop_1_25_is_sfb}, {rob_uop_1_24_is_sfb}, {rob_uop_1_23_is_sfb}, {rob_uop_1_22_is_sfb}, {rob_uop_1_21_is_sfb}, {rob_uop_1_20_is_sfb}, {rob_uop_1_19_is_sfb}, {rob_uop_1_18_is_sfb}, {rob_uop_1_17_is_sfb}, {rob_uop_1_16_is_sfb}, {rob_uop_1_15_is_sfb}, {rob_uop_1_14_is_sfb}, {rob_uop_1_13_is_sfb}, {rob_uop_1_12_is_sfb}, {rob_uop_1_11_is_sfb}, {rob_uop_1_10_is_sfb}, {rob_uop_1_9_is_sfb}, {rob_uop_1_8_is_sfb}, {rob_uop_1_7_is_sfb}, {rob_uop_1_6_is_sfb}, {rob_uop_1_5_is_sfb}, {rob_uop_1_4_is_sfb}, {rob_uop_1_3_is_sfb}, {rob_uop_1_2_is_sfb}, {rob_uop_1_1_is_sfb}, {rob_uop_1_0_is_sfb}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_sfb = _GEN_165[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_166 = {{rob_uop_1_31_is_fence}, {rob_uop_1_30_is_fence}, {rob_uop_1_29_is_fence}, {rob_uop_1_28_is_fence}, {rob_uop_1_27_is_fence}, {rob_uop_1_26_is_fence}, {rob_uop_1_25_is_fence}, {rob_uop_1_24_is_fence}, {rob_uop_1_23_is_fence}, {rob_uop_1_22_is_fence}, {rob_uop_1_21_is_fence}, {rob_uop_1_20_is_fence}, {rob_uop_1_19_is_fence}, {rob_uop_1_18_is_fence}, {rob_uop_1_17_is_fence}, {rob_uop_1_16_is_fence}, {rob_uop_1_15_is_fence}, {rob_uop_1_14_is_fence}, {rob_uop_1_13_is_fence}, {rob_uop_1_12_is_fence}, {rob_uop_1_11_is_fence}, {rob_uop_1_10_is_fence}, {rob_uop_1_9_is_fence}, {rob_uop_1_8_is_fence}, {rob_uop_1_7_is_fence}, {rob_uop_1_6_is_fence}, {rob_uop_1_5_is_fence}, {rob_uop_1_4_is_fence}, {rob_uop_1_3_is_fence}, {rob_uop_1_2_is_fence}, {rob_uop_1_1_is_fence}, {rob_uop_1_0_is_fence}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_fence = _GEN_166[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_167 = {{rob_uop_1_31_is_sfence}, {rob_uop_1_30_is_sfence}, {rob_uop_1_29_is_sfence}, {rob_uop_1_28_is_sfence}, {rob_uop_1_27_is_sfence}, {rob_uop_1_26_is_sfence}, {rob_uop_1_25_is_sfence}, {rob_uop_1_24_is_sfence}, {rob_uop_1_23_is_sfence}, {rob_uop_1_22_is_sfence}, {rob_uop_1_21_is_sfence}, {rob_uop_1_20_is_sfence}, {rob_uop_1_19_is_sfence}, {rob_uop_1_18_is_sfence}, {rob_uop_1_17_is_sfence}, {rob_uop_1_16_is_sfence}, {rob_uop_1_15_is_sfence}, {rob_uop_1_14_is_sfence}, {rob_uop_1_13_is_sfence}, {rob_uop_1_12_is_sfence}, {rob_uop_1_11_is_sfence}, {rob_uop_1_10_is_sfence}, {rob_uop_1_9_is_sfence}, {rob_uop_1_8_is_sfence}, {rob_uop_1_7_is_sfence}, {rob_uop_1_6_is_sfence}, {rob_uop_1_5_is_sfence}, {rob_uop_1_4_is_sfence}, {rob_uop_1_3_is_sfence}, {rob_uop_1_2_is_sfence}, {rob_uop_1_1_is_sfence}, {rob_uop_1_0_is_sfence}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_sfence = _GEN_167[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_168 = {{rob_uop_1_31_is_amo}, {rob_uop_1_30_is_amo}, {rob_uop_1_29_is_amo}, {rob_uop_1_28_is_amo}, {rob_uop_1_27_is_amo}, {rob_uop_1_26_is_amo}, {rob_uop_1_25_is_amo}, {rob_uop_1_24_is_amo}, {rob_uop_1_23_is_amo}, {rob_uop_1_22_is_amo}, {rob_uop_1_21_is_amo}, {rob_uop_1_20_is_amo}, {rob_uop_1_19_is_amo}, {rob_uop_1_18_is_amo}, {rob_uop_1_17_is_amo}, {rob_uop_1_16_is_amo}, {rob_uop_1_15_is_amo}, {rob_uop_1_14_is_amo}, {rob_uop_1_13_is_amo}, {rob_uop_1_12_is_amo}, {rob_uop_1_11_is_amo}, {rob_uop_1_10_is_amo}, {rob_uop_1_9_is_amo}, {rob_uop_1_8_is_amo}, {rob_uop_1_7_is_amo}, {rob_uop_1_6_is_amo}, {rob_uop_1_5_is_amo}, {rob_uop_1_4_is_amo}, {rob_uop_1_3_is_amo}, {rob_uop_1_2_is_amo}, {rob_uop_1_1_is_amo}, {rob_uop_1_0_is_amo}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_amo = _GEN_168[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_169 = {{rob_uop_1_31_is_eret}, {rob_uop_1_30_is_eret}, {rob_uop_1_29_is_eret}, {rob_uop_1_28_is_eret}, {rob_uop_1_27_is_eret}, {rob_uop_1_26_is_eret}, {rob_uop_1_25_is_eret}, {rob_uop_1_24_is_eret}, {rob_uop_1_23_is_eret}, {rob_uop_1_22_is_eret}, {rob_uop_1_21_is_eret}, {rob_uop_1_20_is_eret}, {rob_uop_1_19_is_eret}, {rob_uop_1_18_is_eret}, {rob_uop_1_17_is_eret}, {rob_uop_1_16_is_eret}, {rob_uop_1_15_is_eret}, {rob_uop_1_14_is_eret}, {rob_uop_1_13_is_eret}, {rob_uop_1_12_is_eret}, {rob_uop_1_11_is_eret}, {rob_uop_1_10_is_eret}, {rob_uop_1_9_is_eret}, {rob_uop_1_8_is_eret}, {rob_uop_1_7_is_eret}, {rob_uop_1_6_is_eret}, {rob_uop_1_5_is_eret}, {rob_uop_1_4_is_eret}, {rob_uop_1_3_is_eret}, {rob_uop_1_2_is_eret}, {rob_uop_1_1_is_eret}, {rob_uop_1_0_is_eret}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_eret = _GEN_169[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_170 = {{rob_uop_1_31_is_sys_pc2epc}, {rob_uop_1_30_is_sys_pc2epc}, {rob_uop_1_29_is_sys_pc2epc}, {rob_uop_1_28_is_sys_pc2epc}, {rob_uop_1_27_is_sys_pc2epc}, {rob_uop_1_26_is_sys_pc2epc}, {rob_uop_1_25_is_sys_pc2epc}, {rob_uop_1_24_is_sys_pc2epc}, {rob_uop_1_23_is_sys_pc2epc}, {rob_uop_1_22_is_sys_pc2epc}, {rob_uop_1_21_is_sys_pc2epc}, {rob_uop_1_20_is_sys_pc2epc}, {rob_uop_1_19_is_sys_pc2epc}, {rob_uop_1_18_is_sys_pc2epc}, {rob_uop_1_17_is_sys_pc2epc}, {rob_uop_1_16_is_sys_pc2epc}, {rob_uop_1_15_is_sys_pc2epc}, {rob_uop_1_14_is_sys_pc2epc}, {rob_uop_1_13_is_sys_pc2epc}, {rob_uop_1_12_is_sys_pc2epc}, {rob_uop_1_11_is_sys_pc2epc}, {rob_uop_1_10_is_sys_pc2epc}, {rob_uop_1_9_is_sys_pc2epc}, {rob_uop_1_8_is_sys_pc2epc}, {rob_uop_1_7_is_sys_pc2epc}, {rob_uop_1_6_is_sys_pc2epc}, {rob_uop_1_5_is_sys_pc2epc}, {rob_uop_1_4_is_sys_pc2epc}, {rob_uop_1_3_is_sys_pc2epc}, {rob_uop_1_2_is_sys_pc2epc}, {rob_uop_1_1_is_sys_pc2epc}, {rob_uop_1_0_is_sys_pc2epc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_sys_pc2epc = _GEN_170[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_171 = {{rob_uop_1_31_is_rocc}, {rob_uop_1_30_is_rocc}, {rob_uop_1_29_is_rocc}, {rob_uop_1_28_is_rocc}, {rob_uop_1_27_is_rocc}, {rob_uop_1_26_is_rocc}, {rob_uop_1_25_is_rocc}, {rob_uop_1_24_is_rocc}, {rob_uop_1_23_is_rocc}, {rob_uop_1_22_is_rocc}, {rob_uop_1_21_is_rocc}, {rob_uop_1_20_is_rocc}, {rob_uop_1_19_is_rocc}, {rob_uop_1_18_is_rocc}, {rob_uop_1_17_is_rocc}, {rob_uop_1_16_is_rocc}, {rob_uop_1_15_is_rocc}, {rob_uop_1_14_is_rocc}, {rob_uop_1_13_is_rocc}, {rob_uop_1_12_is_rocc}, {rob_uop_1_11_is_rocc}, {rob_uop_1_10_is_rocc}, {rob_uop_1_9_is_rocc}, {rob_uop_1_8_is_rocc}, {rob_uop_1_7_is_rocc}, {rob_uop_1_6_is_rocc}, {rob_uop_1_5_is_rocc}, {rob_uop_1_4_is_rocc}, {rob_uop_1_3_is_rocc}, {rob_uop_1_2_is_rocc}, {rob_uop_1_1_is_rocc}, {rob_uop_1_0_is_rocc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_rocc = _GEN_171[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_172 = {{rob_uop_1_31_is_mov}, {rob_uop_1_30_is_mov}, {rob_uop_1_29_is_mov}, {rob_uop_1_28_is_mov}, {rob_uop_1_27_is_mov}, {rob_uop_1_26_is_mov}, {rob_uop_1_25_is_mov}, {rob_uop_1_24_is_mov}, {rob_uop_1_23_is_mov}, {rob_uop_1_22_is_mov}, {rob_uop_1_21_is_mov}, {rob_uop_1_20_is_mov}, {rob_uop_1_19_is_mov}, {rob_uop_1_18_is_mov}, {rob_uop_1_17_is_mov}, {rob_uop_1_16_is_mov}, {rob_uop_1_15_is_mov}, {rob_uop_1_14_is_mov}, {rob_uop_1_13_is_mov}, {rob_uop_1_12_is_mov}, {rob_uop_1_11_is_mov}, {rob_uop_1_10_is_mov}, {rob_uop_1_9_is_mov}, {rob_uop_1_8_is_mov}, {rob_uop_1_7_is_mov}, {rob_uop_1_6_is_mov}, {rob_uop_1_5_is_mov}, {rob_uop_1_4_is_mov}, {rob_uop_1_3_is_mov}, {rob_uop_1_2_is_mov}, {rob_uop_1_1_is_mov}, {rob_uop_1_0_is_mov}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_mov = _GEN_172[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_173 = {{rob_uop_1_31_edge_inst}, {rob_uop_1_30_edge_inst}, {rob_uop_1_29_edge_inst}, {rob_uop_1_28_edge_inst}, {rob_uop_1_27_edge_inst}, {rob_uop_1_26_edge_inst}, {rob_uop_1_25_edge_inst}, {rob_uop_1_24_edge_inst}, {rob_uop_1_23_edge_inst}, {rob_uop_1_22_edge_inst}, {rob_uop_1_21_edge_inst}, {rob_uop_1_20_edge_inst}, {rob_uop_1_19_edge_inst}, {rob_uop_1_18_edge_inst}, {rob_uop_1_17_edge_inst}, {rob_uop_1_16_edge_inst}, {rob_uop_1_15_edge_inst}, {rob_uop_1_14_edge_inst}, {rob_uop_1_13_edge_inst}, {rob_uop_1_12_edge_inst}, {rob_uop_1_11_edge_inst}, {rob_uop_1_10_edge_inst}, {rob_uop_1_9_edge_inst}, {rob_uop_1_8_edge_inst}, {rob_uop_1_7_edge_inst}, {rob_uop_1_6_edge_inst}, {rob_uop_1_5_edge_inst}, {rob_uop_1_4_edge_inst}, {rob_uop_1_3_edge_inst}, {rob_uop_1_2_edge_inst}, {rob_uop_1_1_edge_inst}, {rob_uop_1_0_edge_inst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_edge_inst = _GEN_173[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_174 = {{rob_uop_1_31_pc_lob}, {rob_uop_1_30_pc_lob}, {rob_uop_1_29_pc_lob}, {rob_uop_1_28_pc_lob}, {rob_uop_1_27_pc_lob}, {rob_uop_1_26_pc_lob}, {rob_uop_1_25_pc_lob}, {rob_uop_1_24_pc_lob}, {rob_uop_1_23_pc_lob}, {rob_uop_1_22_pc_lob}, {rob_uop_1_21_pc_lob}, {rob_uop_1_20_pc_lob}, {rob_uop_1_19_pc_lob}, {rob_uop_1_18_pc_lob}, {rob_uop_1_17_pc_lob}, {rob_uop_1_16_pc_lob}, {rob_uop_1_15_pc_lob}, {rob_uop_1_14_pc_lob}, {rob_uop_1_13_pc_lob}, {rob_uop_1_12_pc_lob}, {rob_uop_1_11_pc_lob}, {rob_uop_1_10_pc_lob}, {rob_uop_1_9_pc_lob}, {rob_uop_1_8_pc_lob}, {rob_uop_1_7_pc_lob}, {rob_uop_1_6_pc_lob}, {rob_uop_1_5_pc_lob}, {rob_uop_1_4_pc_lob}, {rob_uop_1_3_pc_lob}, {rob_uop_1_2_pc_lob}, {rob_uop_1_1_pc_lob}, {rob_uop_1_0_pc_lob}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_pc_lob = _GEN_174[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_175 = {{rob_uop_1_31_taken}, {rob_uop_1_30_taken}, {rob_uop_1_29_taken}, {rob_uop_1_28_taken}, {rob_uop_1_27_taken}, {rob_uop_1_26_taken}, {rob_uop_1_25_taken}, {rob_uop_1_24_taken}, {rob_uop_1_23_taken}, {rob_uop_1_22_taken}, {rob_uop_1_21_taken}, {rob_uop_1_20_taken}, {rob_uop_1_19_taken}, {rob_uop_1_18_taken}, {rob_uop_1_17_taken}, {rob_uop_1_16_taken}, {rob_uop_1_15_taken}, {rob_uop_1_14_taken}, {rob_uop_1_13_taken}, {rob_uop_1_12_taken}, {rob_uop_1_11_taken}, {rob_uop_1_10_taken}, {rob_uop_1_9_taken}, {rob_uop_1_8_taken}, {rob_uop_1_7_taken}, {rob_uop_1_6_taken}, {rob_uop_1_5_taken}, {rob_uop_1_4_taken}, {rob_uop_1_3_taken}, {rob_uop_1_2_taken}, {rob_uop_1_1_taken}, {rob_uop_1_0_taken}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_taken = _GEN_175[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_176 = {{rob_uop_1_31_imm_rename}, {rob_uop_1_30_imm_rename}, {rob_uop_1_29_imm_rename}, {rob_uop_1_28_imm_rename}, {rob_uop_1_27_imm_rename}, {rob_uop_1_26_imm_rename}, {rob_uop_1_25_imm_rename}, {rob_uop_1_24_imm_rename}, {rob_uop_1_23_imm_rename}, {rob_uop_1_22_imm_rename}, {rob_uop_1_21_imm_rename}, {rob_uop_1_20_imm_rename}, {rob_uop_1_19_imm_rename}, {rob_uop_1_18_imm_rename}, {rob_uop_1_17_imm_rename}, {rob_uop_1_16_imm_rename}, {rob_uop_1_15_imm_rename}, {rob_uop_1_14_imm_rename}, {rob_uop_1_13_imm_rename}, {rob_uop_1_12_imm_rename}, {rob_uop_1_11_imm_rename}, {rob_uop_1_10_imm_rename}, {rob_uop_1_9_imm_rename}, {rob_uop_1_8_imm_rename}, {rob_uop_1_7_imm_rename}, {rob_uop_1_6_imm_rename}, {rob_uop_1_5_imm_rename}, {rob_uop_1_4_imm_rename}, {rob_uop_1_3_imm_rename}, {rob_uop_1_2_imm_rename}, {rob_uop_1_1_imm_rename}, {rob_uop_1_0_imm_rename}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_imm_rename = _GEN_176[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_177 = {{rob_uop_1_31_imm_sel}, {rob_uop_1_30_imm_sel}, {rob_uop_1_29_imm_sel}, {rob_uop_1_28_imm_sel}, {rob_uop_1_27_imm_sel}, {rob_uop_1_26_imm_sel}, {rob_uop_1_25_imm_sel}, {rob_uop_1_24_imm_sel}, {rob_uop_1_23_imm_sel}, {rob_uop_1_22_imm_sel}, {rob_uop_1_21_imm_sel}, {rob_uop_1_20_imm_sel}, {rob_uop_1_19_imm_sel}, {rob_uop_1_18_imm_sel}, {rob_uop_1_17_imm_sel}, {rob_uop_1_16_imm_sel}, {rob_uop_1_15_imm_sel}, {rob_uop_1_14_imm_sel}, {rob_uop_1_13_imm_sel}, {rob_uop_1_12_imm_sel}, {rob_uop_1_11_imm_sel}, {rob_uop_1_10_imm_sel}, {rob_uop_1_9_imm_sel}, {rob_uop_1_8_imm_sel}, {rob_uop_1_7_imm_sel}, {rob_uop_1_6_imm_sel}, {rob_uop_1_5_imm_sel}, {rob_uop_1_4_imm_sel}, {rob_uop_1_3_imm_sel}, {rob_uop_1_2_imm_sel}, {rob_uop_1_1_imm_sel}, {rob_uop_1_0_imm_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_imm_sel = _GEN_177[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_178 = {{rob_uop_1_31_pimm}, {rob_uop_1_30_pimm}, {rob_uop_1_29_pimm}, {rob_uop_1_28_pimm}, {rob_uop_1_27_pimm}, {rob_uop_1_26_pimm}, {rob_uop_1_25_pimm}, {rob_uop_1_24_pimm}, {rob_uop_1_23_pimm}, {rob_uop_1_22_pimm}, {rob_uop_1_21_pimm}, {rob_uop_1_20_pimm}, {rob_uop_1_19_pimm}, {rob_uop_1_18_pimm}, {rob_uop_1_17_pimm}, {rob_uop_1_16_pimm}, {rob_uop_1_15_pimm}, {rob_uop_1_14_pimm}, {rob_uop_1_13_pimm}, {rob_uop_1_12_pimm}, {rob_uop_1_11_pimm}, {rob_uop_1_10_pimm}, {rob_uop_1_9_pimm}, {rob_uop_1_8_pimm}, {rob_uop_1_7_pimm}, {rob_uop_1_6_pimm}, {rob_uop_1_5_pimm}, {rob_uop_1_4_pimm}, {rob_uop_1_3_pimm}, {rob_uop_1_2_pimm}, {rob_uop_1_1_pimm}, {rob_uop_1_0_pimm}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_pimm = _GEN_178[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][19:0] _GEN_179 = {{rob_uop_1_31_imm_packed}, {rob_uop_1_30_imm_packed}, {rob_uop_1_29_imm_packed}, {rob_uop_1_28_imm_packed}, {rob_uop_1_27_imm_packed}, {rob_uop_1_26_imm_packed}, {rob_uop_1_25_imm_packed}, {rob_uop_1_24_imm_packed}, {rob_uop_1_23_imm_packed}, {rob_uop_1_22_imm_packed}, {rob_uop_1_21_imm_packed}, {rob_uop_1_20_imm_packed}, {rob_uop_1_19_imm_packed}, {rob_uop_1_18_imm_packed}, {rob_uop_1_17_imm_packed}, {rob_uop_1_16_imm_packed}, {rob_uop_1_15_imm_packed}, {rob_uop_1_14_imm_packed}, {rob_uop_1_13_imm_packed}, {rob_uop_1_12_imm_packed}, {rob_uop_1_11_imm_packed}, {rob_uop_1_10_imm_packed}, {rob_uop_1_9_imm_packed}, {rob_uop_1_8_imm_packed}, {rob_uop_1_7_imm_packed}, {rob_uop_1_6_imm_packed}, {rob_uop_1_5_imm_packed}, {rob_uop_1_4_imm_packed}, {rob_uop_1_3_imm_packed}, {rob_uop_1_2_imm_packed}, {rob_uop_1_1_imm_packed}, {rob_uop_1_0_imm_packed}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_imm_packed = _GEN_179[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_180 = {{rob_uop_1_31_op1_sel}, {rob_uop_1_30_op1_sel}, {rob_uop_1_29_op1_sel}, {rob_uop_1_28_op1_sel}, {rob_uop_1_27_op1_sel}, {rob_uop_1_26_op1_sel}, {rob_uop_1_25_op1_sel}, {rob_uop_1_24_op1_sel}, {rob_uop_1_23_op1_sel}, {rob_uop_1_22_op1_sel}, {rob_uop_1_21_op1_sel}, {rob_uop_1_20_op1_sel}, {rob_uop_1_19_op1_sel}, {rob_uop_1_18_op1_sel}, {rob_uop_1_17_op1_sel}, {rob_uop_1_16_op1_sel}, {rob_uop_1_15_op1_sel}, {rob_uop_1_14_op1_sel}, {rob_uop_1_13_op1_sel}, {rob_uop_1_12_op1_sel}, {rob_uop_1_11_op1_sel}, {rob_uop_1_10_op1_sel}, {rob_uop_1_9_op1_sel}, {rob_uop_1_8_op1_sel}, {rob_uop_1_7_op1_sel}, {rob_uop_1_6_op1_sel}, {rob_uop_1_5_op1_sel}, {rob_uop_1_4_op1_sel}, {rob_uop_1_3_op1_sel}, {rob_uop_1_2_op1_sel}, {rob_uop_1_1_op1_sel}, {rob_uop_1_0_op1_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_op1_sel = _GEN_180[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_181 = {{rob_uop_1_31_op2_sel}, {rob_uop_1_30_op2_sel}, {rob_uop_1_29_op2_sel}, {rob_uop_1_28_op2_sel}, {rob_uop_1_27_op2_sel}, {rob_uop_1_26_op2_sel}, {rob_uop_1_25_op2_sel}, {rob_uop_1_24_op2_sel}, {rob_uop_1_23_op2_sel}, {rob_uop_1_22_op2_sel}, {rob_uop_1_21_op2_sel}, {rob_uop_1_20_op2_sel}, {rob_uop_1_19_op2_sel}, {rob_uop_1_18_op2_sel}, {rob_uop_1_17_op2_sel}, {rob_uop_1_16_op2_sel}, {rob_uop_1_15_op2_sel}, {rob_uop_1_14_op2_sel}, {rob_uop_1_13_op2_sel}, {rob_uop_1_12_op2_sel}, {rob_uop_1_11_op2_sel}, {rob_uop_1_10_op2_sel}, {rob_uop_1_9_op2_sel}, {rob_uop_1_8_op2_sel}, {rob_uop_1_7_op2_sel}, {rob_uop_1_6_op2_sel}, {rob_uop_1_5_op2_sel}, {rob_uop_1_4_op2_sel}, {rob_uop_1_3_op2_sel}, {rob_uop_1_2_op2_sel}, {rob_uop_1_1_op2_sel}, {rob_uop_1_0_op2_sel}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_op2_sel = _GEN_181[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_182 = {{rob_uop_1_31_fp_ctrl_ldst}, {rob_uop_1_30_fp_ctrl_ldst}, {rob_uop_1_29_fp_ctrl_ldst}, {rob_uop_1_28_fp_ctrl_ldst}, {rob_uop_1_27_fp_ctrl_ldst}, {rob_uop_1_26_fp_ctrl_ldst}, {rob_uop_1_25_fp_ctrl_ldst}, {rob_uop_1_24_fp_ctrl_ldst}, {rob_uop_1_23_fp_ctrl_ldst}, {rob_uop_1_22_fp_ctrl_ldst}, {rob_uop_1_21_fp_ctrl_ldst}, {rob_uop_1_20_fp_ctrl_ldst}, {rob_uop_1_19_fp_ctrl_ldst}, {rob_uop_1_18_fp_ctrl_ldst}, {rob_uop_1_17_fp_ctrl_ldst}, {rob_uop_1_16_fp_ctrl_ldst}, {rob_uop_1_15_fp_ctrl_ldst}, {rob_uop_1_14_fp_ctrl_ldst}, {rob_uop_1_13_fp_ctrl_ldst}, {rob_uop_1_12_fp_ctrl_ldst}, {rob_uop_1_11_fp_ctrl_ldst}, {rob_uop_1_10_fp_ctrl_ldst}, {rob_uop_1_9_fp_ctrl_ldst}, {rob_uop_1_8_fp_ctrl_ldst}, {rob_uop_1_7_fp_ctrl_ldst}, {rob_uop_1_6_fp_ctrl_ldst}, {rob_uop_1_5_fp_ctrl_ldst}, {rob_uop_1_4_fp_ctrl_ldst}, {rob_uop_1_3_fp_ctrl_ldst}, {rob_uop_1_2_fp_ctrl_ldst}, {rob_uop_1_1_fp_ctrl_ldst}, {rob_uop_1_0_fp_ctrl_ldst}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_ldst = _GEN_182[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_183 = {{rob_uop_1_31_fp_ctrl_wen}, {rob_uop_1_30_fp_ctrl_wen}, {rob_uop_1_29_fp_ctrl_wen}, {rob_uop_1_28_fp_ctrl_wen}, {rob_uop_1_27_fp_ctrl_wen}, {rob_uop_1_26_fp_ctrl_wen}, {rob_uop_1_25_fp_ctrl_wen}, {rob_uop_1_24_fp_ctrl_wen}, {rob_uop_1_23_fp_ctrl_wen}, {rob_uop_1_22_fp_ctrl_wen}, {rob_uop_1_21_fp_ctrl_wen}, {rob_uop_1_20_fp_ctrl_wen}, {rob_uop_1_19_fp_ctrl_wen}, {rob_uop_1_18_fp_ctrl_wen}, {rob_uop_1_17_fp_ctrl_wen}, {rob_uop_1_16_fp_ctrl_wen}, {rob_uop_1_15_fp_ctrl_wen}, {rob_uop_1_14_fp_ctrl_wen}, {rob_uop_1_13_fp_ctrl_wen}, {rob_uop_1_12_fp_ctrl_wen}, {rob_uop_1_11_fp_ctrl_wen}, {rob_uop_1_10_fp_ctrl_wen}, {rob_uop_1_9_fp_ctrl_wen}, {rob_uop_1_8_fp_ctrl_wen}, {rob_uop_1_7_fp_ctrl_wen}, {rob_uop_1_6_fp_ctrl_wen}, {rob_uop_1_5_fp_ctrl_wen}, {rob_uop_1_4_fp_ctrl_wen}, {rob_uop_1_3_fp_ctrl_wen}, {rob_uop_1_2_fp_ctrl_wen}, {rob_uop_1_1_fp_ctrl_wen}, {rob_uop_1_0_fp_ctrl_wen}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_wen = _GEN_183[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_184 = {{rob_uop_1_31_fp_ctrl_ren1}, {rob_uop_1_30_fp_ctrl_ren1}, {rob_uop_1_29_fp_ctrl_ren1}, {rob_uop_1_28_fp_ctrl_ren1}, {rob_uop_1_27_fp_ctrl_ren1}, {rob_uop_1_26_fp_ctrl_ren1}, {rob_uop_1_25_fp_ctrl_ren1}, {rob_uop_1_24_fp_ctrl_ren1}, {rob_uop_1_23_fp_ctrl_ren1}, {rob_uop_1_22_fp_ctrl_ren1}, {rob_uop_1_21_fp_ctrl_ren1}, {rob_uop_1_20_fp_ctrl_ren1}, {rob_uop_1_19_fp_ctrl_ren1}, {rob_uop_1_18_fp_ctrl_ren1}, {rob_uop_1_17_fp_ctrl_ren1}, {rob_uop_1_16_fp_ctrl_ren1}, {rob_uop_1_15_fp_ctrl_ren1}, {rob_uop_1_14_fp_ctrl_ren1}, {rob_uop_1_13_fp_ctrl_ren1}, {rob_uop_1_12_fp_ctrl_ren1}, {rob_uop_1_11_fp_ctrl_ren1}, {rob_uop_1_10_fp_ctrl_ren1}, {rob_uop_1_9_fp_ctrl_ren1}, {rob_uop_1_8_fp_ctrl_ren1}, {rob_uop_1_7_fp_ctrl_ren1}, {rob_uop_1_6_fp_ctrl_ren1}, {rob_uop_1_5_fp_ctrl_ren1}, {rob_uop_1_4_fp_ctrl_ren1}, {rob_uop_1_3_fp_ctrl_ren1}, {rob_uop_1_2_fp_ctrl_ren1}, {rob_uop_1_1_fp_ctrl_ren1}, {rob_uop_1_0_fp_ctrl_ren1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_ren1 = _GEN_184[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_185 = {{rob_uop_1_31_fp_ctrl_ren2}, {rob_uop_1_30_fp_ctrl_ren2}, {rob_uop_1_29_fp_ctrl_ren2}, {rob_uop_1_28_fp_ctrl_ren2}, {rob_uop_1_27_fp_ctrl_ren2}, {rob_uop_1_26_fp_ctrl_ren2}, {rob_uop_1_25_fp_ctrl_ren2}, {rob_uop_1_24_fp_ctrl_ren2}, {rob_uop_1_23_fp_ctrl_ren2}, {rob_uop_1_22_fp_ctrl_ren2}, {rob_uop_1_21_fp_ctrl_ren2}, {rob_uop_1_20_fp_ctrl_ren2}, {rob_uop_1_19_fp_ctrl_ren2}, {rob_uop_1_18_fp_ctrl_ren2}, {rob_uop_1_17_fp_ctrl_ren2}, {rob_uop_1_16_fp_ctrl_ren2}, {rob_uop_1_15_fp_ctrl_ren2}, {rob_uop_1_14_fp_ctrl_ren2}, {rob_uop_1_13_fp_ctrl_ren2}, {rob_uop_1_12_fp_ctrl_ren2}, {rob_uop_1_11_fp_ctrl_ren2}, {rob_uop_1_10_fp_ctrl_ren2}, {rob_uop_1_9_fp_ctrl_ren2}, {rob_uop_1_8_fp_ctrl_ren2}, {rob_uop_1_7_fp_ctrl_ren2}, {rob_uop_1_6_fp_ctrl_ren2}, {rob_uop_1_5_fp_ctrl_ren2}, {rob_uop_1_4_fp_ctrl_ren2}, {rob_uop_1_3_fp_ctrl_ren2}, {rob_uop_1_2_fp_ctrl_ren2}, {rob_uop_1_1_fp_ctrl_ren2}, {rob_uop_1_0_fp_ctrl_ren2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_ren2 = _GEN_185[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_186 = {{rob_uop_1_31_fp_ctrl_ren3}, {rob_uop_1_30_fp_ctrl_ren3}, {rob_uop_1_29_fp_ctrl_ren3}, {rob_uop_1_28_fp_ctrl_ren3}, {rob_uop_1_27_fp_ctrl_ren3}, {rob_uop_1_26_fp_ctrl_ren3}, {rob_uop_1_25_fp_ctrl_ren3}, {rob_uop_1_24_fp_ctrl_ren3}, {rob_uop_1_23_fp_ctrl_ren3}, {rob_uop_1_22_fp_ctrl_ren3}, {rob_uop_1_21_fp_ctrl_ren3}, {rob_uop_1_20_fp_ctrl_ren3}, {rob_uop_1_19_fp_ctrl_ren3}, {rob_uop_1_18_fp_ctrl_ren3}, {rob_uop_1_17_fp_ctrl_ren3}, {rob_uop_1_16_fp_ctrl_ren3}, {rob_uop_1_15_fp_ctrl_ren3}, {rob_uop_1_14_fp_ctrl_ren3}, {rob_uop_1_13_fp_ctrl_ren3}, {rob_uop_1_12_fp_ctrl_ren3}, {rob_uop_1_11_fp_ctrl_ren3}, {rob_uop_1_10_fp_ctrl_ren3}, {rob_uop_1_9_fp_ctrl_ren3}, {rob_uop_1_8_fp_ctrl_ren3}, {rob_uop_1_7_fp_ctrl_ren3}, {rob_uop_1_6_fp_ctrl_ren3}, {rob_uop_1_5_fp_ctrl_ren3}, {rob_uop_1_4_fp_ctrl_ren3}, {rob_uop_1_3_fp_ctrl_ren3}, {rob_uop_1_2_fp_ctrl_ren3}, {rob_uop_1_1_fp_ctrl_ren3}, {rob_uop_1_0_fp_ctrl_ren3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_ren3 = _GEN_186[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_187 = {{rob_uop_1_31_fp_ctrl_swap12}, {rob_uop_1_30_fp_ctrl_swap12}, {rob_uop_1_29_fp_ctrl_swap12}, {rob_uop_1_28_fp_ctrl_swap12}, {rob_uop_1_27_fp_ctrl_swap12}, {rob_uop_1_26_fp_ctrl_swap12}, {rob_uop_1_25_fp_ctrl_swap12}, {rob_uop_1_24_fp_ctrl_swap12}, {rob_uop_1_23_fp_ctrl_swap12}, {rob_uop_1_22_fp_ctrl_swap12}, {rob_uop_1_21_fp_ctrl_swap12}, {rob_uop_1_20_fp_ctrl_swap12}, {rob_uop_1_19_fp_ctrl_swap12}, {rob_uop_1_18_fp_ctrl_swap12}, {rob_uop_1_17_fp_ctrl_swap12}, {rob_uop_1_16_fp_ctrl_swap12}, {rob_uop_1_15_fp_ctrl_swap12}, {rob_uop_1_14_fp_ctrl_swap12}, {rob_uop_1_13_fp_ctrl_swap12}, {rob_uop_1_12_fp_ctrl_swap12}, {rob_uop_1_11_fp_ctrl_swap12}, {rob_uop_1_10_fp_ctrl_swap12}, {rob_uop_1_9_fp_ctrl_swap12}, {rob_uop_1_8_fp_ctrl_swap12}, {rob_uop_1_7_fp_ctrl_swap12}, {rob_uop_1_6_fp_ctrl_swap12}, {rob_uop_1_5_fp_ctrl_swap12}, {rob_uop_1_4_fp_ctrl_swap12}, {rob_uop_1_3_fp_ctrl_swap12}, {rob_uop_1_2_fp_ctrl_swap12}, {rob_uop_1_1_fp_ctrl_swap12}, {rob_uop_1_0_fp_ctrl_swap12}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_swap12 = _GEN_187[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_188 = {{rob_uop_1_31_fp_ctrl_swap23}, {rob_uop_1_30_fp_ctrl_swap23}, {rob_uop_1_29_fp_ctrl_swap23}, {rob_uop_1_28_fp_ctrl_swap23}, {rob_uop_1_27_fp_ctrl_swap23}, {rob_uop_1_26_fp_ctrl_swap23}, {rob_uop_1_25_fp_ctrl_swap23}, {rob_uop_1_24_fp_ctrl_swap23}, {rob_uop_1_23_fp_ctrl_swap23}, {rob_uop_1_22_fp_ctrl_swap23}, {rob_uop_1_21_fp_ctrl_swap23}, {rob_uop_1_20_fp_ctrl_swap23}, {rob_uop_1_19_fp_ctrl_swap23}, {rob_uop_1_18_fp_ctrl_swap23}, {rob_uop_1_17_fp_ctrl_swap23}, {rob_uop_1_16_fp_ctrl_swap23}, {rob_uop_1_15_fp_ctrl_swap23}, {rob_uop_1_14_fp_ctrl_swap23}, {rob_uop_1_13_fp_ctrl_swap23}, {rob_uop_1_12_fp_ctrl_swap23}, {rob_uop_1_11_fp_ctrl_swap23}, {rob_uop_1_10_fp_ctrl_swap23}, {rob_uop_1_9_fp_ctrl_swap23}, {rob_uop_1_8_fp_ctrl_swap23}, {rob_uop_1_7_fp_ctrl_swap23}, {rob_uop_1_6_fp_ctrl_swap23}, {rob_uop_1_5_fp_ctrl_swap23}, {rob_uop_1_4_fp_ctrl_swap23}, {rob_uop_1_3_fp_ctrl_swap23}, {rob_uop_1_2_fp_ctrl_swap23}, {rob_uop_1_1_fp_ctrl_swap23}, {rob_uop_1_0_fp_ctrl_swap23}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_swap23 = _GEN_188[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_189 = {{rob_uop_1_31_fp_ctrl_typeTagIn}, {rob_uop_1_30_fp_ctrl_typeTagIn}, {rob_uop_1_29_fp_ctrl_typeTagIn}, {rob_uop_1_28_fp_ctrl_typeTagIn}, {rob_uop_1_27_fp_ctrl_typeTagIn}, {rob_uop_1_26_fp_ctrl_typeTagIn}, {rob_uop_1_25_fp_ctrl_typeTagIn}, {rob_uop_1_24_fp_ctrl_typeTagIn}, {rob_uop_1_23_fp_ctrl_typeTagIn}, {rob_uop_1_22_fp_ctrl_typeTagIn}, {rob_uop_1_21_fp_ctrl_typeTagIn}, {rob_uop_1_20_fp_ctrl_typeTagIn}, {rob_uop_1_19_fp_ctrl_typeTagIn}, {rob_uop_1_18_fp_ctrl_typeTagIn}, {rob_uop_1_17_fp_ctrl_typeTagIn}, {rob_uop_1_16_fp_ctrl_typeTagIn}, {rob_uop_1_15_fp_ctrl_typeTagIn}, {rob_uop_1_14_fp_ctrl_typeTagIn}, {rob_uop_1_13_fp_ctrl_typeTagIn}, {rob_uop_1_12_fp_ctrl_typeTagIn}, {rob_uop_1_11_fp_ctrl_typeTagIn}, {rob_uop_1_10_fp_ctrl_typeTagIn}, {rob_uop_1_9_fp_ctrl_typeTagIn}, {rob_uop_1_8_fp_ctrl_typeTagIn}, {rob_uop_1_7_fp_ctrl_typeTagIn}, {rob_uop_1_6_fp_ctrl_typeTagIn}, {rob_uop_1_5_fp_ctrl_typeTagIn}, {rob_uop_1_4_fp_ctrl_typeTagIn}, {rob_uop_1_3_fp_ctrl_typeTagIn}, {rob_uop_1_2_fp_ctrl_typeTagIn}, {rob_uop_1_1_fp_ctrl_typeTagIn}, {rob_uop_1_0_fp_ctrl_typeTagIn}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_typeTagIn = _GEN_189[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_190 = {{rob_uop_1_31_fp_ctrl_typeTagOut}, {rob_uop_1_30_fp_ctrl_typeTagOut}, {rob_uop_1_29_fp_ctrl_typeTagOut}, {rob_uop_1_28_fp_ctrl_typeTagOut}, {rob_uop_1_27_fp_ctrl_typeTagOut}, {rob_uop_1_26_fp_ctrl_typeTagOut}, {rob_uop_1_25_fp_ctrl_typeTagOut}, {rob_uop_1_24_fp_ctrl_typeTagOut}, {rob_uop_1_23_fp_ctrl_typeTagOut}, {rob_uop_1_22_fp_ctrl_typeTagOut}, {rob_uop_1_21_fp_ctrl_typeTagOut}, {rob_uop_1_20_fp_ctrl_typeTagOut}, {rob_uop_1_19_fp_ctrl_typeTagOut}, {rob_uop_1_18_fp_ctrl_typeTagOut}, {rob_uop_1_17_fp_ctrl_typeTagOut}, {rob_uop_1_16_fp_ctrl_typeTagOut}, {rob_uop_1_15_fp_ctrl_typeTagOut}, {rob_uop_1_14_fp_ctrl_typeTagOut}, {rob_uop_1_13_fp_ctrl_typeTagOut}, {rob_uop_1_12_fp_ctrl_typeTagOut}, {rob_uop_1_11_fp_ctrl_typeTagOut}, {rob_uop_1_10_fp_ctrl_typeTagOut}, {rob_uop_1_9_fp_ctrl_typeTagOut}, {rob_uop_1_8_fp_ctrl_typeTagOut}, {rob_uop_1_7_fp_ctrl_typeTagOut}, {rob_uop_1_6_fp_ctrl_typeTagOut}, {rob_uop_1_5_fp_ctrl_typeTagOut}, {rob_uop_1_4_fp_ctrl_typeTagOut}, {rob_uop_1_3_fp_ctrl_typeTagOut}, {rob_uop_1_2_fp_ctrl_typeTagOut}, {rob_uop_1_1_fp_ctrl_typeTagOut}, {rob_uop_1_0_fp_ctrl_typeTagOut}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_typeTagOut = _GEN_190[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_191 = {{rob_uop_1_31_fp_ctrl_fromint}, {rob_uop_1_30_fp_ctrl_fromint}, {rob_uop_1_29_fp_ctrl_fromint}, {rob_uop_1_28_fp_ctrl_fromint}, {rob_uop_1_27_fp_ctrl_fromint}, {rob_uop_1_26_fp_ctrl_fromint}, {rob_uop_1_25_fp_ctrl_fromint}, {rob_uop_1_24_fp_ctrl_fromint}, {rob_uop_1_23_fp_ctrl_fromint}, {rob_uop_1_22_fp_ctrl_fromint}, {rob_uop_1_21_fp_ctrl_fromint}, {rob_uop_1_20_fp_ctrl_fromint}, {rob_uop_1_19_fp_ctrl_fromint}, {rob_uop_1_18_fp_ctrl_fromint}, {rob_uop_1_17_fp_ctrl_fromint}, {rob_uop_1_16_fp_ctrl_fromint}, {rob_uop_1_15_fp_ctrl_fromint}, {rob_uop_1_14_fp_ctrl_fromint}, {rob_uop_1_13_fp_ctrl_fromint}, {rob_uop_1_12_fp_ctrl_fromint}, {rob_uop_1_11_fp_ctrl_fromint}, {rob_uop_1_10_fp_ctrl_fromint}, {rob_uop_1_9_fp_ctrl_fromint}, {rob_uop_1_8_fp_ctrl_fromint}, {rob_uop_1_7_fp_ctrl_fromint}, {rob_uop_1_6_fp_ctrl_fromint}, {rob_uop_1_5_fp_ctrl_fromint}, {rob_uop_1_4_fp_ctrl_fromint}, {rob_uop_1_3_fp_ctrl_fromint}, {rob_uop_1_2_fp_ctrl_fromint}, {rob_uop_1_1_fp_ctrl_fromint}, {rob_uop_1_0_fp_ctrl_fromint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_fromint = _GEN_191[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_192 = {{rob_uop_1_31_fp_ctrl_toint}, {rob_uop_1_30_fp_ctrl_toint}, {rob_uop_1_29_fp_ctrl_toint}, {rob_uop_1_28_fp_ctrl_toint}, {rob_uop_1_27_fp_ctrl_toint}, {rob_uop_1_26_fp_ctrl_toint}, {rob_uop_1_25_fp_ctrl_toint}, {rob_uop_1_24_fp_ctrl_toint}, {rob_uop_1_23_fp_ctrl_toint}, {rob_uop_1_22_fp_ctrl_toint}, {rob_uop_1_21_fp_ctrl_toint}, {rob_uop_1_20_fp_ctrl_toint}, {rob_uop_1_19_fp_ctrl_toint}, {rob_uop_1_18_fp_ctrl_toint}, {rob_uop_1_17_fp_ctrl_toint}, {rob_uop_1_16_fp_ctrl_toint}, {rob_uop_1_15_fp_ctrl_toint}, {rob_uop_1_14_fp_ctrl_toint}, {rob_uop_1_13_fp_ctrl_toint}, {rob_uop_1_12_fp_ctrl_toint}, {rob_uop_1_11_fp_ctrl_toint}, {rob_uop_1_10_fp_ctrl_toint}, {rob_uop_1_9_fp_ctrl_toint}, {rob_uop_1_8_fp_ctrl_toint}, {rob_uop_1_7_fp_ctrl_toint}, {rob_uop_1_6_fp_ctrl_toint}, {rob_uop_1_5_fp_ctrl_toint}, {rob_uop_1_4_fp_ctrl_toint}, {rob_uop_1_3_fp_ctrl_toint}, {rob_uop_1_2_fp_ctrl_toint}, {rob_uop_1_1_fp_ctrl_toint}, {rob_uop_1_0_fp_ctrl_toint}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_toint = _GEN_192[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_193 = {{rob_uop_1_31_fp_ctrl_fastpipe}, {rob_uop_1_30_fp_ctrl_fastpipe}, {rob_uop_1_29_fp_ctrl_fastpipe}, {rob_uop_1_28_fp_ctrl_fastpipe}, {rob_uop_1_27_fp_ctrl_fastpipe}, {rob_uop_1_26_fp_ctrl_fastpipe}, {rob_uop_1_25_fp_ctrl_fastpipe}, {rob_uop_1_24_fp_ctrl_fastpipe}, {rob_uop_1_23_fp_ctrl_fastpipe}, {rob_uop_1_22_fp_ctrl_fastpipe}, {rob_uop_1_21_fp_ctrl_fastpipe}, {rob_uop_1_20_fp_ctrl_fastpipe}, {rob_uop_1_19_fp_ctrl_fastpipe}, {rob_uop_1_18_fp_ctrl_fastpipe}, {rob_uop_1_17_fp_ctrl_fastpipe}, {rob_uop_1_16_fp_ctrl_fastpipe}, {rob_uop_1_15_fp_ctrl_fastpipe}, {rob_uop_1_14_fp_ctrl_fastpipe}, {rob_uop_1_13_fp_ctrl_fastpipe}, {rob_uop_1_12_fp_ctrl_fastpipe}, {rob_uop_1_11_fp_ctrl_fastpipe}, {rob_uop_1_10_fp_ctrl_fastpipe}, {rob_uop_1_9_fp_ctrl_fastpipe}, {rob_uop_1_8_fp_ctrl_fastpipe}, {rob_uop_1_7_fp_ctrl_fastpipe}, {rob_uop_1_6_fp_ctrl_fastpipe}, {rob_uop_1_5_fp_ctrl_fastpipe}, {rob_uop_1_4_fp_ctrl_fastpipe}, {rob_uop_1_3_fp_ctrl_fastpipe}, {rob_uop_1_2_fp_ctrl_fastpipe}, {rob_uop_1_1_fp_ctrl_fastpipe}, {rob_uop_1_0_fp_ctrl_fastpipe}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_fastpipe = _GEN_193[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_194 = {{rob_uop_1_31_fp_ctrl_fma}, {rob_uop_1_30_fp_ctrl_fma}, {rob_uop_1_29_fp_ctrl_fma}, {rob_uop_1_28_fp_ctrl_fma}, {rob_uop_1_27_fp_ctrl_fma}, {rob_uop_1_26_fp_ctrl_fma}, {rob_uop_1_25_fp_ctrl_fma}, {rob_uop_1_24_fp_ctrl_fma}, {rob_uop_1_23_fp_ctrl_fma}, {rob_uop_1_22_fp_ctrl_fma}, {rob_uop_1_21_fp_ctrl_fma}, {rob_uop_1_20_fp_ctrl_fma}, {rob_uop_1_19_fp_ctrl_fma}, {rob_uop_1_18_fp_ctrl_fma}, {rob_uop_1_17_fp_ctrl_fma}, {rob_uop_1_16_fp_ctrl_fma}, {rob_uop_1_15_fp_ctrl_fma}, {rob_uop_1_14_fp_ctrl_fma}, {rob_uop_1_13_fp_ctrl_fma}, {rob_uop_1_12_fp_ctrl_fma}, {rob_uop_1_11_fp_ctrl_fma}, {rob_uop_1_10_fp_ctrl_fma}, {rob_uop_1_9_fp_ctrl_fma}, {rob_uop_1_8_fp_ctrl_fma}, {rob_uop_1_7_fp_ctrl_fma}, {rob_uop_1_6_fp_ctrl_fma}, {rob_uop_1_5_fp_ctrl_fma}, {rob_uop_1_4_fp_ctrl_fma}, {rob_uop_1_3_fp_ctrl_fma}, {rob_uop_1_2_fp_ctrl_fma}, {rob_uop_1_1_fp_ctrl_fma}, {rob_uop_1_0_fp_ctrl_fma}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_fma = _GEN_194[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_195 = {{rob_uop_1_31_fp_ctrl_div}, {rob_uop_1_30_fp_ctrl_div}, {rob_uop_1_29_fp_ctrl_div}, {rob_uop_1_28_fp_ctrl_div}, {rob_uop_1_27_fp_ctrl_div}, {rob_uop_1_26_fp_ctrl_div}, {rob_uop_1_25_fp_ctrl_div}, {rob_uop_1_24_fp_ctrl_div}, {rob_uop_1_23_fp_ctrl_div}, {rob_uop_1_22_fp_ctrl_div}, {rob_uop_1_21_fp_ctrl_div}, {rob_uop_1_20_fp_ctrl_div}, {rob_uop_1_19_fp_ctrl_div}, {rob_uop_1_18_fp_ctrl_div}, {rob_uop_1_17_fp_ctrl_div}, {rob_uop_1_16_fp_ctrl_div}, {rob_uop_1_15_fp_ctrl_div}, {rob_uop_1_14_fp_ctrl_div}, {rob_uop_1_13_fp_ctrl_div}, {rob_uop_1_12_fp_ctrl_div}, {rob_uop_1_11_fp_ctrl_div}, {rob_uop_1_10_fp_ctrl_div}, {rob_uop_1_9_fp_ctrl_div}, {rob_uop_1_8_fp_ctrl_div}, {rob_uop_1_7_fp_ctrl_div}, {rob_uop_1_6_fp_ctrl_div}, {rob_uop_1_5_fp_ctrl_div}, {rob_uop_1_4_fp_ctrl_div}, {rob_uop_1_3_fp_ctrl_div}, {rob_uop_1_2_fp_ctrl_div}, {rob_uop_1_1_fp_ctrl_div}, {rob_uop_1_0_fp_ctrl_div}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_div = _GEN_195[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_196 = {{rob_uop_1_31_fp_ctrl_sqrt}, {rob_uop_1_30_fp_ctrl_sqrt}, {rob_uop_1_29_fp_ctrl_sqrt}, {rob_uop_1_28_fp_ctrl_sqrt}, {rob_uop_1_27_fp_ctrl_sqrt}, {rob_uop_1_26_fp_ctrl_sqrt}, {rob_uop_1_25_fp_ctrl_sqrt}, {rob_uop_1_24_fp_ctrl_sqrt}, {rob_uop_1_23_fp_ctrl_sqrt}, {rob_uop_1_22_fp_ctrl_sqrt}, {rob_uop_1_21_fp_ctrl_sqrt}, {rob_uop_1_20_fp_ctrl_sqrt}, {rob_uop_1_19_fp_ctrl_sqrt}, {rob_uop_1_18_fp_ctrl_sqrt}, {rob_uop_1_17_fp_ctrl_sqrt}, {rob_uop_1_16_fp_ctrl_sqrt}, {rob_uop_1_15_fp_ctrl_sqrt}, {rob_uop_1_14_fp_ctrl_sqrt}, {rob_uop_1_13_fp_ctrl_sqrt}, {rob_uop_1_12_fp_ctrl_sqrt}, {rob_uop_1_11_fp_ctrl_sqrt}, {rob_uop_1_10_fp_ctrl_sqrt}, {rob_uop_1_9_fp_ctrl_sqrt}, {rob_uop_1_8_fp_ctrl_sqrt}, {rob_uop_1_7_fp_ctrl_sqrt}, {rob_uop_1_6_fp_ctrl_sqrt}, {rob_uop_1_5_fp_ctrl_sqrt}, {rob_uop_1_4_fp_ctrl_sqrt}, {rob_uop_1_3_fp_ctrl_sqrt}, {rob_uop_1_2_fp_ctrl_sqrt}, {rob_uop_1_1_fp_ctrl_sqrt}, {rob_uop_1_0_fp_ctrl_sqrt}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_sqrt = _GEN_196[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_197 = {{rob_uop_1_31_fp_ctrl_wflags}, {rob_uop_1_30_fp_ctrl_wflags}, {rob_uop_1_29_fp_ctrl_wflags}, {rob_uop_1_28_fp_ctrl_wflags}, {rob_uop_1_27_fp_ctrl_wflags}, {rob_uop_1_26_fp_ctrl_wflags}, {rob_uop_1_25_fp_ctrl_wflags}, {rob_uop_1_24_fp_ctrl_wflags}, {rob_uop_1_23_fp_ctrl_wflags}, {rob_uop_1_22_fp_ctrl_wflags}, {rob_uop_1_21_fp_ctrl_wflags}, {rob_uop_1_20_fp_ctrl_wflags}, {rob_uop_1_19_fp_ctrl_wflags}, {rob_uop_1_18_fp_ctrl_wflags}, {rob_uop_1_17_fp_ctrl_wflags}, {rob_uop_1_16_fp_ctrl_wflags}, {rob_uop_1_15_fp_ctrl_wflags}, {rob_uop_1_14_fp_ctrl_wflags}, {rob_uop_1_13_fp_ctrl_wflags}, {rob_uop_1_12_fp_ctrl_wflags}, {rob_uop_1_11_fp_ctrl_wflags}, {rob_uop_1_10_fp_ctrl_wflags}, {rob_uop_1_9_fp_ctrl_wflags}, {rob_uop_1_8_fp_ctrl_wflags}, {rob_uop_1_7_fp_ctrl_wflags}, {rob_uop_1_6_fp_ctrl_wflags}, {rob_uop_1_5_fp_ctrl_wflags}, {rob_uop_1_4_fp_ctrl_wflags}, {rob_uop_1_3_fp_ctrl_wflags}, {rob_uop_1_2_fp_ctrl_wflags}, {rob_uop_1_1_fp_ctrl_wflags}, {rob_uop_1_0_fp_ctrl_wflags}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_wflags = _GEN_197[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_198 = {{rob_uop_1_31_fp_ctrl_vec}, {rob_uop_1_30_fp_ctrl_vec}, {rob_uop_1_29_fp_ctrl_vec}, {rob_uop_1_28_fp_ctrl_vec}, {rob_uop_1_27_fp_ctrl_vec}, {rob_uop_1_26_fp_ctrl_vec}, {rob_uop_1_25_fp_ctrl_vec}, {rob_uop_1_24_fp_ctrl_vec}, {rob_uop_1_23_fp_ctrl_vec}, {rob_uop_1_22_fp_ctrl_vec}, {rob_uop_1_21_fp_ctrl_vec}, {rob_uop_1_20_fp_ctrl_vec}, {rob_uop_1_19_fp_ctrl_vec}, {rob_uop_1_18_fp_ctrl_vec}, {rob_uop_1_17_fp_ctrl_vec}, {rob_uop_1_16_fp_ctrl_vec}, {rob_uop_1_15_fp_ctrl_vec}, {rob_uop_1_14_fp_ctrl_vec}, {rob_uop_1_13_fp_ctrl_vec}, {rob_uop_1_12_fp_ctrl_vec}, {rob_uop_1_11_fp_ctrl_vec}, {rob_uop_1_10_fp_ctrl_vec}, {rob_uop_1_9_fp_ctrl_vec}, {rob_uop_1_8_fp_ctrl_vec}, {rob_uop_1_7_fp_ctrl_vec}, {rob_uop_1_6_fp_ctrl_vec}, {rob_uop_1_5_fp_ctrl_vec}, {rob_uop_1_4_fp_ctrl_vec}, {rob_uop_1_3_fp_ctrl_vec}, {rob_uop_1_2_fp_ctrl_vec}, {rob_uop_1_1_fp_ctrl_vec}, {rob_uop_1_0_fp_ctrl_vec}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_ctrl_vec = _GEN_198[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_199 = {{rob_uop_1_31_rob_idx}, {rob_uop_1_30_rob_idx}, {rob_uop_1_29_rob_idx}, {rob_uop_1_28_rob_idx}, {rob_uop_1_27_rob_idx}, {rob_uop_1_26_rob_idx}, {rob_uop_1_25_rob_idx}, {rob_uop_1_24_rob_idx}, {rob_uop_1_23_rob_idx}, {rob_uop_1_22_rob_idx}, {rob_uop_1_21_rob_idx}, {rob_uop_1_20_rob_idx}, {rob_uop_1_19_rob_idx}, {rob_uop_1_18_rob_idx}, {rob_uop_1_17_rob_idx}, {rob_uop_1_16_rob_idx}, {rob_uop_1_15_rob_idx}, {rob_uop_1_14_rob_idx}, {rob_uop_1_13_rob_idx}, {rob_uop_1_12_rob_idx}, {rob_uop_1_11_rob_idx}, {rob_uop_1_10_rob_idx}, {rob_uop_1_9_rob_idx}, {rob_uop_1_8_rob_idx}, {rob_uop_1_7_rob_idx}, {rob_uop_1_6_rob_idx}, {rob_uop_1_5_rob_idx}, {rob_uop_1_4_rob_idx}, {rob_uop_1_3_rob_idx}, {rob_uop_1_2_rob_idx}, {rob_uop_1_1_rob_idx}, {rob_uop_1_0_rob_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_rob_idx = _GEN_199[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_200 = {{rob_uop_1_31_ldq_idx}, {rob_uop_1_30_ldq_idx}, {rob_uop_1_29_ldq_idx}, {rob_uop_1_28_ldq_idx}, {rob_uop_1_27_ldq_idx}, {rob_uop_1_26_ldq_idx}, {rob_uop_1_25_ldq_idx}, {rob_uop_1_24_ldq_idx}, {rob_uop_1_23_ldq_idx}, {rob_uop_1_22_ldq_idx}, {rob_uop_1_21_ldq_idx}, {rob_uop_1_20_ldq_idx}, {rob_uop_1_19_ldq_idx}, {rob_uop_1_18_ldq_idx}, {rob_uop_1_17_ldq_idx}, {rob_uop_1_16_ldq_idx}, {rob_uop_1_15_ldq_idx}, {rob_uop_1_14_ldq_idx}, {rob_uop_1_13_ldq_idx}, {rob_uop_1_12_ldq_idx}, {rob_uop_1_11_ldq_idx}, {rob_uop_1_10_ldq_idx}, {rob_uop_1_9_ldq_idx}, {rob_uop_1_8_ldq_idx}, {rob_uop_1_7_ldq_idx}, {rob_uop_1_6_ldq_idx}, {rob_uop_1_5_ldq_idx}, {rob_uop_1_4_ldq_idx}, {rob_uop_1_3_ldq_idx}, {rob_uop_1_2_ldq_idx}, {rob_uop_1_1_ldq_idx}, {rob_uop_1_0_ldq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_ldq_idx = _GEN_200[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][3:0] _GEN_201 = {{rob_uop_1_31_stq_idx}, {rob_uop_1_30_stq_idx}, {rob_uop_1_29_stq_idx}, {rob_uop_1_28_stq_idx}, {rob_uop_1_27_stq_idx}, {rob_uop_1_26_stq_idx}, {rob_uop_1_25_stq_idx}, {rob_uop_1_24_stq_idx}, {rob_uop_1_23_stq_idx}, {rob_uop_1_22_stq_idx}, {rob_uop_1_21_stq_idx}, {rob_uop_1_20_stq_idx}, {rob_uop_1_19_stq_idx}, {rob_uop_1_18_stq_idx}, {rob_uop_1_17_stq_idx}, {rob_uop_1_16_stq_idx}, {rob_uop_1_15_stq_idx}, {rob_uop_1_14_stq_idx}, {rob_uop_1_13_stq_idx}, {rob_uop_1_12_stq_idx}, {rob_uop_1_11_stq_idx}, {rob_uop_1_10_stq_idx}, {rob_uop_1_9_stq_idx}, {rob_uop_1_8_stq_idx}, {rob_uop_1_7_stq_idx}, {rob_uop_1_6_stq_idx}, {rob_uop_1_5_stq_idx}, {rob_uop_1_4_stq_idx}, {rob_uop_1_3_stq_idx}, {rob_uop_1_2_stq_idx}, {rob_uop_1_1_stq_idx}, {rob_uop_1_0_stq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_stq_idx = _GEN_201[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_202 = {{rob_uop_1_31_rxq_idx}, {rob_uop_1_30_rxq_idx}, {rob_uop_1_29_rxq_idx}, {rob_uop_1_28_rxq_idx}, {rob_uop_1_27_rxq_idx}, {rob_uop_1_26_rxq_idx}, {rob_uop_1_25_rxq_idx}, {rob_uop_1_24_rxq_idx}, {rob_uop_1_23_rxq_idx}, {rob_uop_1_22_rxq_idx}, {rob_uop_1_21_rxq_idx}, {rob_uop_1_20_rxq_idx}, {rob_uop_1_19_rxq_idx}, {rob_uop_1_18_rxq_idx}, {rob_uop_1_17_rxq_idx}, {rob_uop_1_16_rxq_idx}, {rob_uop_1_15_rxq_idx}, {rob_uop_1_14_rxq_idx}, {rob_uop_1_13_rxq_idx}, {rob_uop_1_12_rxq_idx}, {rob_uop_1_11_rxq_idx}, {rob_uop_1_10_rxq_idx}, {rob_uop_1_9_rxq_idx}, {rob_uop_1_8_rxq_idx}, {rob_uop_1_7_rxq_idx}, {rob_uop_1_6_rxq_idx}, {rob_uop_1_5_rxq_idx}, {rob_uop_1_4_rxq_idx}, {rob_uop_1_3_rxq_idx}, {rob_uop_1_2_rxq_idx}, {rob_uop_1_1_rxq_idx}, {rob_uop_1_0_rxq_idx}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_rxq_idx = _GEN_202[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_203 = {{rob_uop_1_31_prs1}, {rob_uop_1_30_prs1}, {rob_uop_1_29_prs1}, {rob_uop_1_28_prs1}, {rob_uop_1_27_prs1}, {rob_uop_1_26_prs1}, {rob_uop_1_25_prs1}, {rob_uop_1_24_prs1}, {rob_uop_1_23_prs1}, {rob_uop_1_22_prs1}, {rob_uop_1_21_prs1}, {rob_uop_1_20_prs1}, {rob_uop_1_19_prs1}, {rob_uop_1_18_prs1}, {rob_uop_1_17_prs1}, {rob_uop_1_16_prs1}, {rob_uop_1_15_prs1}, {rob_uop_1_14_prs1}, {rob_uop_1_13_prs1}, {rob_uop_1_12_prs1}, {rob_uop_1_11_prs1}, {rob_uop_1_10_prs1}, {rob_uop_1_9_prs1}, {rob_uop_1_8_prs1}, {rob_uop_1_7_prs1}, {rob_uop_1_6_prs1}, {rob_uop_1_5_prs1}, {rob_uop_1_4_prs1}, {rob_uop_1_3_prs1}, {rob_uop_1_2_prs1}, {rob_uop_1_1_prs1}, {rob_uop_1_0_prs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs1 = _GEN_203[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_204 = {{rob_uop_1_31_prs2}, {rob_uop_1_30_prs2}, {rob_uop_1_29_prs2}, {rob_uop_1_28_prs2}, {rob_uop_1_27_prs2}, {rob_uop_1_26_prs2}, {rob_uop_1_25_prs2}, {rob_uop_1_24_prs2}, {rob_uop_1_23_prs2}, {rob_uop_1_22_prs2}, {rob_uop_1_21_prs2}, {rob_uop_1_20_prs2}, {rob_uop_1_19_prs2}, {rob_uop_1_18_prs2}, {rob_uop_1_17_prs2}, {rob_uop_1_16_prs2}, {rob_uop_1_15_prs2}, {rob_uop_1_14_prs2}, {rob_uop_1_13_prs2}, {rob_uop_1_12_prs2}, {rob_uop_1_11_prs2}, {rob_uop_1_10_prs2}, {rob_uop_1_9_prs2}, {rob_uop_1_8_prs2}, {rob_uop_1_7_prs2}, {rob_uop_1_6_prs2}, {rob_uop_1_5_prs2}, {rob_uop_1_4_prs2}, {rob_uop_1_3_prs2}, {rob_uop_1_2_prs2}, {rob_uop_1_1_prs2}, {rob_uop_1_0_prs2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs2 = _GEN_204[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][6:0] _GEN_205 = {{rob_uop_1_31_prs3}, {rob_uop_1_30_prs3}, {rob_uop_1_29_prs3}, {rob_uop_1_28_prs3}, {rob_uop_1_27_prs3}, {rob_uop_1_26_prs3}, {rob_uop_1_25_prs3}, {rob_uop_1_24_prs3}, {rob_uop_1_23_prs3}, {rob_uop_1_22_prs3}, {rob_uop_1_21_prs3}, {rob_uop_1_20_prs3}, {rob_uop_1_19_prs3}, {rob_uop_1_18_prs3}, {rob_uop_1_17_prs3}, {rob_uop_1_16_prs3}, {rob_uop_1_15_prs3}, {rob_uop_1_14_prs3}, {rob_uop_1_13_prs3}, {rob_uop_1_12_prs3}, {rob_uop_1_11_prs3}, {rob_uop_1_10_prs3}, {rob_uop_1_9_prs3}, {rob_uop_1_8_prs3}, {rob_uop_1_7_prs3}, {rob_uop_1_6_prs3}, {rob_uop_1_5_prs3}, {rob_uop_1_4_prs3}, {rob_uop_1_3_prs3}, {rob_uop_1_2_prs3}, {rob_uop_1_1_prs3}, {rob_uop_1_0_prs3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs3 = _GEN_205[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_206 = {{rob_uop_1_31_ppred}, {rob_uop_1_30_ppred}, {rob_uop_1_29_ppred}, {rob_uop_1_28_ppred}, {rob_uop_1_27_ppred}, {rob_uop_1_26_ppred}, {rob_uop_1_25_ppred}, {rob_uop_1_24_ppred}, {rob_uop_1_23_ppred}, {rob_uop_1_22_ppred}, {rob_uop_1_21_ppred}, {rob_uop_1_20_ppred}, {rob_uop_1_19_ppred}, {rob_uop_1_18_ppred}, {rob_uop_1_17_ppred}, {rob_uop_1_16_ppred}, {rob_uop_1_15_ppred}, {rob_uop_1_14_ppred}, {rob_uop_1_13_ppred}, {rob_uop_1_12_ppred}, {rob_uop_1_11_ppred}, {rob_uop_1_10_ppred}, {rob_uop_1_9_ppred}, {rob_uop_1_8_ppred}, {rob_uop_1_7_ppred}, {rob_uop_1_6_ppred}, {rob_uop_1_5_ppred}, {rob_uop_1_4_ppred}, {rob_uop_1_3_ppred}, {rob_uop_1_2_ppred}, {rob_uop_1_1_ppred}, {rob_uop_1_0_ppred}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_ppred = _GEN_206[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_207 = {{rob_uop_1_31_prs1_busy}, {rob_uop_1_30_prs1_busy}, {rob_uop_1_29_prs1_busy}, {rob_uop_1_28_prs1_busy}, {rob_uop_1_27_prs1_busy}, {rob_uop_1_26_prs1_busy}, {rob_uop_1_25_prs1_busy}, {rob_uop_1_24_prs1_busy}, {rob_uop_1_23_prs1_busy}, {rob_uop_1_22_prs1_busy}, {rob_uop_1_21_prs1_busy}, {rob_uop_1_20_prs1_busy}, {rob_uop_1_19_prs1_busy}, {rob_uop_1_18_prs1_busy}, {rob_uop_1_17_prs1_busy}, {rob_uop_1_16_prs1_busy}, {rob_uop_1_15_prs1_busy}, {rob_uop_1_14_prs1_busy}, {rob_uop_1_13_prs1_busy}, {rob_uop_1_12_prs1_busy}, {rob_uop_1_11_prs1_busy}, {rob_uop_1_10_prs1_busy}, {rob_uop_1_9_prs1_busy}, {rob_uop_1_8_prs1_busy}, {rob_uop_1_7_prs1_busy}, {rob_uop_1_6_prs1_busy}, {rob_uop_1_5_prs1_busy}, {rob_uop_1_4_prs1_busy}, {rob_uop_1_3_prs1_busy}, {rob_uop_1_2_prs1_busy}, {rob_uop_1_1_prs1_busy}, {rob_uop_1_0_prs1_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs1_busy = _GEN_207[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_208 = {{rob_uop_1_31_prs2_busy}, {rob_uop_1_30_prs2_busy}, {rob_uop_1_29_prs2_busy}, {rob_uop_1_28_prs2_busy}, {rob_uop_1_27_prs2_busy}, {rob_uop_1_26_prs2_busy}, {rob_uop_1_25_prs2_busy}, {rob_uop_1_24_prs2_busy}, {rob_uop_1_23_prs2_busy}, {rob_uop_1_22_prs2_busy}, {rob_uop_1_21_prs2_busy}, {rob_uop_1_20_prs2_busy}, {rob_uop_1_19_prs2_busy}, {rob_uop_1_18_prs2_busy}, {rob_uop_1_17_prs2_busy}, {rob_uop_1_16_prs2_busy}, {rob_uop_1_15_prs2_busy}, {rob_uop_1_14_prs2_busy}, {rob_uop_1_13_prs2_busy}, {rob_uop_1_12_prs2_busy}, {rob_uop_1_11_prs2_busy}, {rob_uop_1_10_prs2_busy}, {rob_uop_1_9_prs2_busy}, {rob_uop_1_8_prs2_busy}, {rob_uop_1_7_prs2_busy}, {rob_uop_1_6_prs2_busy}, {rob_uop_1_5_prs2_busy}, {rob_uop_1_4_prs2_busy}, {rob_uop_1_3_prs2_busy}, {rob_uop_1_2_prs2_busy}, {rob_uop_1_1_prs2_busy}, {rob_uop_1_0_prs2_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs2_busy = _GEN_208[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_209 = {{rob_uop_1_31_prs3_busy}, {rob_uop_1_30_prs3_busy}, {rob_uop_1_29_prs3_busy}, {rob_uop_1_28_prs3_busy}, {rob_uop_1_27_prs3_busy}, {rob_uop_1_26_prs3_busy}, {rob_uop_1_25_prs3_busy}, {rob_uop_1_24_prs3_busy}, {rob_uop_1_23_prs3_busy}, {rob_uop_1_22_prs3_busy}, {rob_uop_1_21_prs3_busy}, {rob_uop_1_20_prs3_busy}, {rob_uop_1_19_prs3_busy}, {rob_uop_1_18_prs3_busy}, {rob_uop_1_17_prs3_busy}, {rob_uop_1_16_prs3_busy}, {rob_uop_1_15_prs3_busy}, {rob_uop_1_14_prs3_busy}, {rob_uop_1_13_prs3_busy}, {rob_uop_1_12_prs3_busy}, {rob_uop_1_11_prs3_busy}, {rob_uop_1_10_prs3_busy}, {rob_uop_1_9_prs3_busy}, {rob_uop_1_8_prs3_busy}, {rob_uop_1_7_prs3_busy}, {rob_uop_1_6_prs3_busy}, {rob_uop_1_5_prs3_busy}, {rob_uop_1_4_prs3_busy}, {rob_uop_1_3_prs3_busy}, {rob_uop_1_2_prs3_busy}, {rob_uop_1_1_prs3_busy}, {rob_uop_1_0_prs3_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_prs3_busy = _GEN_209[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_210 = {{rob_uop_1_31_ppred_busy}, {rob_uop_1_30_ppred_busy}, {rob_uop_1_29_ppred_busy}, {rob_uop_1_28_ppred_busy}, {rob_uop_1_27_ppred_busy}, {rob_uop_1_26_ppred_busy}, {rob_uop_1_25_ppred_busy}, {rob_uop_1_24_ppred_busy}, {rob_uop_1_23_ppred_busy}, {rob_uop_1_22_ppred_busy}, {rob_uop_1_21_ppred_busy}, {rob_uop_1_20_ppred_busy}, {rob_uop_1_19_ppred_busy}, {rob_uop_1_18_ppred_busy}, {rob_uop_1_17_ppred_busy}, {rob_uop_1_16_ppred_busy}, {rob_uop_1_15_ppred_busy}, {rob_uop_1_14_ppred_busy}, {rob_uop_1_13_ppred_busy}, {rob_uop_1_12_ppred_busy}, {rob_uop_1_11_ppred_busy}, {rob_uop_1_10_ppred_busy}, {rob_uop_1_9_ppred_busy}, {rob_uop_1_8_ppred_busy}, {rob_uop_1_7_ppred_busy}, {rob_uop_1_6_ppred_busy}, {rob_uop_1_5_ppred_busy}, {rob_uop_1_4_ppred_busy}, {rob_uop_1_3_ppred_busy}, {rob_uop_1_2_ppred_busy}, {rob_uop_1_1_ppred_busy}, {rob_uop_1_0_ppred_busy}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_ppred_busy = _GEN_210[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_211 = {{rob_uop_1_31_exception}, {rob_uop_1_30_exception}, {rob_uop_1_29_exception}, {rob_uop_1_28_exception}, {rob_uop_1_27_exception}, {rob_uop_1_26_exception}, {rob_uop_1_25_exception}, {rob_uop_1_24_exception}, {rob_uop_1_23_exception}, {rob_uop_1_22_exception}, {rob_uop_1_21_exception}, {rob_uop_1_20_exception}, {rob_uop_1_19_exception}, {rob_uop_1_18_exception}, {rob_uop_1_17_exception}, {rob_uop_1_16_exception}, {rob_uop_1_15_exception}, {rob_uop_1_14_exception}, {rob_uop_1_13_exception}, {rob_uop_1_12_exception}, {rob_uop_1_11_exception}, {rob_uop_1_10_exception}, {rob_uop_1_9_exception}, {rob_uop_1_8_exception}, {rob_uop_1_7_exception}, {rob_uop_1_6_exception}, {rob_uop_1_5_exception}, {rob_uop_1_4_exception}, {rob_uop_1_3_exception}, {rob_uop_1_2_exception}, {rob_uop_1_1_exception}, {rob_uop_1_0_exception}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_exception = _GEN_211[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][63:0] _GEN_212 = {{rob_uop_1_31_exc_cause}, {rob_uop_1_30_exc_cause}, {rob_uop_1_29_exc_cause}, {rob_uop_1_28_exc_cause}, {rob_uop_1_27_exc_cause}, {rob_uop_1_26_exc_cause}, {rob_uop_1_25_exc_cause}, {rob_uop_1_24_exc_cause}, {rob_uop_1_23_exc_cause}, {rob_uop_1_22_exc_cause}, {rob_uop_1_21_exc_cause}, {rob_uop_1_20_exc_cause}, {rob_uop_1_19_exc_cause}, {rob_uop_1_18_exc_cause}, {rob_uop_1_17_exc_cause}, {rob_uop_1_16_exc_cause}, {rob_uop_1_15_exc_cause}, {rob_uop_1_14_exc_cause}, {rob_uop_1_13_exc_cause}, {rob_uop_1_12_exc_cause}, {rob_uop_1_11_exc_cause}, {rob_uop_1_10_exc_cause}, {rob_uop_1_9_exc_cause}, {rob_uop_1_8_exc_cause}, {rob_uop_1_7_exc_cause}, {rob_uop_1_6_exc_cause}, {rob_uop_1_5_exc_cause}, {rob_uop_1_4_exc_cause}, {rob_uop_1_3_exc_cause}, {rob_uop_1_2_exc_cause}, {rob_uop_1_1_exc_cause}, {rob_uop_1_0_exc_cause}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_exc_cause = _GEN_212[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_213 = {{rob_uop_1_31_mem_cmd}, {rob_uop_1_30_mem_cmd}, {rob_uop_1_29_mem_cmd}, {rob_uop_1_28_mem_cmd}, {rob_uop_1_27_mem_cmd}, {rob_uop_1_26_mem_cmd}, {rob_uop_1_25_mem_cmd}, {rob_uop_1_24_mem_cmd}, {rob_uop_1_23_mem_cmd}, {rob_uop_1_22_mem_cmd}, {rob_uop_1_21_mem_cmd}, {rob_uop_1_20_mem_cmd}, {rob_uop_1_19_mem_cmd}, {rob_uop_1_18_mem_cmd}, {rob_uop_1_17_mem_cmd}, {rob_uop_1_16_mem_cmd}, {rob_uop_1_15_mem_cmd}, {rob_uop_1_14_mem_cmd}, {rob_uop_1_13_mem_cmd}, {rob_uop_1_12_mem_cmd}, {rob_uop_1_11_mem_cmd}, {rob_uop_1_10_mem_cmd}, {rob_uop_1_9_mem_cmd}, {rob_uop_1_8_mem_cmd}, {rob_uop_1_7_mem_cmd}, {rob_uop_1_6_mem_cmd}, {rob_uop_1_5_mem_cmd}, {rob_uop_1_4_mem_cmd}, {rob_uop_1_3_mem_cmd}, {rob_uop_1_2_mem_cmd}, {rob_uop_1_1_mem_cmd}, {rob_uop_1_0_mem_cmd}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_mem_cmd = _GEN_213[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_214 = {{rob_uop_1_31_mem_size}, {rob_uop_1_30_mem_size}, {rob_uop_1_29_mem_size}, {rob_uop_1_28_mem_size}, {rob_uop_1_27_mem_size}, {rob_uop_1_26_mem_size}, {rob_uop_1_25_mem_size}, {rob_uop_1_24_mem_size}, {rob_uop_1_23_mem_size}, {rob_uop_1_22_mem_size}, {rob_uop_1_21_mem_size}, {rob_uop_1_20_mem_size}, {rob_uop_1_19_mem_size}, {rob_uop_1_18_mem_size}, {rob_uop_1_17_mem_size}, {rob_uop_1_16_mem_size}, {rob_uop_1_15_mem_size}, {rob_uop_1_14_mem_size}, {rob_uop_1_13_mem_size}, {rob_uop_1_12_mem_size}, {rob_uop_1_11_mem_size}, {rob_uop_1_10_mem_size}, {rob_uop_1_9_mem_size}, {rob_uop_1_8_mem_size}, {rob_uop_1_7_mem_size}, {rob_uop_1_6_mem_size}, {rob_uop_1_5_mem_size}, {rob_uop_1_4_mem_size}, {rob_uop_1_3_mem_size}, {rob_uop_1_2_mem_size}, {rob_uop_1_1_mem_size}, {rob_uop_1_0_mem_size}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_mem_size = _GEN_214[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_215 = {{rob_uop_1_31_mem_signed}, {rob_uop_1_30_mem_signed}, {rob_uop_1_29_mem_signed}, {rob_uop_1_28_mem_signed}, {rob_uop_1_27_mem_signed}, {rob_uop_1_26_mem_signed}, {rob_uop_1_25_mem_signed}, {rob_uop_1_24_mem_signed}, {rob_uop_1_23_mem_signed}, {rob_uop_1_22_mem_signed}, {rob_uop_1_21_mem_signed}, {rob_uop_1_20_mem_signed}, {rob_uop_1_19_mem_signed}, {rob_uop_1_18_mem_signed}, {rob_uop_1_17_mem_signed}, {rob_uop_1_16_mem_signed}, {rob_uop_1_15_mem_signed}, {rob_uop_1_14_mem_signed}, {rob_uop_1_13_mem_signed}, {rob_uop_1_12_mem_signed}, {rob_uop_1_11_mem_signed}, {rob_uop_1_10_mem_signed}, {rob_uop_1_9_mem_signed}, {rob_uop_1_8_mem_signed}, {rob_uop_1_7_mem_signed}, {rob_uop_1_6_mem_signed}, {rob_uop_1_5_mem_signed}, {rob_uop_1_4_mem_signed}, {rob_uop_1_3_mem_signed}, {rob_uop_1_2_mem_signed}, {rob_uop_1_1_mem_signed}, {rob_uop_1_0_mem_signed}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_mem_signed = _GEN_215[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_216 = {{rob_uop_1_31_is_unique}, {rob_uop_1_30_is_unique}, {rob_uop_1_29_is_unique}, {rob_uop_1_28_is_unique}, {rob_uop_1_27_is_unique}, {rob_uop_1_26_is_unique}, {rob_uop_1_25_is_unique}, {rob_uop_1_24_is_unique}, {rob_uop_1_23_is_unique}, {rob_uop_1_22_is_unique}, {rob_uop_1_21_is_unique}, {rob_uop_1_20_is_unique}, {rob_uop_1_19_is_unique}, {rob_uop_1_18_is_unique}, {rob_uop_1_17_is_unique}, {rob_uop_1_16_is_unique}, {rob_uop_1_15_is_unique}, {rob_uop_1_14_is_unique}, {rob_uop_1_13_is_unique}, {rob_uop_1_12_is_unique}, {rob_uop_1_11_is_unique}, {rob_uop_1_10_is_unique}, {rob_uop_1_9_is_unique}, {rob_uop_1_8_is_unique}, {rob_uop_1_7_is_unique}, {rob_uop_1_6_is_unique}, {rob_uop_1_5_is_unique}, {rob_uop_1_4_is_unique}, {rob_uop_1_3_is_unique}, {rob_uop_1_2_is_unique}, {rob_uop_1_1_is_unique}, {rob_uop_1_0_is_unique}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_is_unique = _GEN_216[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_217 = {{rob_uop_1_31_flush_on_commit}, {rob_uop_1_30_flush_on_commit}, {rob_uop_1_29_flush_on_commit}, {rob_uop_1_28_flush_on_commit}, {rob_uop_1_27_flush_on_commit}, {rob_uop_1_26_flush_on_commit}, {rob_uop_1_25_flush_on_commit}, {rob_uop_1_24_flush_on_commit}, {rob_uop_1_23_flush_on_commit}, {rob_uop_1_22_flush_on_commit}, {rob_uop_1_21_flush_on_commit}, {rob_uop_1_20_flush_on_commit}, {rob_uop_1_19_flush_on_commit}, {rob_uop_1_18_flush_on_commit}, {rob_uop_1_17_flush_on_commit}, {rob_uop_1_16_flush_on_commit}, {rob_uop_1_15_flush_on_commit}, {rob_uop_1_14_flush_on_commit}, {rob_uop_1_13_flush_on_commit}, {rob_uop_1_12_flush_on_commit}, {rob_uop_1_11_flush_on_commit}, {rob_uop_1_10_flush_on_commit}, {rob_uop_1_9_flush_on_commit}, {rob_uop_1_8_flush_on_commit}, {rob_uop_1_7_flush_on_commit}, {rob_uop_1_6_flush_on_commit}, {rob_uop_1_5_flush_on_commit}, {rob_uop_1_4_flush_on_commit}, {rob_uop_1_3_flush_on_commit}, {rob_uop_1_2_flush_on_commit}, {rob_uop_1_1_flush_on_commit}, {rob_uop_1_0_flush_on_commit}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_flush_on_commit = _GEN_217[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_218 = {{rob_uop_1_31_csr_cmd}, {rob_uop_1_30_csr_cmd}, {rob_uop_1_29_csr_cmd}, {rob_uop_1_28_csr_cmd}, {rob_uop_1_27_csr_cmd}, {rob_uop_1_26_csr_cmd}, {rob_uop_1_25_csr_cmd}, {rob_uop_1_24_csr_cmd}, {rob_uop_1_23_csr_cmd}, {rob_uop_1_22_csr_cmd}, {rob_uop_1_21_csr_cmd}, {rob_uop_1_20_csr_cmd}, {rob_uop_1_19_csr_cmd}, {rob_uop_1_18_csr_cmd}, {rob_uop_1_17_csr_cmd}, {rob_uop_1_16_csr_cmd}, {rob_uop_1_15_csr_cmd}, {rob_uop_1_14_csr_cmd}, {rob_uop_1_13_csr_cmd}, {rob_uop_1_12_csr_cmd}, {rob_uop_1_11_csr_cmd}, {rob_uop_1_10_csr_cmd}, {rob_uop_1_9_csr_cmd}, {rob_uop_1_8_csr_cmd}, {rob_uop_1_7_csr_cmd}, {rob_uop_1_6_csr_cmd}, {rob_uop_1_5_csr_cmd}, {rob_uop_1_4_csr_cmd}, {rob_uop_1_3_csr_cmd}, {rob_uop_1_2_csr_cmd}, {rob_uop_1_1_csr_cmd}, {rob_uop_1_0_csr_cmd}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_csr_cmd = _GEN_218[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_219 = {{rob_uop_1_31_ldst_is_rs1}, {rob_uop_1_30_ldst_is_rs1}, {rob_uop_1_29_ldst_is_rs1}, {rob_uop_1_28_ldst_is_rs1}, {rob_uop_1_27_ldst_is_rs1}, {rob_uop_1_26_ldst_is_rs1}, {rob_uop_1_25_ldst_is_rs1}, {rob_uop_1_24_ldst_is_rs1}, {rob_uop_1_23_ldst_is_rs1}, {rob_uop_1_22_ldst_is_rs1}, {rob_uop_1_21_ldst_is_rs1}, {rob_uop_1_20_ldst_is_rs1}, {rob_uop_1_19_ldst_is_rs1}, {rob_uop_1_18_ldst_is_rs1}, {rob_uop_1_17_ldst_is_rs1}, {rob_uop_1_16_ldst_is_rs1}, {rob_uop_1_15_ldst_is_rs1}, {rob_uop_1_14_ldst_is_rs1}, {rob_uop_1_13_ldst_is_rs1}, {rob_uop_1_12_ldst_is_rs1}, {rob_uop_1_11_ldst_is_rs1}, {rob_uop_1_10_ldst_is_rs1}, {rob_uop_1_9_ldst_is_rs1}, {rob_uop_1_8_ldst_is_rs1}, {rob_uop_1_7_ldst_is_rs1}, {rob_uop_1_6_ldst_is_rs1}, {rob_uop_1_5_ldst_is_rs1}, {rob_uop_1_4_ldst_is_rs1}, {rob_uop_1_3_ldst_is_rs1}, {rob_uop_1_2_ldst_is_rs1}, {rob_uop_1_1_ldst_is_rs1}, {rob_uop_1_0_ldst_is_rs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_ldst_is_rs1 = _GEN_219[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_220 = {{rob_uop_1_31_lrs1}, {rob_uop_1_30_lrs1}, {rob_uop_1_29_lrs1}, {rob_uop_1_28_lrs1}, {rob_uop_1_27_lrs1}, {rob_uop_1_26_lrs1}, {rob_uop_1_25_lrs1}, {rob_uop_1_24_lrs1}, {rob_uop_1_23_lrs1}, {rob_uop_1_22_lrs1}, {rob_uop_1_21_lrs1}, {rob_uop_1_20_lrs1}, {rob_uop_1_19_lrs1}, {rob_uop_1_18_lrs1}, {rob_uop_1_17_lrs1}, {rob_uop_1_16_lrs1}, {rob_uop_1_15_lrs1}, {rob_uop_1_14_lrs1}, {rob_uop_1_13_lrs1}, {rob_uop_1_12_lrs1}, {rob_uop_1_11_lrs1}, {rob_uop_1_10_lrs1}, {rob_uop_1_9_lrs1}, {rob_uop_1_8_lrs1}, {rob_uop_1_7_lrs1}, {rob_uop_1_6_lrs1}, {rob_uop_1_5_lrs1}, {rob_uop_1_4_lrs1}, {rob_uop_1_3_lrs1}, {rob_uop_1_2_lrs1}, {rob_uop_1_1_lrs1}, {rob_uop_1_0_lrs1}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_lrs1 = _GEN_220[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_221 = {{rob_uop_1_31_lrs2}, {rob_uop_1_30_lrs2}, {rob_uop_1_29_lrs2}, {rob_uop_1_28_lrs2}, {rob_uop_1_27_lrs2}, {rob_uop_1_26_lrs2}, {rob_uop_1_25_lrs2}, {rob_uop_1_24_lrs2}, {rob_uop_1_23_lrs2}, {rob_uop_1_22_lrs2}, {rob_uop_1_21_lrs2}, {rob_uop_1_20_lrs2}, {rob_uop_1_19_lrs2}, {rob_uop_1_18_lrs2}, {rob_uop_1_17_lrs2}, {rob_uop_1_16_lrs2}, {rob_uop_1_15_lrs2}, {rob_uop_1_14_lrs2}, {rob_uop_1_13_lrs2}, {rob_uop_1_12_lrs2}, {rob_uop_1_11_lrs2}, {rob_uop_1_10_lrs2}, {rob_uop_1_9_lrs2}, {rob_uop_1_8_lrs2}, {rob_uop_1_7_lrs2}, {rob_uop_1_6_lrs2}, {rob_uop_1_5_lrs2}, {rob_uop_1_4_lrs2}, {rob_uop_1_3_lrs2}, {rob_uop_1_2_lrs2}, {rob_uop_1_1_lrs2}, {rob_uop_1_0_lrs2}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_lrs2 = _GEN_221[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][5:0] _GEN_222 = {{rob_uop_1_31_lrs3}, {rob_uop_1_30_lrs3}, {rob_uop_1_29_lrs3}, {rob_uop_1_28_lrs3}, {rob_uop_1_27_lrs3}, {rob_uop_1_26_lrs3}, {rob_uop_1_25_lrs3}, {rob_uop_1_24_lrs3}, {rob_uop_1_23_lrs3}, {rob_uop_1_22_lrs3}, {rob_uop_1_21_lrs3}, {rob_uop_1_20_lrs3}, {rob_uop_1_19_lrs3}, {rob_uop_1_18_lrs3}, {rob_uop_1_17_lrs3}, {rob_uop_1_16_lrs3}, {rob_uop_1_15_lrs3}, {rob_uop_1_14_lrs3}, {rob_uop_1_13_lrs3}, {rob_uop_1_12_lrs3}, {rob_uop_1_11_lrs3}, {rob_uop_1_10_lrs3}, {rob_uop_1_9_lrs3}, {rob_uop_1_8_lrs3}, {rob_uop_1_7_lrs3}, {rob_uop_1_6_lrs3}, {rob_uop_1_5_lrs3}, {rob_uop_1_4_lrs3}, {rob_uop_1_3_lrs3}, {rob_uop_1_2_lrs3}, {rob_uop_1_1_lrs3}, {rob_uop_1_0_lrs3}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_lrs3 = _GEN_222[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_223 = {{rob_uop_1_31_lrs1_rtype}, {rob_uop_1_30_lrs1_rtype}, {rob_uop_1_29_lrs1_rtype}, {rob_uop_1_28_lrs1_rtype}, {rob_uop_1_27_lrs1_rtype}, {rob_uop_1_26_lrs1_rtype}, {rob_uop_1_25_lrs1_rtype}, {rob_uop_1_24_lrs1_rtype}, {rob_uop_1_23_lrs1_rtype}, {rob_uop_1_22_lrs1_rtype}, {rob_uop_1_21_lrs1_rtype}, {rob_uop_1_20_lrs1_rtype}, {rob_uop_1_19_lrs1_rtype}, {rob_uop_1_18_lrs1_rtype}, {rob_uop_1_17_lrs1_rtype}, {rob_uop_1_16_lrs1_rtype}, {rob_uop_1_15_lrs1_rtype}, {rob_uop_1_14_lrs1_rtype}, {rob_uop_1_13_lrs1_rtype}, {rob_uop_1_12_lrs1_rtype}, {rob_uop_1_11_lrs1_rtype}, {rob_uop_1_10_lrs1_rtype}, {rob_uop_1_9_lrs1_rtype}, {rob_uop_1_8_lrs1_rtype}, {rob_uop_1_7_lrs1_rtype}, {rob_uop_1_6_lrs1_rtype}, {rob_uop_1_5_lrs1_rtype}, {rob_uop_1_4_lrs1_rtype}, {rob_uop_1_3_lrs1_rtype}, {rob_uop_1_2_lrs1_rtype}, {rob_uop_1_1_lrs1_rtype}, {rob_uop_1_0_lrs1_rtype}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_lrs1_rtype = _GEN_223[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_224 = {{rob_uop_1_31_lrs2_rtype}, {rob_uop_1_30_lrs2_rtype}, {rob_uop_1_29_lrs2_rtype}, {rob_uop_1_28_lrs2_rtype}, {rob_uop_1_27_lrs2_rtype}, {rob_uop_1_26_lrs2_rtype}, {rob_uop_1_25_lrs2_rtype}, {rob_uop_1_24_lrs2_rtype}, {rob_uop_1_23_lrs2_rtype}, {rob_uop_1_22_lrs2_rtype}, {rob_uop_1_21_lrs2_rtype}, {rob_uop_1_20_lrs2_rtype}, {rob_uop_1_19_lrs2_rtype}, {rob_uop_1_18_lrs2_rtype}, {rob_uop_1_17_lrs2_rtype}, {rob_uop_1_16_lrs2_rtype}, {rob_uop_1_15_lrs2_rtype}, {rob_uop_1_14_lrs2_rtype}, {rob_uop_1_13_lrs2_rtype}, {rob_uop_1_12_lrs2_rtype}, {rob_uop_1_11_lrs2_rtype}, {rob_uop_1_10_lrs2_rtype}, {rob_uop_1_9_lrs2_rtype}, {rob_uop_1_8_lrs2_rtype}, {rob_uop_1_7_lrs2_rtype}, {rob_uop_1_6_lrs2_rtype}, {rob_uop_1_5_lrs2_rtype}, {rob_uop_1_4_lrs2_rtype}, {rob_uop_1_3_lrs2_rtype}, {rob_uop_1_2_lrs2_rtype}, {rob_uop_1_1_lrs2_rtype}, {rob_uop_1_0_lrs2_rtype}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_lrs2_rtype = _GEN_224[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_225 = {{rob_uop_1_31_frs3_en}, {rob_uop_1_30_frs3_en}, {rob_uop_1_29_frs3_en}, {rob_uop_1_28_frs3_en}, {rob_uop_1_27_frs3_en}, {rob_uop_1_26_frs3_en}, {rob_uop_1_25_frs3_en}, {rob_uop_1_24_frs3_en}, {rob_uop_1_23_frs3_en}, {rob_uop_1_22_frs3_en}, {rob_uop_1_21_frs3_en}, {rob_uop_1_20_frs3_en}, {rob_uop_1_19_frs3_en}, {rob_uop_1_18_frs3_en}, {rob_uop_1_17_frs3_en}, {rob_uop_1_16_frs3_en}, {rob_uop_1_15_frs3_en}, {rob_uop_1_14_frs3_en}, {rob_uop_1_13_frs3_en}, {rob_uop_1_12_frs3_en}, {rob_uop_1_11_frs3_en}, {rob_uop_1_10_frs3_en}, {rob_uop_1_9_frs3_en}, {rob_uop_1_8_frs3_en}, {rob_uop_1_7_frs3_en}, {rob_uop_1_6_frs3_en}, {rob_uop_1_5_frs3_en}, {rob_uop_1_4_frs3_en}, {rob_uop_1_3_frs3_en}, {rob_uop_1_2_frs3_en}, {rob_uop_1_1_frs3_en}, {rob_uop_1_0_frs3_en}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_frs3_en = _GEN_225[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_226 = {{rob_uop_1_31_fcn_dw}, {rob_uop_1_30_fcn_dw}, {rob_uop_1_29_fcn_dw}, {rob_uop_1_28_fcn_dw}, {rob_uop_1_27_fcn_dw}, {rob_uop_1_26_fcn_dw}, {rob_uop_1_25_fcn_dw}, {rob_uop_1_24_fcn_dw}, {rob_uop_1_23_fcn_dw}, {rob_uop_1_22_fcn_dw}, {rob_uop_1_21_fcn_dw}, {rob_uop_1_20_fcn_dw}, {rob_uop_1_19_fcn_dw}, {rob_uop_1_18_fcn_dw}, {rob_uop_1_17_fcn_dw}, {rob_uop_1_16_fcn_dw}, {rob_uop_1_15_fcn_dw}, {rob_uop_1_14_fcn_dw}, {rob_uop_1_13_fcn_dw}, {rob_uop_1_12_fcn_dw}, {rob_uop_1_11_fcn_dw}, {rob_uop_1_10_fcn_dw}, {rob_uop_1_9_fcn_dw}, {rob_uop_1_8_fcn_dw}, {rob_uop_1_7_fcn_dw}, {rob_uop_1_6_fcn_dw}, {rob_uop_1_5_fcn_dw}, {rob_uop_1_4_fcn_dw}, {rob_uop_1_3_fcn_dw}, {rob_uop_1_2_fcn_dw}, {rob_uop_1_1_fcn_dw}, {rob_uop_1_0_fcn_dw}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fcn_dw = _GEN_226[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][4:0] _GEN_227 = {{rob_uop_1_31_fcn_op}, {rob_uop_1_30_fcn_op}, {rob_uop_1_29_fcn_op}, {rob_uop_1_28_fcn_op}, {rob_uop_1_27_fcn_op}, {rob_uop_1_26_fcn_op}, {rob_uop_1_25_fcn_op}, {rob_uop_1_24_fcn_op}, {rob_uop_1_23_fcn_op}, {rob_uop_1_22_fcn_op}, {rob_uop_1_21_fcn_op}, {rob_uop_1_20_fcn_op}, {rob_uop_1_19_fcn_op}, {rob_uop_1_18_fcn_op}, {rob_uop_1_17_fcn_op}, {rob_uop_1_16_fcn_op}, {rob_uop_1_15_fcn_op}, {rob_uop_1_14_fcn_op}, {rob_uop_1_13_fcn_op}, {rob_uop_1_12_fcn_op}, {rob_uop_1_11_fcn_op}, {rob_uop_1_10_fcn_op}, {rob_uop_1_9_fcn_op}, {rob_uop_1_8_fcn_op}, {rob_uop_1_7_fcn_op}, {rob_uop_1_6_fcn_op}, {rob_uop_1_5_fcn_op}, {rob_uop_1_4_fcn_op}, {rob_uop_1_3_fcn_op}, {rob_uop_1_2_fcn_op}, {rob_uop_1_1_fcn_op}, {rob_uop_1_0_fcn_op}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fcn_op = _GEN_227[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_228 = {{rob_uop_1_31_fp_val}, {rob_uop_1_30_fp_val}, {rob_uop_1_29_fp_val}, {rob_uop_1_28_fp_val}, {rob_uop_1_27_fp_val}, {rob_uop_1_26_fp_val}, {rob_uop_1_25_fp_val}, {rob_uop_1_24_fp_val}, {rob_uop_1_23_fp_val}, {rob_uop_1_22_fp_val}, {rob_uop_1_21_fp_val}, {rob_uop_1_20_fp_val}, {rob_uop_1_19_fp_val}, {rob_uop_1_18_fp_val}, {rob_uop_1_17_fp_val}, {rob_uop_1_16_fp_val}, {rob_uop_1_15_fp_val}, {rob_uop_1_14_fp_val}, {rob_uop_1_13_fp_val}, {rob_uop_1_12_fp_val}, {rob_uop_1_11_fp_val}, {rob_uop_1_10_fp_val}, {rob_uop_1_9_fp_val}, {rob_uop_1_8_fp_val}, {rob_uop_1_7_fp_val}, {rob_uop_1_6_fp_val}, {rob_uop_1_5_fp_val}, {rob_uop_1_4_fp_val}, {rob_uop_1_3_fp_val}, {rob_uop_1_2_fp_val}, {rob_uop_1_1_fp_val}, {rob_uop_1_0_fp_val}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_val = _GEN_228[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_229 = {{rob_uop_1_31_fp_rm}, {rob_uop_1_30_fp_rm}, {rob_uop_1_29_fp_rm}, {rob_uop_1_28_fp_rm}, {rob_uop_1_27_fp_rm}, {rob_uop_1_26_fp_rm}, {rob_uop_1_25_fp_rm}, {rob_uop_1_24_fp_rm}, {rob_uop_1_23_fp_rm}, {rob_uop_1_22_fp_rm}, {rob_uop_1_21_fp_rm}, {rob_uop_1_20_fp_rm}, {rob_uop_1_19_fp_rm}, {rob_uop_1_18_fp_rm}, {rob_uop_1_17_fp_rm}, {rob_uop_1_16_fp_rm}, {rob_uop_1_15_fp_rm}, {rob_uop_1_14_fp_rm}, {rob_uop_1_13_fp_rm}, {rob_uop_1_12_fp_rm}, {rob_uop_1_11_fp_rm}, {rob_uop_1_10_fp_rm}, {rob_uop_1_9_fp_rm}, {rob_uop_1_8_fp_rm}, {rob_uop_1_7_fp_rm}, {rob_uop_1_6_fp_rm}, {rob_uop_1_5_fp_rm}, {rob_uop_1_4_fp_rm}, {rob_uop_1_3_fp_rm}, {rob_uop_1_2_fp_rm}, {rob_uop_1_1_fp_rm}, {rob_uop_1_0_fp_rm}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_rm = _GEN_229[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][1:0] _GEN_230 = {{rob_uop_1_31_fp_typ}, {rob_uop_1_30_fp_typ}, {rob_uop_1_29_fp_typ}, {rob_uop_1_28_fp_typ}, {rob_uop_1_27_fp_typ}, {rob_uop_1_26_fp_typ}, {rob_uop_1_25_fp_typ}, {rob_uop_1_24_fp_typ}, {rob_uop_1_23_fp_typ}, {rob_uop_1_22_fp_typ}, {rob_uop_1_21_fp_typ}, {rob_uop_1_20_fp_typ}, {rob_uop_1_19_fp_typ}, {rob_uop_1_18_fp_typ}, {rob_uop_1_17_fp_typ}, {rob_uop_1_16_fp_typ}, {rob_uop_1_15_fp_typ}, {rob_uop_1_14_fp_typ}, {rob_uop_1_13_fp_typ}, {rob_uop_1_12_fp_typ}, {rob_uop_1_11_fp_typ}, {rob_uop_1_10_fp_typ}, {rob_uop_1_9_fp_typ}, {rob_uop_1_8_fp_typ}, {rob_uop_1_7_fp_typ}, {rob_uop_1_6_fp_typ}, {rob_uop_1_5_fp_typ}, {rob_uop_1_4_fp_typ}, {rob_uop_1_3_fp_typ}, {rob_uop_1_2_fp_typ}, {rob_uop_1_1_fp_typ}, {rob_uop_1_0_fp_typ}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_fp_typ = _GEN_230[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_231 = {{rob_uop_1_31_xcpt_pf_if}, {rob_uop_1_30_xcpt_pf_if}, {rob_uop_1_29_xcpt_pf_if}, {rob_uop_1_28_xcpt_pf_if}, {rob_uop_1_27_xcpt_pf_if}, {rob_uop_1_26_xcpt_pf_if}, {rob_uop_1_25_xcpt_pf_if}, {rob_uop_1_24_xcpt_pf_if}, {rob_uop_1_23_xcpt_pf_if}, {rob_uop_1_22_xcpt_pf_if}, {rob_uop_1_21_xcpt_pf_if}, {rob_uop_1_20_xcpt_pf_if}, {rob_uop_1_19_xcpt_pf_if}, {rob_uop_1_18_xcpt_pf_if}, {rob_uop_1_17_xcpt_pf_if}, {rob_uop_1_16_xcpt_pf_if}, {rob_uop_1_15_xcpt_pf_if}, {rob_uop_1_14_xcpt_pf_if}, {rob_uop_1_13_xcpt_pf_if}, {rob_uop_1_12_xcpt_pf_if}, {rob_uop_1_11_xcpt_pf_if}, {rob_uop_1_10_xcpt_pf_if}, {rob_uop_1_9_xcpt_pf_if}, {rob_uop_1_8_xcpt_pf_if}, {rob_uop_1_7_xcpt_pf_if}, {rob_uop_1_6_xcpt_pf_if}, {rob_uop_1_5_xcpt_pf_if}, {rob_uop_1_4_xcpt_pf_if}, {rob_uop_1_3_xcpt_pf_if}, {rob_uop_1_2_xcpt_pf_if}, {rob_uop_1_1_xcpt_pf_if}, {rob_uop_1_0_xcpt_pf_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_xcpt_pf_if = _GEN_231[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_232 = {{rob_uop_1_31_xcpt_ae_if}, {rob_uop_1_30_xcpt_ae_if}, {rob_uop_1_29_xcpt_ae_if}, {rob_uop_1_28_xcpt_ae_if}, {rob_uop_1_27_xcpt_ae_if}, {rob_uop_1_26_xcpt_ae_if}, {rob_uop_1_25_xcpt_ae_if}, {rob_uop_1_24_xcpt_ae_if}, {rob_uop_1_23_xcpt_ae_if}, {rob_uop_1_22_xcpt_ae_if}, {rob_uop_1_21_xcpt_ae_if}, {rob_uop_1_20_xcpt_ae_if}, {rob_uop_1_19_xcpt_ae_if}, {rob_uop_1_18_xcpt_ae_if}, {rob_uop_1_17_xcpt_ae_if}, {rob_uop_1_16_xcpt_ae_if}, {rob_uop_1_15_xcpt_ae_if}, {rob_uop_1_14_xcpt_ae_if}, {rob_uop_1_13_xcpt_ae_if}, {rob_uop_1_12_xcpt_ae_if}, {rob_uop_1_11_xcpt_ae_if}, {rob_uop_1_10_xcpt_ae_if}, {rob_uop_1_9_xcpt_ae_if}, {rob_uop_1_8_xcpt_ae_if}, {rob_uop_1_7_xcpt_ae_if}, {rob_uop_1_6_xcpt_ae_if}, {rob_uop_1_5_xcpt_ae_if}, {rob_uop_1_4_xcpt_ae_if}, {rob_uop_1_3_xcpt_ae_if}, {rob_uop_1_2_xcpt_ae_if}, {rob_uop_1_1_xcpt_ae_if}, {rob_uop_1_0_xcpt_ae_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_xcpt_ae_if = _GEN_232[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_233 = {{rob_uop_1_31_xcpt_ma_if}, {rob_uop_1_30_xcpt_ma_if}, {rob_uop_1_29_xcpt_ma_if}, {rob_uop_1_28_xcpt_ma_if}, {rob_uop_1_27_xcpt_ma_if}, {rob_uop_1_26_xcpt_ma_if}, {rob_uop_1_25_xcpt_ma_if}, {rob_uop_1_24_xcpt_ma_if}, {rob_uop_1_23_xcpt_ma_if}, {rob_uop_1_22_xcpt_ma_if}, {rob_uop_1_21_xcpt_ma_if}, {rob_uop_1_20_xcpt_ma_if}, {rob_uop_1_19_xcpt_ma_if}, {rob_uop_1_18_xcpt_ma_if}, {rob_uop_1_17_xcpt_ma_if}, {rob_uop_1_16_xcpt_ma_if}, {rob_uop_1_15_xcpt_ma_if}, {rob_uop_1_14_xcpt_ma_if}, {rob_uop_1_13_xcpt_ma_if}, {rob_uop_1_12_xcpt_ma_if}, {rob_uop_1_11_xcpt_ma_if}, {rob_uop_1_10_xcpt_ma_if}, {rob_uop_1_9_xcpt_ma_if}, {rob_uop_1_8_xcpt_ma_if}, {rob_uop_1_7_xcpt_ma_if}, {rob_uop_1_6_xcpt_ma_if}, {rob_uop_1_5_xcpt_ma_if}, {rob_uop_1_4_xcpt_ma_if}, {rob_uop_1_3_xcpt_ma_if}, {rob_uop_1_2_xcpt_ma_if}, {rob_uop_1_1_xcpt_ma_if}, {rob_uop_1_0_xcpt_ma_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_xcpt_ma_if = _GEN_233[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_234 = {{rob_uop_1_31_bp_debug_if}, {rob_uop_1_30_bp_debug_if}, {rob_uop_1_29_bp_debug_if}, {rob_uop_1_28_bp_debug_if}, {rob_uop_1_27_bp_debug_if}, {rob_uop_1_26_bp_debug_if}, {rob_uop_1_25_bp_debug_if}, {rob_uop_1_24_bp_debug_if}, {rob_uop_1_23_bp_debug_if}, {rob_uop_1_22_bp_debug_if}, {rob_uop_1_21_bp_debug_if}, {rob_uop_1_20_bp_debug_if}, {rob_uop_1_19_bp_debug_if}, {rob_uop_1_18_bp_debug_if}, {rob_uop_1_17_bp_debug_if}, {rob_uop_1_16_bp_debug_if}, {rob_uop_1_15_bp_debug_if}, {rob_uop_1_14_bp_debug_if}, {rob_uop_1_13_bp_debug_if}, {rob_uop_1_12_bp_debug_if}, {rob_uop_1_11_bp_debug_if}, {rob_uop_1_10_bp_debug_if}, {rob_uop_1_9_bp_debug_if}, {rob_uop_1_8_bp_debug_if}, {rob_uop_1_7_bp_debug_if}, {rob_uop_1_6_bp_debug_if}, {rob_uop_1_5_bp_debug_if}, {rob_uop_1_4_bp_debug_if}, {rob_uop_1_3_bp_debug_if}, {rob_uop_1_2_bp_debug_if}, {rob_uop_1_1_bp_debug_if}, {rob_uop_1_0_bp_debug_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_bp_debug_if = _GEN_234[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0] _GEN_235 = {{rob_uop_1_31_bp_xcpt_if}, {rob_uop_1_30_bp_xcpt_if}, {rob_uop_1_29_bp_xcpt_if}, {rob_uop_1_28_bp_xcpt_if}, {rob_uop_1_27_bp_xcpt_if}, {rob_uop_1_26_bp_xcpt_if}, {rob_uop_1_25_bp_xcpt_if}, {rob_uop_1_24_bp_xcpt_if}, {rob_uop_1_23_bp_xcpt_if}, {rob_uop_1_22_bp_xcpt_if}, {rob_uop_1_21_bp_xcpt_if}, {rob_uop_1_20_bp_xcpt_if}, {rob_uop_1_19_bp_xcpt_if}, {rob_uop_1_18_bp_xcpt_if}, {rob_uop_1_17_bp_xcpt_if}, {rob_uop_1_16_bp_xcpt_if}, {rob_uop_1_15_bp_xcpt_if}, {rob_uop_1_14_bp_xcpt_if}, {rob_uop_1_13_bp_xcpt_if}, {rob_uop_1_12_bp_xcpt_if}, {rob_uop_1_11_bp_xcpt_if}, {rob_uop_1_10_bp_xcpt_if}, {rob_uop_1_9_bp_xcpt_if}, {rob_uop_1_8_bp_xcpt_if}, {rob_uop_1_7_bp_xcpt_if}, {rob_uop_1_6_bp_xcpt_if}, {rob_uop_1_5_bp_xcpt_if}, {rob_uop_1_4_bp_xcpt_if}, {rob_uop_1_3_bp_xcpt_if}, {rob_uop_1_2_bp_xcpt_if}, {rob_uop_1_1_bp_xcpt_if}, {rob_uop_1_0_bp_xcpt_if}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_bp_xcpt_if = _GEN_235[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_236 = {{rob_uop_1_31_debug_fsrc}, {rob_uop_1_30_debug_fsrc}, {rob_uop_1_29_debug_fsrc}, {rob_uop_1_28_debug_fsrc}, {rob_uop_1_27_debug_fsrc}, {rob_uop_1_26_debug_fsrc}, {rob_uop_1_25_debug_fsrc}, {rob_uop_1_24_debug_fsrc}, {rob_uop_1_23_debug_fsrc}, {rob_uop_1_22_debug_fsrc}, {rob_uop_1_21_debug_fsrc}, {rob_uop_1_20_debug_fsrc}, {rob_uop_1_19_debug_fsrc}, {rob_uop_1_18_debug_fsrc}, {rob_uop_1_17_debug_fsrc}, {rob_uop_1_16_debug_fsrc}, {rob_uop_1_15_debug_fsrc}, {rob_uop_1_14_debug_fsrc}, {rob_uop_1_13_debug_fsrc}, {rob_uop_1_12_debug_fsrc}, {rob_uop_1_11_debug_fsrc}, {rob_uop_1_10_debug_fsrc}, {rob_uop_1_9_debug_fsrc}, {rob_uop_1_8_debug_fsrc}, {rob_uop_1_7_debug_fsrc}, {rob_uop_1_6_debug_fsrc}, {rob_uop_1_5_debug_fsrc}, {rob_uop_1_4_debug_fsrc}, {rob_uop_1_3_debug_fsrc}, {rob_uop_1_2_debug_fsrc}, {rob_uop_1_1_debug_fsrc}, {rob_uop_1_0_debug_fsrc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_debug_fsrc = _GEN_236[rob_head]; // @[rob.scala:210:29, :313:23]
wire [31:0][2:0] _GEN_237 = {{rob_uop_1_31_debug_tsrc}, {rob_uop_1_30_debug_tsrc}, {rob_uop_1_29_debug_tsrc}, {rob_uop_1_28_debug_tsrc}, {rob_uop_1_27_debug_tsrc}, {rob_uop_1_26_debug_tsrc}, {rob_uop_1_25_debug_tsrc}, {rob_uop_1_24_debug_tsrc}, {rob_uop_1_23_debug_tsrc}, {rob_uop_1_22_debug_tsrc}, {rob_uop_1_21_debug_tsrc}, {rob_uop_1_20_debug_tsrc}, {rob_uop_1_19_debug_tsrc}, {rob_uop_1_18_debug_tsrc}, {rob_uop_1_17_debug_tsrc}, {rob_uop_1_16_debug_tsrc}, {rob_uop_1_15_debug_tsrc}, {rob_uop_1_14_debug_tsrc}, {rob_uop_1_13_debug_tsrc}, {rob_uop_1_12_debug_tsrc}, {rob_uop_1_11_debug_tsrc}, {rob_uop_1_10_debug_tsrc}, {rob_uop_1_9_debug_tsrc}, {rob_uop_1_8_debug_tsrc}, {rob_uop_1_7_debug_tsrc}, {rob_uop_1_6_debug_tsrc}, {rob_uop_1_5_debug_tsrc}, {rob_uop_1_4_debug_tsrc}, {rob_uop_1_3_debug_tsrc}, {rob_uop_1_2_debug_tsrc}, {rob_uop_1_1_debug_tsrc}, {rob_uop_1_0_debug_tsrc}}; // @[rob.scala:313:23, :361:28]
assign io_commit_uops_1_out_debug_tsrc = _GEN_237[rob_head]; // @[rob.scala:210:29, :313:23]
wire _T_719 = io_brupdate_b2_mispredict_0 & brupdate_b2_rob_bank_idx & io_brupdate_b2_uop_rob_idx_0[5:1] == rob_head; // @[rob.scala:199:7, :210:29, :254:25, :258:36, :463:37, :464:57, :465:45]
assign io_commit_uops_1_debug_fsrc_0 = _T_719 ? 3'h4 : io_commit_uops_1_out_debug_fsrc; // @[rob.scala:199:7, :313:23, :458:30, :463:37, :464:57, :465:59, :466:36]
assign io_commit_uops_1_taken_0 = _T_719 ? io_brupdate_b2_taken_0 : io_commit_uops_1_out_taken; // @[rob.scala:199:7, :313:23, :458:30, :463:37, :464:57, :465:59, :467:36]
assign rob_head_fflags_1_valid = _GEN_126[rob_head]; // @[rob.scala:210:29, :238:33, :402:18, :518:26]
wire [31:0][4:0] _GEN_238 = {{rob_fflags_2_31_bits}, {rob_fflags_2_30_bits}, {rob_fflags_2_29_bits}, {rob_fflags_2_28_bits}, {rob_fflags_2_27_bits}, {rob_fflags_2_26_bits}, {rob_fflags_2_25_bits}, {rob_fflags_2_24_bits}, {rob_fflags_2_23_bits}, {rob_fflags_2_22_bits}, {rob_fflags_2_21_bits}, {rob_fflags_2_20_bits}, {rob_fflags_2_19_bits}, {rob_fflags_2_18_bits}, {rob_fflags_2_17_bits}, {rob_fflags_2_16_bits}, {rob_fflags_2_15_bits}, {rob_fflags_2_14_bits}, {rob_fflags_2_13_bits}, {rob_fflags_2_12_bits}, {rob_fflags_2_11_bits}, {rob_fflags_2_10_bits}, {rob_fflags_2_9_bits}, {rob_fflags_2_8_bits}, {rob_fflags_2_7_bits}, {rob_fflags_2_6_bits}, {rob_fflags_2_5_bits}, {rob_fflags_2_4_bits}, {rob_fflags_2_3_bits}, {rob_fflags_2_2_bits}, {rob_fflags_2_1_bits}, {rob_fflags_2_0_bits}}; // @[rob.scala:364:28, :518:26]
assign rob_head_fflags_1_bits = _GEN_238[rob_head]; // @[rob.scala:210:29, :238:33, :518:26]
wire _rob_unsafe_masked_1_T = rob_unsafe_1_0 | rob_exception_1_0; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_1_T_1 = rob_val_1_0 & _rob_unsafe_masked_1_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_1 = _rob_unsafe_masked_1_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_3_T = rob_unsafe_1_1 | rob_exception_1_1; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_3_T_1 = rob_val_1_1 & _rob_unsafe_masked_3_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_3 = _rob_unsafe_masked_3_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_5_T = rob_unsafe_1_2 | rob_exception_1_2; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_5_T_1 = rob_val_1_2 & _rob_unsafe_masked_5_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_5 = _rob_unsafe_masked_5_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_7_T = rob_unsafe_1_3 | rob_exception_1_3; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_7_T_1 = rob_val_1_3 & _rob_unsafe_masked_7_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_7 = _rob_unsafe_masked_7_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_9_T = rob_unsafe_1_4 | rob_exception_1_4; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_9_T_1 = rob_val_1_4 & _rob_unsafe_masked_9_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_9 = _rob_unsafe_masked_9_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_11_T = rob_unsafe_1_5 | rob_exception_1_5; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_11_T_1 = rob_val_1_5 & _rob_unsafe_masked_11_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_11 = _rob_unsafe_masked_11_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_13_T = rob_unsafe_1_6 | rob_exception_1_6; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_13_T_1 = rob_val_1_6 & _rob_unsafe_masked_13_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_13 = _rob_unsafe_masked_13_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_15_T = rob_unsafe_1_7 | rob_exception_1_7; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_15_T_1 = rob_val_1_7 & _rob_unsafe_masked_15_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_15 = _rob_unsafe_masked_15_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_17_T = rob_unsafe_1_8 | rob_exception_1_8; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_17_T_1 = rob_val_1_8 & _rob_unsafe_masked_17_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_17 = _rob_unsafe_masked_17_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_19_T = rob_unsafe_1_9 | rob_exception_1_9; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_19_T_1 = rob_val_1_9 & _rob_unsafe_masked_19_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_19 = _rob_unsafe_masked_19_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_21_T = rob_unsafe_1_10 | rob_exception_1_10; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_21_T_1 = rob_val_1_10 & _rob_unsafe_masked_21_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_21 = _rob_unsafe_masked_21_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_23_T = rob_unsafe_1_11 | rob_exception_1_11; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_23_T_1 = rob_val_1_11 & _rob_unsafe_masked_23_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_23 = _rob_unsafe_masked_23_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_25_T = rob_unsafe_1_12 | rob_exception_1_12; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_25_T_1 = rob_val_1_12 & _rob_unsafe_masked_25_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_25 = _rob_unsafe_masked_25_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_27_T = rob_unsafe_1_13 | rob_exception_1_13; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_27_T_1 = rob_val_1_13 & _rob_unsafe_masked_27_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_27 = _rob_unsafe_masked_27_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_29_T = rob_unsafe_1_14 | rob_exception_1_14; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_29_T_1 = rob_val_1_14 & _rob_unsafe_masked_29_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_29 = _rob_unsafe_masked_29_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_31_T = rob_unsafe_1_15 | rob_exception_1_15; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_31_T_1 = rob_val_1_15 & _rob_unsafe_masked_31_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_31 = _rob_unsafe_masked_31_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_33_T = rob_unsafe_1_16 | rob_exception_1_16; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_33_T_1 = rob_val_1_16 & _rob_unsafe_masked_33_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_33 = _rob_unsafe_masked_33_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_35_T = rob_unsafe_1_17 | rob_exception_1_17; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_35_T_1 = rob_val_1_17 & _rob_unsafe_masked_35_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_35 = _rob_unsafe_masked_35_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_37_T = rob_unsafe_1_18 | rob_exception_1_18; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_37_T_1 = rob_val_1_18 & _rob_unsafe_masked_37_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_37 = _rob_unsafe_masked_37_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_39_T = rob_unsafe_1_19 | rob_exception_1_19; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_39_T_1 = rob_val_1_19 & _rob_unsafe_masked_39_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_39 = _rob_unsafe_masked_39_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_41_T = rob_unsafe_1_20 | rob_exception_1_20; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_41_T_1 = rob_val_1_20 & _rob_unsafe_masked_41_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_41 = _rob_unsafe_masked_41_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_43_T = rob_unsafe_1_21 | rob_exception_1_21; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_43_T_1 = rob_val_1_21 & _rob_unsafe_masked_43_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_43 = _rob_unsafe_masked_43_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_45_T = rob_unsafe_1_22 | rob_exception_1_22; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_45_T_1 = rob_val_1_22 & _rob_unsafe_masked_45_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_45 = _rob_unsafe_masked_45_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_47_T = rob_unsafe_1_23 | rob_exception_1_23; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_47_T_1 = rob_val_1_23 & _rob_unsafe_masked_47_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_47 = _rob_unsafe_masked_47_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_49_T = rob_unsafe_1_24 | rob_exception_1_24; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_49_T_1 = rob_val_1_24 & _rob_unsafe_masked_49_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_49 = _rob_unsafe_masked_49_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_51_T = rob_unsafe_1_25 | rob_exception_1_25; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_51_T_1 = rob_val_1_25 & _rob_unsafe_masked_51_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_51 = _rob_unsafe_masked_51_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_53_T = rob_unsafe_1_26 | rob_exception_1_26; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_53_T_1 = rob_val_1_26 & _rob_unsafe_masked_53_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_53 = _rob_unsafe_masked_53_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_55_T = rob_unsafe_1_27 | rob_exception_1_27; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_55_T_1 = rob_val_1_27 & _rob_unsafe_masked_55_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_55 = _rob_unsafe_masked_55_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_57_T = rob_unsafe_1_28 | rob_exception_1_28; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_57_T_1 = rob_val_1_28 & _rob_unsafe_masked_57_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_57 = _rob_unsafe_masked_57_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_59_T = rob_unsafe_1_29 | rob_exception_1_29; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_59_T_1 = rob_val_1_29 & _rob_unsafe_masked_59_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_59 = _rob_unsafe_masked_59_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_61_T = rob_unsafe_1_30 | rob_exception_1_30; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_61_T_1 = rob_val_1_30 & _rob_unsafe_masked_61_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_61 = _rob_unsafe_masked_61_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_unsafe_masked_63_T = rob_unsafe_1_31 | rob_exception_1_31; // @[rob.scala:360:28, :362:28, :525:89]
assign _rob_unsafe_masked_63_T_1 = rob_val_1_31 & _rob_unsafe_masked_63_T; // @[rob.scala:358:32, :525:{71,89}]
assign rob_unsafe_masked_63 = _rob_unsafe_masked_63_T_1; // @[rob.scala:280:35, :525:71]
wire _rob_pnr_unsafe_1_T = _GEN_131[rob_pnr] | _GEN_133[rob_pnr]; // @[rob.scala:218:29, :437:15, :444:49, :528:67]
assign _rob_pnr_unsafe_1_T_1 = _GEN_125[rob_pnr] & _rob_pnr_unsafe_1_T; // @[rob.scala:218:29, :375:31, :528:{43,67}]
assign rob_pnr_unsafe_1 = _rob_pnr_unsafe_1_T_1; // @[rob.scala:233:33, :528:43]
wire [4:0] _temp_uop_T_13 = _temp_uop_T_12[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_15 = _temp_uop_T_14[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_17 = _temp_uop_T_16[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_19 = _temp_uop_T_18[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_21 = _temp_uop_T_20[4:0]; // @[rob.scala:254:25]
wire [4:0] _temp_uop_T_23 = _temp_uop_T_22[4:0]; // @[rob.scala:254:25]
wire _block_commit_T = rob_state != 2'h1; // @[rob.scala:207:26, :567:33]
wire _block_commit_T_1 = rob_state != 2'h2; // @[rob.scala:207:26, :567:61]
wire _block_commit_T_2 = _block_commit_T & _block_commit_T_1; // @[rob.scala:567:{33,47,61}]
reg block_commit_REG; // @[rob.scala:567:94]
wire _block_commit_T_3 = _block_commit_T_2 | block_commit_REG; // @[rob.scala:567:{47,84,94}]
reg block_commit_REG_1; // @[rob.scala:567:131]
reg block_commit_REG_2; // @[rob.scala:567:123]
wire block_commit = _block_commit_T_3 | block_commit_REG_2; // @[rob.scala:567:{84,113,123}]
wire _will_commit_0_T = ~can_throw_exception_0; // @[rob.scala:231:33, :574:46]
wire _will_commit_0_T_1 = can_commit_0 & _will_commit_0_T; // @[rob.scala:230:33, :574:{43,46}]
wire _will_commit_0_T_2 = ~block_commit; // @[rob.scala:567:113, :572:55, :574:73]
assign _will_commit_0_T_3 = _will_commit_0_T_1 & _will_commit_0_T_2; // @[rob.scala:574:{43,70,73}]
assign will_commit_0 = _will_commit_0_T_3; // @[rob.scala:229:33, :574:70]
wire _T_1156 = rob_head_vals_0 & (~can_commit_0 | can_throw_exception_0) | block_commit; // @[rob.scala:230:33, :231:33, :234:33, :567:113, :575:46, :576:{29,44,72}]
assign exception_thrown = can_throw_exception_1 & ~_T_1156 & ~will_commit_0 | can_throw_exception_0 & ~block_commit; // @[rob.scala:229:33, :231:33, :240:30, :567:113, :572:{52,55,69,72,85}, :576:72]
wire _will_commit_1_T = ~can_throw_exception_1; // @[rob.scala:231:33, :574:46]
wire _will_commit_1_T_1 = can_commit_1 & _will_commit_1_T; // @[rob.scala:230:33, :574:{43,46}]
wire _will_commit_1_T_2 = ~_T_1156; // @[rob.scala:572:55, :574:73, :576:72]
assign _will_commit_1_T_3 = _will_commit_1_T_1 & _will_commit_1_T_2; // @[rob.scala:574:{43,70,73}]
assign will_commit_1 = _will_commit_1_T_3; // @[rob.scala:229:33, :574:70]
wire _is_mini_exception_T = io_com_xcpt_bits_cause_0 == 64'h10; // @[package.scala:16:47]
wire _is_mini_exception_T_1 = io_com_xcpt_bits_cause_0 == 64'h11; // @[package.scala:16:47]
wire is_mini_exception = _is_mini_exception_T | _is_mini_exception_T_1; // @[package.scala:16:47, :81:59]
wire _io_com_xcpt_valid_T = ~is_mini_exception; // @[package.scala:81:59]
assign _io_com_xcpt_valid_T_1 = exception_thrown & _io_com_xcpt_valid_T; // @[rob.scala:240:30, :584:{41,44}]
assign io_com_xcpt_valid_0 = _io_com_xcpt_valid_T_1; // @[rob.scala:199:7, :584:41]
wire _io_com_xcpt_bits_badvaddr_T = r_xcpt_badvaddr[39]; // @[util.scala:269:46]
wire [23:0] _io_com_xcpt_bits_badvaddr_T_1 = {24{_io_com_xcpt_bits_badvaddr_T}}; // @[util.scala:269:{25,46}]
assign _io_com_xcpt_bits_badvaddr_T_2 = {_io_com_xcpt_bits_badvaddr_T_1, r_xcpt_badvaddr}; // @[util.scala:269:{20,25}]
assign io_com_xcpt_bits_badvaddr_0 = _io_com_xcpt_bits_badvaddr_T_2; // @[util.scala:269:20]
wire _insn_sys_pc2epc_T = rob_head_vals_0 | rob_head_vals_1; // @[rob.scala:234:33, :590:27]
wire _GEN_239 = rob_head_vals_0 ? io_commit_uops_0_is_sys_pc2epc_0 : io_commit_uops_1_is_sys_pc2epc_0; // @[Mux.scala:50:70]
wire _insn_sys_pc2epc_T_1; // @[Mux.scala:50:70]
assign _insn_sys_pc2epc_T_1 = _GEN_239; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_sys_pc2epc; // @[Mux.scala:50:70]
assign com_xcpt_uop_is_sys_pc2epc = _GEN_239; // @[Mux.scala:50:70]
wire insn_sys_pc2epc = _insn_sys_pc2epc_T & _insn_sys_pc2epc_T_1; // @[Mux.scala:50:70]
wire refetch_inst = exception_thrown | insn_sys_pc2epc; // @[rob.scala:240:30, :590:31, :592:39]
wire [31:0] com_xcpt_uop_inst = rob_head_vals_0 ? io_commit_uops_0_inst_0 : io_commit_uops_1_inst_0; // @[Mux.scala:50:70]
wire [31:0] com_xcpt_uop_debug_inst = rob_head_vals_0 ? io_commit_uops_0_debug_inst_0 : io_commit_uops_1_debug_inst_0; // @[Mux.scala:50:70]
assign com_xcpt_uop_is_rvc = rob_head_vals_0 ? io_commit_uops_0_is_rvc_0 : io_commit_uops_1_is_rvc_0; // @[Mux.scala:50:70]
wire [39:0] com_xcpt_uop_debug_pc = rob_head_vals_0 ? io_commit_uops_0_debug_pc_0 : io_commit_uops_1_debug_pc_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iq_type_0 = rob_head_vals_0 ? io_commit_uops_0_iq_type_0_0 : io_commit_uops_1_iq_type_0_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iq_type_1 = rob_head_vals_0 ? io_commit_uops_0_iq_type_1_0 : io_commit_uops_1_iq_type_1_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iq_type_2 = rob_head_vals_0 ? io_commit_uops_0_iq_type_2_0 : io_commit_uops_1_iq_type_2_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iq_type_3 = rob_head_vals_0 ? io_commit_uops_0_iq_type_3_0 : io_commit_uops_1_iq_type_3_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_0 = rob_head_vals_0 ? io_commit_uops_0_fu_code_0_0 : io_commit_uops_1_fu_code_0_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_1 = rob_head_vals_0 ? io_commit_uops_0_fu_code_1_0 : io_commit_uops_1_fu_code_1_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_2 = rob_head_vals_0 ? io_commit_uops_0_fu_code_2_0 : io_commit_uops_1_fu_code_2_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_3 = rob_head_vals_0 ? io_commit_uops_0_fu_code_3_0 : io_commit_uops_1_fu_code_3_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_4 = rob_head_vals_0 ? io_commit_uops_0_fu_code_4_0 : io_commit_uops_1_fu_code_4_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_5 = rob_head_vals_0 ? io_commit_uops_0_fu_code_5_0 : io_commit_uops_1_fu_code_5_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_6 = rob_head_vals_0 ? io_commit_uops_0_fu_code_6_0 : io_commit_uops_1_fu_code_6_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_7 = rob_head_vals_0 ? io_commit_uops_0_fu_code_7_0 : io_commit_uops_1_fu_code_7_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_8 = rob_head_vals_0 ? io_commit_uops_0_fu_code_8_0 : io_commit_uops_1_fu_code_8_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fu_code_9 = rob_head_vals_0 ? io_commit_uops_0_fu_code_9_0 : io_commit_uops_1_fu_code_9_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_issued = rob_head_vals_0 ? io_commit_uops_0_iw_issued_0 : io_commit_uops_1_iw_issued_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_issued_partial_agen = rob_head_vals_0 ? io_commit_uops_0_iw_issued_partial_agen_0 : io_commit_uops_1_iw_issued_partial_agen_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_issued_partial_dgen = rob_head_vals_0 ? io_commit_uops_0_iw_issued_partial_dgen_0 : io_commit_uops_1_iw_issued_partial_dgen_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_iw_p1_speculative_child = rob_head_vals_0 ? io_commit_uops_0_iw_p1_speculative_child_0 : io_commit_uops_1_iw_p1_speculative_child_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_iw_p2_speculative_child = rob_head_vals_0 ? io_commit_uops_0_iw_p2_speculative_child_0 : io_commit_uops_1_iw_p2_speculative_child_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_p1_bypass_hint = rob_head_vals_0 ? io_commit_uops_0_iw_p1_bypass_hint_0 : io_commit_uops_1_iw_p1_bypass_hint_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_p2_bypass_hint = rob_head_vals_0 ? io_commit_uops_0_iw_p2_bypass_hint_0 : io_commit_uops_1_iw_p2_bypass_hint_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_iw_p3_bypass_hint = rob_head_vals_0 ? io_commit_uops_0_iw_p3_bypass_hint_0 : io_commit_uops_1_iw_p3_bypass_hint_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_dis_col_sel = rob_head_vals_0 ? io_commit_uops_0_dis_col_sel_0 : io_commit_uops_1_dis_col_sel_0; // @[Mux.scala:50:70]
wire [11:0] com_xcpt_uop_br_mask = rob_head_vals_0 ? io_commit_uops_0_br_mask_0 : io_commit_uops_1_br_mask_0; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_br_tag = rob_head_vals_0 ? io_commit_uops_0_br_tag_0 : io_commit_uops_1_br_tag_0; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_br_type = rob_head_vals_0 ? io_commit_uops_0_br_type_0 : io_commit_uops_1_br_type_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_sfb = rob_head_vals_0 ? io_commit_uops_0_is_sfb_0 : io_commit_uops_1_is_sfb_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_fence = rob_head_vals_0 ? io_commit_uops_0_is_fence_0 : io_commit_uops_1_is_fence_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_fencei = rob_head_vals_0 ? io_commit_uops_0_is_fencei_0 : io_commit_uops_1_is_fencei_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_sfence = rob_head_vals_0 ? io_commit_uops_0_is_sfence_0 : io_commit_uops_1_is_sfence_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_amo = rob_head_vals_0 ? io_commit_uops_0_is_amo_0 : io_commit_uops_1_is_amo_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_eret = rob_head_vals_0 ? io_commit_uops_0_is_eret_0 : io_commit_uops_1_is_eret_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_rocc = rob_head_vals_0 ? io_commit_uops_0_is_rocc_0 : io_commit_uops_1_is_rocc_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_mov = rob_head_vals_0 ? io_commit_uops_0_is_mov_0 : io_commit_uops_1_is_mov_0; // @[Mux.scala:50:70]
assign com_xcpt_uop_ftq_idx = rob_head_vals_0 ? io_commit_uops_0_ftq_idx_0 : io_commit_uops_1_ftq_idx_0; // @[Mux.scala:50:70]
assign com_xcpt_uop_edge_inst = rob_head_vals_0 ? io_commit_uops_0_edge_inst_0 : io_commit_uops_1_edge_inst_0; // @[Mux.scala:50:70]
assign com_xcpt_uop_pc_lob = rob_head_vals_0 ? io_commit_uops_0_pc_lob_0 : io_commit_uops_1_pc_lob_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_taken = rob_head_vals_0 ? io_commit_uops_0_taken_0 : io_commit_uops_1_taken_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_imm_rename = rob_head_vals_0 ? io_commit_uops_0_imm_rename_0 : io_commit_uops_1_imm_rename_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_imm_sel = rob_head_vals_0 ? io_commit_uops_0_imm_sel_0 : io_commit_uops_1_imm_sel_0; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_pimm = rob_head_vals_0 ? io_commit_uops_0_pimm_0 : io_commit_uops_1_pimm_0; // @[Mux.scala:50:70]
wire [19:0] com_xcpt_uop_imm_packed = rob_head_vals_0 ? io_commit_uops_0_imm_packed_0 : io_commit_uops_1_imm_packed_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_op1_sel = rob_head_vals_0 ? io_commit_uops_0_op1_sel_0 : io_commit_uops_1_op1_sel_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_op2_sel = rob_head_vals_0 ? io_commit_uops_0_op2_sel_0 : io_commit_uops_1_op2_sel_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_ldst = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_ldst_0 : io_commit_uops_1_fp_ctrl_ldst_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_wen = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_wen_0 : io_commit_uops_1_fp_ctrl_wen_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_ren1 = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_ren1_0 : io_commit_uops_1_fp_ctrl_ren1_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_ren2 = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_ren2_0 : io_commit_uops_1_fp_ctrl_ren2_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_ren3 = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_ren3_0 : io_commit_uops_1_fp_ctrl_ren3_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_swap12 = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_swap12_0 : io_commit_uops_1_fp_ctrl_swap12_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_swap23 = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_swap23_0 : io_commit_uops_1_fp_ctrl_swap23_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_fp_ctrl_typeTagIn = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_typeTagIn_0 : io_commit_uops_1_fp_ctrl_typeTagIn_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_fp_ctrl_typeTagOut = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_typeTagOut_0 : io_commit_uops_1_fp_ctrl_typeTagOut_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_fromint = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_fromint_0 : io_commit_uops_1_fp_ctrl_fromint_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_toint = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_toint_0 : io_commit_uops_1_fp_ctrl_toint_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_fastpipe = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_fastpipe_0 : io_commit_uops_1_fp_ctrl_fastpipe_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_fma = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_fma_0 : io_commit_uops_1_fp_ctrl_fma_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_div = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_div_0 : io_commit_uops_1_fp_ctrl_div_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_sqrt = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_sqrt_0 : io_commit_uops_1_fp_ctrl_sqrt_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_wflags = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_wflags_0 : io_commit_uops_1_fp_ctrl_wflags_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_ctrl_vec = rob_head_vals_0 ? io_commit_uops_0_fp_ctrl_vec_0 : io_commit_uops_1_fp_ctrl_vec_0; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_rob_idx = rob_head_vals_0 ? io_commit_uops_0_rob_idx_0 : io_commit_uops_1_rob_idx_0; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_ldq_idx = rob_head_vals_0 ? io_commit_uops_0_ldq_idx_0 : io_commit_uops_1_ldq_idx_0; // @[Mux.scala:50:70]
wire [3:0] com_xcpt_uop_stq_idx = rob_head_vals_0 ? io_commit_uops_0_stq_idx_0 : io_commit_uops_1_stq_idx_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_rxq_idx = rob_head_vals_0 ? io_commit_uops_0_rxq_idx_0 : io_commit_uops_1_rxq_idx_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_pdst = rob_head_vals_0 ? io_commit_uops_0_pdst_0 : io_commit_uops_1_pdst_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs1 = rob_head_vals_0 ? io_commit_uops_0_prs1_0 : io_commit_uops_1_prs1_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs2 = rob_head_vals_0 ? io_commit_uops_0_prs2_0 : io_commit_uops_1_prs2_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_prs3 = rob_head_vals_0 ? io_commit_uops_0_prs3_0 : io_commit_uops_1_prs3_0; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_ppred = rob_head_vals_0 ? io_commit_uops_0_ppred_0 : io_commit_uops_1_ppred_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs1_busy = rob_head_vals_0 ? io_commit_uops_0_prs1_busy_0 : io_commit_uops_1_prs1_busy_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs2_busy = rob_head_vals_0 ? io_commit_uops_0_prs2_busy_0 : io_commit_uops_1_prs2_busy_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_prs3_busy = rob_head_vals_0 ? io_commit_uops_0_prs3_busy_0 : io_commit_uops_1_prs3_busy_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_ppred_busy = rob_head_vals_0 ? io_commit_uops_0_ppred_busy_0 : io_commit_uops_1_ppred_busy_0; // @[Mux.scala:50:70]
wire [6:0] com_xcpt_uop_stale_pdst = rob_head_vals_0 ? io_commit_uops_0_stale_pdst_0 : io_commit_uops_1_stale_pdst_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_exception = rob_head_vals_0 ? io_commit_uops_0_exception_0 : io_commit_uops_1_exception_0; // @[Mux.scala:50:70]
wire [63:0] com_xcpt_uop_exc_cause = rob_head_vals_0 ? io_commit_uops_0_exc_cause_0 : io_commit_uops_1_exc_cause_0; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_mem_cmd = rob_head_vals_0 ? io_commit_uops_0_mem_cmd_0 : io_commit_uops_1_mem_cmd_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_mem_size = rob_head_vals_0 ? io_commit_uops_0_mem_size_0 : io_commit_uops_1_mem_size_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_mem_signed = rob_head_vals_0 ? io_commit_uops_0_mem_signed_0 : io_commit_uops_1_mem_signed_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_uses_ldq = rob_head_vals_0 ? io_commit_uops_0_uses_ldq_0 : io_commit_uops_1_uses_ldq_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_uses_stq = rob_head_vals_0 ? io_commit_uops_0_uses_stq_0 : io_commit_uops_1_uses_stq_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_is_unique = rob_head_vals_0 ? io_commit_uops_0_is_unique_0 : io_commit_uops_1_is_unique_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_flush_on_commit = rob_head_vals_0 ? io_commit_uops_0_flush_on_commit_0 : io_commit_uops_1_flush_on_commit_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_csr_cmd = rob_head_vals_0 ? io_commit_uops_0_csr_cmd_0 : io_commit_uops_1_csr_cmd_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_ldst_is_rs1 = rob_head_vals_0 ? io_commit_uops_0_ldst_is_rs1_0 : io_commit_uops_1_ldst_is_rs1_0; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_ldst = rob_head_vals_0 ? io_commit_uops_0_ldst_0 : io_commit_uops_1_ldst_0; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs1 = rob_head_vals_0 ? io_commit_uops_0_lrs1_0 : io_commit_uops_1_lrs1_0; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs2 = rob_head_vals_0 ? io_commit_uops_0_lrs2_0 : io_commit_uops_1_lrs2_0; // @[Mux.scala:50:70]
wire [5:0] com_xcpt_uop_lrs3 = rob_head_vals_0 ? io_commit_uops_0_lrs3_0 : io_commit_uops_1_lrs3_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_dst_rtype = rob_head_vals_0 ? io_commit_uops_0_dst_rtype_0 : io_commit_uops_1_dst_rtype_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_lrs1_rtype = rob_head_vals_0 ? io_commit_uops_0_lrs1_rtype_0 : io_commit_uops_1_lrs1_rtype_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_lrs2_rtype = rob_head_vals_0 ? io_commit_uops_0_lrs2_rtype_0 : io_commit_uops_1_lrs2_rtype_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_frs3_en = rob_head_vals_0 ? io_commit_uops_0_frs3_en_0 : io_commit_uops_1_frs3_en_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fcn_dw = rob_head_vals_0 ? io_commit_uops_0_fcn_dw_0 : io_commit_uops_1_fcn_dw_0; // @[Mux.scala:50:70]
wire [4:0] com_xcpt_uop_fcn_op = rob_head_vals_0 ? io_commit_uops_0_fcn_op_0 : io_commit_uops_1_fcn_op_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_fp_val = rob_head_vals_0 ? io_commit_uops_0_fp_val_0 : io_commit_uops_1_fp_val_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_fp_rm = rob_head_vals_0 ? io_commit_uops_0_fp_rm_0 : io_commit_uops_1_fp_rm_0; // @[Mux.scala:50:70]
wire [1:0] com_xcpt_uop_fp_typ = rob_head_vals_0 ? io_commit_uops_0_fp_typ_0 : io_commit_uops_1_fp_typ_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_pf_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_pf_if_0 : io_commit_uops_1_xcpt_pf_if_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_ae_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_ae_if_0 : io_commit_uops_1_xcpt_ae_if_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_xcpt_ma_if = rob_head_vals_0 ? io_commit_uops_0_xcpt_ma_if_0 : io_commit_uops_1_xcpt_ma_if_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_bp_debug_if = rob_head_vals_0 ? io_commit_uops_0_bp_debug_if_0 : io_commit_uops_1_bp_debug_if_0; // @[Mux.scala:50:70]
wire com_xcpt_uop_bp_xcpt_if = rob_head_vals_0 ? io_commit_uops_0_bp_xcpt_if_0 : io_commit_uops_1_bp_xcpt_if_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_debug_fsrc = rob_head_vals_0 ? io_commit_uops_0_debug_fsrc_0 : io_commit_uops_1_debug_fsrc_0; // @[Mux.scala:50:70]
wire [2:0] com_xcpt_uop_debug_tsrc = rob_head_vals_0 ? io_commit_uops_0_debug_tsrc_0 : io_commit_uops_1_debug_tsrc_0; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_is_rvc = com_xcpt_uop_is_rvc; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_ftq_idx_0 = com_xcpt_uop_ftq_idx; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_edge_inst_0 = com_xcpt_uop_edge_inst; // @[Mux.scala:50:70]
assign io_com_xcpt_bits_pc_lob_0 = com_xcpt_uop_pc_lob; // @[Mux.scala:50:70]
wire flush_commit_mask_0 = io_commit_valids_0_0 & io_commit_uops_0_flush_on_commit_0; // @[rob.scala:199:7, :599:75]
wire flush_commit_mask_1 = io_commit_valids_1_0 & io_commit_uops_1_flush_on_commit_0; // @[rob.scala:199:7, :599:75]
wire flush_commit = flush_commit_mask_0 | flush_commit_mask_1; // @[rob.scala:599:75, :600:48]
assign flush_val = exception_thrown | flush_commit; // @[rob.scala:240:30, :600:48, :601:36]
assign io_flush_valid_0 = flush_val; // @[rob.scala:199:7, :601:36]
wire [31:0] _flush_uop_WIRE_114; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_113; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_112; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_WIRE_111; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_106_0; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_106_1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_106_2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_106_3; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_0; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_3; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_4; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_5; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_6; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_7; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_8; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_95_9; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_94; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_93; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_92; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_91; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_90; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_89; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_88; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_87; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_86; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_WIRE_85; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_84; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_83; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_82; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_81; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_80; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_79; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_78; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_77; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_76; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_75; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_74; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_73; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_72; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_71; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_70; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_69; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_68; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_67; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_WIRE_66; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_65; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_64; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_ldst; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_wen; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_ren1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_ren2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_ren3; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_swap12; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_swap23; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_46_typeTagIn; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_46_typeTagOut; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_fromint; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_toint; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_fastpipe; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_fma; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_div; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_sqrt; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_wflags; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_46_vec; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_45; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_44; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_43; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_42; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_41; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_40; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_39; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_38; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_37; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_36; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_35; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_34; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_33; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_32; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_31; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_WIRE_30; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_29; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_28; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_27; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_26; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_25; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_24; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_23; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_22; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_21; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_20; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_19; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_18; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_17; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_16; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_15; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_14; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_13; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_12; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_11; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_10; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_9; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_8; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_7; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_6; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_5; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_4; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_3; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_2; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_1; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T = flush_commit_mask_0 ? io_commit_uops_0_debug_tsrc_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_1 = flush_commit_mask_1 ? io_commit_uops_1_debug_tsrc_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_2 = _flush_uop_T | _flush_uop_T_1; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_1 = _flush_uop_T_2; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_debug_tsrc = _flush_uop_WIRE_1; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_3 = flush_commit_mask_0 ? io_commit_uops_0_debug_fsrc_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_4 = flush_commit_mask_1 ? io_commit_uops_1_debug_fsrc_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_5 = _flush_uop_T_3 | _flush_uop_T_4; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_2 = _flush_uop_T_5; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_debug_fsrc = _flush_uop_WIRE_2; // @[Mux.scala:30:73]
wire _flush_uop_T_6 = flush_commit_mask_0 & io_commit_uops_0_bp_xcpt_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_7 = flush_commit_mask_1 & io_commit_uops_1_bp_xcpt_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_8 = _flush_uop_T_6 | _flush_uop_T_7; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_3 = _flush_uop_T_8; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_bp_xcpt_if = _flush_uop_WIRE_3; // @[Mux.scala:30:73]
wire _flush_uop_T_9 = flush_commit_mask_0 & io_commit_uops_0_bp_debug_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_10 = flush_commit_mask_1 & io_commit_uops_1_bp_debug_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_11 = _flush_uop_T_9 | _flush_uop_T_10; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_4 = _flush_uop_T_11; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_bp_debug_if = _flush_uop_WIRE_4; // @[Mux.scala:30:73]
wire _flush_uop_T_12 = flush_commit_mask_0 & io_commit_uops_0_xcpt_ma_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_13 = flush_commit_mask_1 & io_commit_uops_1_xcpt_ma_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_14 = _flush_uop_T_12 | _flush_uop_T_13; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_5 = _flush_uop_T_14; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_ma_if = _flush_uop_WIRE_5; // @[Mux.scala:30:73]
wire _flush_uop_T_15 = flush_commit_mask_0 & io_commit_uops_0_xcpt_ae_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_16 = flush_commit_mask_1 & io_commit_uops_1_xcpt_ae_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_17 = _flush_uop_T_15 | _flush_uop_T_16; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_6 = _flush_uop_T_17; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_ae_if = _flush_uop_WIRE_6; // @[Mux.scala:30:73]
wire _flush_uop_T_18 = flush_commit_mask_0 & io_commit_uops_0_xcpt_pf_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_19 = flush_commit_mask_1 & io_commit_uops_1_xcpt_pf_if_0; // @[Mux.scala:30:73]
wire _flush_uop_T_20 = _flush_uop_T_18 | _flush_uop_T_19; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_7 = _flush_uop_T_20; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_xcpt_pf_if = _flush_uop_WIRE_7; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_21 = flush_commit_mask_0 ? io_commit_uops_0_fp_typ_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_22 = flush_commit_mask_1 ? io_commit_uops_1_fp_typ_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_23 = _flush_uop_T_21 | _flush_uop_T_22; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_8 = _flush_uop_T_23; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_fp_typ = _flush_uop_WIRE_8; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_24 = flush_commit_mask_0 ? io_commit_uops_0_fp_rm_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_25 = flush_commit_mask_1 ? io_commit_uops_1_fp_rm_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_26 = _flush_uop_T_24 | _flush_uop_T_25; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_9 = _flush_uop_T_26; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_fp_rm = _flush_uop_WIRE_9; // @[Mux.scala:30:73]
wire _flush_uop_T_27 = flush_commit_mask_0 & io_commit_uops_0_fp_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_28 = flush_commit_mask_1 & io_commit_uops_1_fp_val_0; // @[Mux.scala:30:73]
wire _flush_uop_T_29 = _flush_uop_T_27 | _flush_uop_T_28; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_10 = _flush_uop_T_29; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_val = _flush_uop_WIRE_10; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_30 = flush_commit_mask_0 ? io_commit_uops_0_fcn_op_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_31 = flush_commit_mask_1 ? io_commit_uops_1_fcn_op_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_32 = _flush_uop_T_30 | _flush_uop_T_31; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_11 = _flush_uop_T_32; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_fcn_op = _flush_uop_WIRE_11; // @[Mux.scala:30:73]
wire _flush_uop_T_33 = flush_commit_mask_0 & io_commit_uops_0_fcn_dw_0; // @[Mux.scala:30:73]
wire _flush_uop_T_34 = flush_commit_mask_1 & io_commit_uops_1_fcn_dw_0; // @[Mux.scala:30:73]
wire _flush_uop_T_35 = _flush_uop_T_33 | _flush_uop_T_34; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_12 = _flush_uop_T_35; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fcn_dw = _flush_uop_WIRE_12; // @[Mux.scala:30:73]
wire _flush_uop_T_36 = flush_commit_mask_0 & io_commit_uops_0_frs3_en_0; // @[Mux.scala:30:73]
wire _flush_uop_T_37 = flush_commit_mask_1 & io_commit_uops_1_frs3_en_0; // @[Mux.scala:30:73]
wire _flush_uop_T_38 = _flush_uop_T_36 | _flush_uop_T_37; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_13 = _flush_uop_T_38; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_frs3_en = _flush_uop_WIRE_13; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_39 = flush_commit_mask_0 ? io_commit_uops_0_lrs2_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_40 = flush_commit_mask_1 ? io_commit_uops_1_lrs2_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_41 = _flush_uop_T_39 | _flush_uop_T_40; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_14 = _flush_uop_T_41; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_lrs2_rtype = _flush_uop_WIRE_14; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_42 = flush_commit_mask_0 ? io_commit_uops_0_lrs1_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_43 = flush_commit_mask_1 ? io_commit_uops_1_lrs1_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_44 = _flush_uop_T_42 | _flush_uop_T_43; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_15 = _flush_uop_T_44; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_lrs1_rtype = _flush_uop_WIRE_15; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_45 = flush_commit_mask_0 ? io_commit_uops_0_dst_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_46 = flush_commit_mask_1 ? io_commit_uops_1_dst_rtype_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_47 = _flush_uop_T_45 | _flush_uop_T_46; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_16 = _flush_uop_T_47; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_dst_rtype = _flush_uop_WIRE_16; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_48 = flush_commit_mask_0 ? io_commit_uops_0_lrs3_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_49 = flush_commit_mask_1 ? io_commit_uops_1_lrs3_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_50 = _flush_uop_T_48 | _flush_uop_T_49; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_17 = _flush_uop_T_50; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs3 = _flush_uop_WIRE_17; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_51 = flush_commit_mask_0 ? io_commit_uops_0_lrs2_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_52 = flush_commit_mask_1 ? io_commit_uops_1_lrs2_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_53 = _flush_uop_T_51 | _flush_uop_T_52; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_18 = _flush_uop_T_53; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs2 = _flush_uop_WIRE_18; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_54 = flush_commit_mask_0 ? io_commit_uops_0_lrs1_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_55 = flush_commit_mask_1 ? io_commit_uops_1_lrs1_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_56 = _flush_uop_T_54 | _flush_uop_T_55; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_19 = _flush_uop_T_56; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_lrs1 = _flush_uop_WIRE_19; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_57 = flush_commit_mask_0 ? io_commit_uops_0_ldst_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_58 = flush_commit_mask_1 ? io_commit_uops_1_ldst_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_59 = _flush_uop_T_57 | _flush_uop_T_58; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_20 = _flush_uop_T_59; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_ldst = _flush_uop_WIRE_20; // @[Mux.scala:30:73]
wire _flush_uop_T_60 = flush_commit_mask_0 & io_commit_uops_0_ldst_is_rs1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_61 = flush_commit_mask_1 & io_commit_uops_1_ldst_is_rs1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_62 = _flush_uop_T_60 | _flush_uop_T_61; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_21 = _flush_uop_T_62; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ldst_is_rs1 = _flush_uop_WIRE_21; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_63 = flush_commit_mask_0 ? io_commit_uops_0_csr_cmd_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_64 = flush_commit_mask_1 ? io_commit_uops_1_csr_cmd_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_65 = _flush_uop_T_63 | _flush_uop_T_64; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_22 = _flush_uop_T_65; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_csr_cmd = _flush_uop_WIRE_22; // @[Mux.scala:30:73]
wire _flush_uop_T_66 = flush_commit_mask_0 & io_commit_uops_0_flush_on_commit_0; // @[Mux.scala:30:73]
wire _flush_uop_T_67 = flush_commit_mask_1 & io_commit_uops_1_flush_on_commit_0; // @[Mux.scala:30:73]
wire _flush_uop_T_68 = _flush_uop_T_66 | _flush_uop_T_67; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_23 = _flush_uop_T_68; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_flush_on_commit = _flush_uop_WIRE_23; // @[Mux.scala:30:73]
wire _flush_uop_T_69 = flush_commit_mask_0 & io_commit_uops_0_is_unique_0; // @[Mux.scala:30:73]
wire _flush_uop_T_70 = flush_commit_mask_1 & io_commit_uops_1_is_unique_0; // @[Mux.scala:30:73]
wire _flush_uop_T_71 = _flush_uop_T_69 | _flush_uop_T_70; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_24 = _flush_uop_T_71; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_unique = _flush_uop_WIRE_24; // @[Mux.scala:30:73]
wire _flush_uop_T_72 = flush_commit_mask_0 & io_commit_uops_0_uses_stq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_73 = flush_commit_mask_1 & io_commit_uops_1_uses_stq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_74 = _flush_uop_T_72 | _flush_uop_T_73; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_25 = _flush_uop_T_74; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_uses_stq = _flush_uop_WIRE_25; // @[Mux.scala:30:73]
wire _flush_uop_T_75 = flush_commit_mask_0 & io_commit_uops_0_uses_ldq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_76 = flush_commit_mask_1 & io_commit_uops_1_uses_ldq_0; // @[Mux.scala:30:73]
wire _flush_uop_T_77 = _flush_uop_T_75 | _flush_uop_T_76; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_26 = _flush_uop_T_77; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_uses_ldq = _flush_uop_WIRE_26; // @[Mux.scala:30:73]
wire _flush_uop_T_78 = flush_commit_mask_0 & io_commit_uops_0_mem_signed_0; // @[Mux.scala:30:73]
wire _flush_uop_T_79 = flush_commit_mask_1 & io_commit_uops_1_mem_signed_0; // @[Mux.scala:30:73]
wire _flush_uop_T_80 = _flush_uop_T_78 | _flush_uop_T_79; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_27 = _flush_uop_T_80; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_mem_signed = _flush_uop_WIRE_27; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_81 = flush_commit_mask_0 ? io_commit_uops_0_mem_size_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_82 = flush_commit_mask_1 ? io_commit_uops_1_mem_size_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_83 = _flush_uop_T_81 | _flush_uop_T_82; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_28 = _flush_uop_T_83; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_mem_size = _flush_uop_WIRE_28; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_84 = flush_commit_mask_0 ? io_commit_uops_0_mem_cmd_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_85 = flush_commit_mask_1 ? io_commit_uops_1_mem_cmd_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_86 = _flush_uop_T_84 | _flush_uop_T_85; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_29 = _flush_uop_T_86; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_mem_cmd = _flush_uop_WIRE_29; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_87 = flush_commit_mask_0 ? io_commit_uops_0_exc_cause_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_88 = flush_commit_mask_1 ? io_commit_uops_1_exc_cause_0 : 64'h0; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_T_89 = _flush_uop_T_87 | _flush_uop_T_88; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_30 = _flush_uop_T_89; // @[Mux.scala:30:73]
wire [63:0] _flush_uop_WIRE_exc_cause = _flush_uop_WIRE_30; // @[Mux.scala:30:73]
wire _flush_uop_T_90 = flush_commit_mask_0 & io_commit_uops_0_exception_0; // @[Mux.scala:30:73]
wire _flush_uop_T_91 = flush_commit_mask_1 & io_commit_uops_1_exception_0; // @[Mux.scala:30:73]
wire _flush_uop_T_92 = _flush_uop_T_90 | _flush_uop_T_91; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_31 = _flush_uop_T_92; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_exception = _flush_uop_WIRE_31; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_93 = flush_commit_mask_0 ? io_commit_uops_0_stale_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_94 = flush_commit_mask_1 ? io_commit_uops_1_stale_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_95 = _flush_uop_T_93 | _flush_uop_T_94; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_32 = _flush_uop_T_95; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_stale_pdst = _flush_uop_WIRE_32; // @[Mux.scala:30:73]
wire _flush_uop_T_96 = flush_commit_mask_0 & io_commit_uops_0_ppred_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_97 = flush_commit_mask_1 & io_commit_uops_1_ppred_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_98 = _flush_uop_T_96 | _flush_uop_T_97; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_33 = _flush_uop_T_98; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_ppred_busy = _flush_uop_WIRE_33; // @[Mux.scala:30:73]
wire _flush_uop_T_99 = flush_commit_mask_0 & io_commit_uops_0_prs3_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_100 = flush_commit_mask_1 & io_commit_uops_1_prs3_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_101 = _flush_uop_T_99 | _flush_uop_T_100; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_34 = _flush_uop_T_101; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs3_busy = _flush_uop_WIRE_34; // @[Mux.scala:30:73]
wire _flush_uop_T_102 = flush_commit_mask_0 & io_commit_uops_0_prs2_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_103 = flush_commit_mask_1 & io_commit_uops_1_prs2_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_104 = _flush_uop_T_102 | _flush_uop_T_103; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_35 = _flush_uop_T_104; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs2_busy = _flush_uop_WIRE_35; // @[Mux.scala:30:73]
wire _flush_uop_T_105 = flush_commit_mask_0 & io_commit_uops_0_prs1_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_106 = flush_commit_mask_1 & io_commit_uops_1_prs1_busy_0; // @[Mux.scala:30:73]
wire _flush_uop_T_107 = _flush_uop_T_105 | _flush_uop_T_106; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_36 = _flush_uop_T_107; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_prs1_busy = _flush_uop_WIRE_36; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_108 = flush_commit_mask_0 ? io_commit_uops_0_ppred_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_109 = flush_commit_mask_1 ? io_commit_uops_1_ppred_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_110 = _flush_uop_T_108 | _flush_uop_T_109; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_37 = _flush_uop_T_110; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ppred = _flush_uop_WIRE_37; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_111 = flush_commit_mask_0 ? io_commit_uops_0_prs3_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_112 = flush_commit_mask_1 ? io_commit_uops_1_prs3_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_113 = _flush_uop_T_111 | _flush_uop_T_112; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_38 = _flush_uop_T_113; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs3 = _flush_uop_WIRE_38; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_114 = flush_commit_mask_0 ? io_commit_uops_0_prs2_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_115 = flush_commit_mask_1 ? io_commit_uops_1_prs2_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_116 = _flush_uop_T_114 | _flush_uop_T_115; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_39 = _flush_uop_T_116; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs2 = _flush_uop_WIRE_39; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_117 = flush_commit_mask_0 ? io_commit_uops_0_prs1_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_118 = flush_commit_mask_1 ? io_commit_uops_1_prs1_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_119 = _flush_uop_T_117 | _flush_uop_T_118; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_40 = _flush_uop_T_119; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_prs1 = _flush_uop_WIRE_40; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_120 = flush_commit_mask_0 ? io_commit_uops_0_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_121 = flush_commit_mask_1 ? io_commit_uops_1_pdst_0 : 7'h0; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_T_122 = _flush_uop_T_120 | _flush_uop_T_121; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_41 = _flush_uop_T_122; // @[Mux.scala:30:73]
wire [6:0] _flush_uop_WIRE_pdst = _flush_uop_WIRE_41; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_123 = flush_commit_mask_0 ? io_commit_uops_0_rxq_idx_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_124 = flush_commit_mask_1 ? io_commit_uops_1_rxq_idx_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_125 = _flush_uop_T_123 | _flush_uop_T_124; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_42 = _flush_uop_T_125; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_rxq_idx = _flush_uop_WIRE_42; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_126 = flush_commit_mask_0 ? io_commit_uops_0_stq_idx_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_127 = flush_commit_mask_1 ? io_commit_uops_1_stq_idx_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_128 = _flush_uop_T_126 | _flush_uop_T_127; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_43 = _flush_uop_T_128; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_stq_idx = _flush_uop_WIRE_43; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_129 = flush_commit_mask_0 ? io_commit_uops_0_ldq_idx_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_130 = flush_commit_mask_1 ? io_commit_uops_1_ldq_idx_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_131 = _flush_uop_T_129 | _flush_uop_T_130; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_44 = _flush_uop_T_131; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_ldq_idx = _flush_uop_WIRE_44; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_132 = flush_commit_mask_0 ? io_commit_uops_0_rob_idx_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_133 = flush_commit_mask_1 ? io_commit_uops_1_rob_idx_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_134 = _flush_uop_T_132 | _flush_uop_T_133; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_45 = _flush_uop_T_134; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_rob_idx = _flush_uop_WIRE_45; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_63; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_ldst = _flush_uop_WIRE_46_ldst; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_62; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_wen = _flush_uop_WIRE_46_wen; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_61; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_ren1 = _flush_uop_WIRE_46_ren1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_60; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_ren2 = _flush_uop_WIRE_46_ren2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_59; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_ren3 = _flush_uop_WIRE_46_ren3; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_58; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_swap12 = _flush_uop_WIRE_46_swap12; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_57; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_swap23 = _flush_uop_WIRE_46_swap23; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_56; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_fp_ctrl_typeTagIn = _flush_uop_WIRE_46_typeTagIn; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_55; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_fp_ctrl_typeTagOut = _flush_uop_WIRE_46_typeTagOut; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_54; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_fromint = _flush_uop_WIRE_46_fromint; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_53; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_toint = _flush_uop_WIRE_46_toint; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_52; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_fastpipe = _flush_uop_WIRE_46_fastpipe; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_51; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_fma = _flush_uop_WIRE_46_fma; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_50; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_div = _flush_uop_WIRE_46_div; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_49; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_sqrt = _flush_uop_WIRE_46_sqrt; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_48; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_wflags = _flush_uop_WIRE_46_wflags; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_47; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fp_ctrl_vec = _flush_uop_WIRE_46_vec; // @[Mux.scala:30:73]
wire _flush_uop_T_135 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_vec_0; // @[Mux.scala:30:73]
wire _flush_uop_T_136 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_vec_0; // @[Mux.scala:30:73]
wire _flush_uop_T_137 = _flush_uop_T_135 | _flush_uop_T_136; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_47 = _flush_uop_T_137; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_vec = _flush_uop_WIRE_47; // @[Mux.scala:30:73]
wire _flush_uop_T_138 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_wflags_0; // @[Mux.scala:30:73]
wire _flush_uop_T_139 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_wflags_0; // @[Mux.scala:30:73]
wire _flush_uop_T_140 = _flush_uop_T_138 | _flush_uop_T_139; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_48 = _flush_uop_T_140; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_wflags = _flush_uop_WIRE_48; // @[Mux.scala:30:73]
wire _flush_uop_T_141 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_sqrt_0; // @[Mux.scala:30:73]
wire _flush_uop_T_142 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_sqrt_0; // @[Mux.scala:30:73]
wire _flush_uop_T_143 = _flush_uop_T_141 | _flush_uop_T_142; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_49 = _flush_uop_T_143; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_sqrt = _flush_uop_WIRE_49; // @[Mux.scala:30:73]
wire _flush_uop_T_144 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_div_0; // @[Mux.scala:30:73]
wire _flush_uop_T_145 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_div_0; // @[Mux.scala:30:73]
wire _flush_uop_T_146 = _flush_uop_T_144 | _flush_uop_T_145; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_50 = _flush_uop_T_146; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_div = _flush_uop_WIRE_50; // @[Mux.scala:30:73]
wire _flush_uop_T_147 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_fma_0; // @[Mux.scala:30:73]
wire _flush_uop_T_148 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_fma_0; // @[Mux.scala:30:73]
wire _flush_uop_T_149 = _flush_uop_T_147 | _flush_uop_T_148; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_51 = _flush_uop_T_149; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_fma = _flush_uop_WIRE_51; // @[Mux.scala:30:73]
wire _flush_uop_T_150 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_fastpipe_0; // @[Mux.scala:30:73]
wire _flush_uop_T_151 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_fastpipe_0; // @[Mux.scala:30:73]
wire _flush_uop_T_152 = _flush_uop_T_150 | _flush_uop_T_151; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_52 = _flush_uop_T_152; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_fastpipe = _flush_uop_WIRE_52; // @[Mux.scala:30:73]
wire _flush_uop_T_153 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_toint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_154 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_toint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_155 = _flush_uop_T_153 | _flush_uop_T_154; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_53 = _flush_uop_T_155; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_toint = _flush_uop_WIRE_53; // @[Mux.scala:30:73]
wire _flush_uop_T_156 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_fromint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_157 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_fromint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_158 = _flush_uop_T_156 | _flush_uop_T_157; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_54 = _flush_uop_T_158; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_fromint = _flush_uop_WIRE_54; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_159 = flush_commit_mask_0 ? io_commit_uops_0_fp_ctrl_typeTagOut_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_160 = flush_commit_mask_1 ? io_commit_uops_1_fp_ctrl_typeTagOut_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_161 = _flush_uop_T_159 | _flush_uop_T_160; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_55 = _flush_uop_T_161; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_typeTagOut = _flush_uop_WIRE_55; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_162 = flush_commit_mask_0 ? io_commit_uops_0_fp_ctrl_typeTagIn_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_163 = flush_commit_mask_1 ? io_commit_uops_1_fp_ctrl_typeTagIn_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_164 = _flush_uop_T_162 | _flush_uop_T_163; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_56 = _flush_uop_T_164; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_typeTagIn = _flush_uop_WIRE_56; // @[Mux.scala:30:73]
wire _flush_uop_T_165 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_swap23_0; // @[Mux.scala:30:73]
wire _flush_uop_T_166 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_swap23_0; // @[Mux.scala:30:73]
wire _flush_uop_T_167 = _flush_uop_T_165 | _flush_uop_T_166; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_57 = _flush_uop_T_167; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_swap23 = _flush_uop_WIRE_57; // @[Mux.scala:30:73]
wire _flush_uop_T_168 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_swap12_0; // @[Mux.scala:30:73]
wire _flush_uop_T_169 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_swap12_0; // @[Mux.scala:30:73]
wire _flush_uop_T_170 = _flush_uop_T_168 | _flush_uop_T_169; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_58 = _flush_uop_T_170; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_swap12 = _flush_uop_WIRE_58; // @[Mux.scala:30:73]
wire _flush_uop_T_171 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_ren3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_172 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_ren3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_173 = _flush_uop_T_171 | _flush_uop_T_172; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_59 = _flush_uop_T_173; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_ren3 = _flush_uop_WIRE_59; // @[Mux.scala:30:73]
wire _flush_uop_T_174 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_ren2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_175 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_ren2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_176 = _flush_uop_T_174 | _flush_uop_T_175; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_60 = _flush_uop_T_176; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_ren2 = _flush_uop_WIRE_60; // @[Mux.scala:30:73]
wire _flush_uop_T_177 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_ren1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_178 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_ren1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_179 = _flush_uop_T_177 | _flush_uop_T_178; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_61 = _flush_uop_T_179; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_ren1 = _flush_uop_WIRE_61; // @[Mux.scala:30:73]
wire _flush_uop_T_180 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_wen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_181 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_wen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_182 = _flush_uop_T_180 | _flush_uop_T_181; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_62 = _flush_uop_T_182; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_wen = _flush_uop_WIRE_62; // @[Mux.scala:30:73]
wire _flush_uop_T_183 = flush_commit_mask_0 & io_commit_uops_0_fp_ctrl_ldst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_184 = flush_commit_mask_1 & io_commit_uops_1_fp_ctrl_ldst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_185 = _flush_uop_T_183 | _flush_uop_T_184; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_63 = _flush_uop_T_185; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_46_ldst = _flush_uop_WIRE_63; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_186 = flush_commit_mask_0 ? io_commit_uops_0_op2_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_187 = flush_commit_mask_1 ? io_commit_uops_1_op2_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_188 = _flush_uop_T_186 | _flush_uop_T_187; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_64 = _flush_uop_T_188; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_op2_sel = _flush_uop_WIRE_64; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_189 = flush_commit_mask_0 ? io_commit_uops_0_op1_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_190 = flush_commit_mask_1 ? io_commit_uops_1_op1_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_191 = _flush_uop_T_189 | _flush_uop_T_190; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_65 = _flush_uop_T_191; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_op1_sel = _flush_uop_WIRE_65; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_192 = flush_commit_mask_0 ? io_commit_uops_0_imm_packed_0 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_193 = flush_commit_mask_1 ? io_commit_uops_1_imm_packed_0 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_T_194 = _flush_uop_T_192 | _flush_uop_T_193; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_66 = _flush_uop_T_194; // @[Mux.scala:30:73]
wire [19:0] _flush_uop_WIRE_imm_packed = _flush_uop_WIRE_66; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_195 = flush_commit_mask_0 ? io_commit_uops_0_pimm_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_196 = flush_commit_mask_1 ? io_commit_uops_1_pimm_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_197 = _flush_uop_T_195 | _flush_uop_T_196; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_67 = _flush_uop_T_197; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_pimm = _flush_uop_WIRE_67; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_198 = flush_commit_mask_0 ? io_commit_uops_0_imm_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_199 = flush_commit_mask_1 ? io_commit_uops_1_imm_sel_0 : 3'h0; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_T_200 = _flush_uop_T_198 | _flush_uop_T_199; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_68 = _flush_uop_T_200; // @[Mux.scala:30:73]
wire [2:0] _flush_uop_WIRE_imm_sel = _flush_uop_WIRE_68; // @[Mux.scala:30:73]
wire _flush_uop_T_201 = flush_commit_mask_0 & io_commit_uops_0_imm_rename_0; // @[Mux.scala:30:73]
wire _flush_uop_T_202 = flush_commit_mask_1 & io_commit_uops_1_imm_rename_0; // @[Mux.scala:30:73]
wire _flush_uop_T_203 = _flush_uop_T_201 | _flush_uop_T_202; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_69 = _flush_uop_T_203; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_imm_rename = _flush_uop_WIRE_69; // @[Mux.scala:30:73]
wire _flush_uop_T_204 = flush_commit_mask_0 & io_commit_uops_0_taken_0; // @[Mux.scala:30:73]
wire _flush_uop_T_205 = flush_commit_mask_1 & io_commit_uops_1_taken_0; // @[Mux.scala:30:73]
wire _flush_uop_T_206 = _flush_uop_T_204 | _flush_uop_T_205; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_70 = _flush_uop_T_206; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_taken = _flush_uop_WIRE_70; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_207 = flush_commit_mask_0 ? io_commit_uops_0_pc_lob_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_208 = flush_commit_mask_1 ? io_commit_uops_1_pc_lob_0 : 6'h0; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_T_209 = _flush_uop_T_207 | _flush_uop_T_208; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_71 = _flush_uop_T_209; // @[Mux.scala:30:73]
wire [5:0] _flush_uop_WIRE_pc_lob = _flush_uop_WIRE_71; // @[Mux.scala:30:73]
wire _flush_uop_T_210 = flush_commit_mask_0 & io_commit_uops_0_edge_inst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_211 = flush_commit_mask_1 & io_commit_uops_1_edge_inst_0; // @[Mux.scala:30:73]
wire _flush_uop_T_212 = _flush_uop_T_210 | _flush_uop_T_211; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_72 = _flush_uop_T_212; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_edge_inst = _flush_uop_WIRE_72; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_213 = flush_commit_mask_0 ? io_commit_uops_0_ftq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_214 = flush_commit_mask_1 ? io_commit_uops_1_ftq_idx_0 : 5'h0; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_T_215 = _flush_uop_T_213 | _flush_uop_T_214; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_73 = _flush_uop_T_215; // @[Mux.scala:30:73]
wire [4:0] _flush_uop_WIRE_ftq_idx = _flush_uop_WIRE_73; // @[Mux.scala:30:73]
wire _flush_uop_T_216 = flush_commit_mask_0 & io_commit_uops_0_is_mov_0; // @[Mux.scala:30:73]
wire _flush_uop_T_217 = flush_commit_mask_1 & io_commit_uops_1_is_mov_0; // @[Mux.scala:30:73]
wire _flush_uop_T_218 = _flush_uop_T_216 | _flush_uop_T_217; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_74 = _flush_uop_T_218; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_mov = _flush_uop_WIRE_74; // @[Mux.scala:30:73]
wire _flush_uop_T_219 = flush_commit_mask_0 & io_commit_uops_0_is_rocc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_220 = flush_commit_mask_1 & io_commit_uops_1_is_rocc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_221 = _flush_uop_T_219 | _flush_uop_T_220; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_75 = _flush_uop_T_221; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_rocc = _flush_uop_WIRE_75; // @[Mux.scala:30:73]
wire _flush_uop_T_222 = flush_commit_mask_0 & io_commit_uops_0_is_sys_pc2epc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_223 = flush_commit_mask_1 & io_commit_uops_1_is_sys_pc2epc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_224 = _flush_uop_T_222 | _flush_uop_T_223; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_76 = _flush_uop_T_224; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_sys_pc2epc = _flush_uop_WIRE_76; // @[Mux.scala:30:73]
wire _flush_uop_T_225 = flush_commit_mask_0 & io_commit_uops_0_is_eret_0; // @[Mux.scala:30:73]
wire _flush_uop_T_226 = flush_commit_mask_1 & io_commit_uops_1_is_eret_0; // @[Mux.scala:30:73]
wire _flush_uop_T_227 = _flush_uop_T_225 | _flush_uop_T_226; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_77 = _flush_uop_T_227; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_eret = _flush_uop_WIRE_77; // @[Mux.scala:30:73]
wire _flush_uop_T_228 = flush_commit_mask_0 & io_commit_uops_0_is_amo_0; // @[Mux.scala:30:73]
wire _flush_uop_T_229 = flush_commit_mask_1 & io_commit_uops_1_is_amo_0; // @[Mux.scala:30:73]
wire _flush_uop_T_230 = _flush_uop_T_228 | _flush_uop_T_229; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_78 = _flush_uop_T_230; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_amo = _flush_uop_WIRE_78; // @[Mux.scala:30:73]
wire _flush_uop_T_231 = flush_commit_mask_0 & io_commit_uops_0_is_sfence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_232 = flush_commit_mask_1 & io_commit_uops_1_is_sfence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_233 = _flush_uop_T_231 | _flush_uop_T_232; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_79 = _flush_uop_T_233; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_sfence = _flush_uop_WIRE_79; // @[Mux.scala:30:73]
wire _flush_uop_T_234 = flush_commit_mask_0 & io_commit_uops_0_is_fencei_0; // @[Mux.scala:30:73]
wire _flush_uop_T_235 = flush_commit_mask_1 & io_commit_uops_1_is_fencei_0; // @[Mux.scala:30:73]
wire _flush_uop_T_236 = _flush_uop_T_234 | _flush_uop_T_235; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_80 = _flush_uop_T_236; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_fencei = _flush_uop_WIRE_80; // @[Mux.scala:30:73]
wire _flush_uop_T_237 = flush_commit_mask_0 & io_commit_uops_0_is_fence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_238 = flush_commit_mask_1 & io_commit_uops_1_is_fence_0; // @[Mux.scala:30:73]
wire _flush_uop_T_239 = _flush_uop_T_237 | _flush_uop_T_238; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_81 = _flush_uop_T_239; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_fence = _flush_uop_WIRE_81; // @[Mux.scala:30:73]
wire _flush_uop_T_240 = flush_commit_mask_0 & io_commit_uops_0_is_sfb_0; // @[Mux.scala:30:73]
wire _flush_uop_T_241 = flush_commit_mask_1 & io_commit_uops_1_is_sfb_0; // @[Mux.scala:30:73]
wire _flush_uop_T_242 = _flush_uop_T_240 | _flush_uop_T_241; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_82 = _flush_uop_T_242; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_sfb = _flush_uop_WIRE_82; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_243 = flush_commit_mask_0 ? io_commit_uops_0_br_type_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_244 = flush_commit_mask_1 ? io_commit_uops_1_br_type_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_245 = _flush_uop_T_243 | _flush_uop_T_244; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_83 = _flush_uop_T_245; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_br_type = _flush_uop_WIRE_83; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_246 = flush_commit_mask_0 ? io_commit_uops_0_br_tag_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_247 = flush_commit_mask_1 ? io_commit_uops_1_br_tag_0 : 4'h0; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_T_248 = _flush_uop_T_246 | _flush_uop_T_247; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_84 = _flush_uop_T_248; // @[Mux.scala:30:73]
wire [3:0] _flush_uop_WIRE_br_tag = _flush_uop_WIRE_84; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_249 = flush_commit_mask_0 ? io_commit_uops_0_br_mask_0 : 12'h0; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_250 = flush_commit_mask_1 ? io_commit_uops_1_br_mask_0 : 12'h0; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_T_251 = _flush_uop_T_249 | _flush_uop_T_250; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_85 = _flush_uop_T_251; // @[Mux.scala:30:73]
wire [11:0] _flush_uop_WIRE_br_mask = _flush_uop_WIRE_85; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_252 = flush_commit_mask_0 ? io_commit_uops_0_dis_col_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_253 = flush_commit_mask_1 ? io_commit_uops_1_dis_col_sel_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_254 = _flush_uop_T_252 | _flush_uop_T_253; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_86 = _flush_uop_T_254; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_dis_col_sel = _flush_uop_WIRE_86; // @[Mux.scala:30:73]
wire _flush_uop_T_255 = flush_commit_mask_0 & io_commit_uops_0_iw_p3_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_256 = flush_commit_mask_1 & io_commit_uops_1_iw_p3_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_257 = _flush_uop_T_255 | _flush_uop_T_256; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_87 = _flush_uop_T_257; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_p3_bypass_hint = _flush_uop_WIRE_87; // @[Mux.scala:30:73]
wire _flush_uop_T_258 = flush_commit_mask_0 & io_commit_uops_0_iw_p2_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_259 = flush_commit_mask_1 & io_commit_uops_1_iw_p2_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_260 = _flush_uop_T_258 | _flush_uop_T_259; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_88 = _flush_uop_T_260; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_p2_bypass_hint = _flush_uop_WIRE_88; // @[Mux.scala:30:73]
wire _flush_uop_T_261 = flush_commit_mask_0 & io_commit_uops_0_iw_p1_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_262 = flush_commit_mask_1 & io_commit_uops_1_iw_p1_bypass_hint_0; // @[Mux.scala:30:73]
wire _flush_uop_T_263 = _flush_uop_T_261 | _flush_uop_T_262; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_89 = _flush_uop_T_263; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_p1_bypass_hint = _flush_uop_WIRE_89; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_264 = flush_commit_mask_0 ? io_commit_uops_0_iw_p2_speculative_child_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_265 = flush_commit_mask_1 ? io_commit_uops_1_iw_p2_speculative_child_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_266 = _flush_uop_T_264 | _flush_uop_T_265; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_90 = _flush_uop_T_266; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_iw_p2_speculative_child = _flush_uop_WIRE_90; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_267 = flush_commit_mask_0 ? io_commit_uops_0_iw_p1_speculative_child_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_268 = flush_commit_mask_1 ? io_commit_uops_1_iw_p1_speculative_child_0 : 2'h0; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_T_269 = _flush_uop_T_267 | _flush_uop_T_268; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_91 = _flush_uop_T_269; // @[Mux.scala:30:73]
wire [1:0] _flush_uop_WIRE_iw_p1_speculative_child = _flush_uop_WIRE_91; // @[Mux.scala:30:73]
wire _flush_uop_T_270 = flush_commit_mask_0 & io_commit_uops_0_iw_issued_partial_dgen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_271 = flush_commit_mask_1 & io_commit_uops_1_iw_issued_partial_dgen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_272 = _flush_uop_T_270 | _flush_uop_T_271; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_92 = _flush_uop_T_272; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_issued_partial_dgen = _flush_uop_WIRE_92; // @[Mux.scala:30:73]
wire _flush_uop_T_273 = flush_commit_mask_0 & io_commit_uops_0_iw_issued_partial_agen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_274 = flush_commit_mask_1 & io_commit_uops_1_iw_issued_partial_agen_0; // @[Mux.scala:30:73]
wire _flush_uop_T_275 = _flush_uop_T_273 | _flush_uop_T_274; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_93 = _flush_uop_T_275; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_issued_partial_agen = _flush_uop_WIRE_93; // @[Mux.scala:30:73]
wire _flush_uop_T_276 = flush_commit_mask_0 & io_commit_uops_0_iw_issued_0; // @[Mux.scala:30:73]
wire _flush_uop_T_277 = flush_commit_mask_1 & io_commit_uops_1_iw_issued_0; // @[Mux.scala:30:73]
wire _flush_uop_T_278 = _flush_uop_T_276 | _flush_uop_T_277; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_94 = _flush_uop_T_278; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iw_issued = _flush_uop_WIRE_94; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_96; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_0 = _flush_uop_WIRE_95_0; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_97; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_1 = _flush_uop_WIRE_95_1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_98; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_2 = _flush_uop_WIRE_95_2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_99; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_3 = _flush_uop_WIRE_95_3; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_100; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_4 = _flush_uop_WIRE_95_4; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_101; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_5 = _flush_uop_WIRE_95_5; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_102; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_6 = _flush_uop_WIRE_95_6; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_103; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_7 = _flush_uop_WIRE_95_7; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_104; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_8 = _flush_uop_WIRE_95_8; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_105; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_fu_code_9 = _flush_uop_WIRE_95_9; // @[Mux.scala:30:73]
wire _flush_uop_T_279 = flush_commit_mask_0 & io_commit_uops_0_fu_code_0_0; // @[Mux.scala:30:73]
wire _flush_uop_T_280 = flush_commit_mask_1 & io_commit_uops_1_fu_code_0_0; // @[Mux.scala:30:73]
wire _flush_uop_T_281 = _flush_uop_T_279 | _flush_uop_T_280; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_96 = _flush_uop_T_281; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_0 = _flush_uop_WIRE_96; // @[Mux.scala:30:73]
wire _flush_uop_T_282 = flush_commit_mask_0 & io_commit_uops_0_fu_code_1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_283 = flush_commit_mask_1 & io_commit_uops_1_fu_code_1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_284 = _flush_uop_T_282 | _flush_uop_T_283; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_97 = _flush_uop_T_284; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_1 = _flush_uop_WIRE_97; // @[Mux.scala:30:73]
wire _flush_uop_T_285 = flush_commit_mask_0 & io_commit_uops_0_fu_code_2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_286 = flush_commit_mask_1 & io_commit_uops_1_fu_code_2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_287 = _flush_uop_T_285 | _flush_uop_T_286; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_98 = _flush_uop_T_287; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_2 = _flush_uop_WIRE_98; // @[Mux.scala:30:73]
wire _flush_uop_T_288 = flush_commit_mask_0 & io_commit_uops_0_fu_code_3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_289 = flush_commit_mask_1 & io_commit_uops_1_fu_code_3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_290 = _flush_uop_T_288 | _flush_uop_T_289; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_99 = _flush_uop_T_290; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_3 = _flush_uop_WIRE_99; // @[Mux.scala:30:73]
wire _flush_uop_T_291 = flush_commit_mask_0 & io_commit_uops_0_fu_code_4_0; // @[Mux.scala:30:73]
wire _flush_uop_T_292 = flush_commit_mask_1 & io_commit_uops_1_fu_code_4_0; // @[Mux.scala:30:73]
wire _flush_uop_T_293 = _flush_uop_T_291 | _flush_uop_T_292; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_100 = _flush_uop_T_293; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_4 = _flush_uop_WIRE_100; // @[Mux.scala:30:73]
wire _flush_uop_T_294 = flush_commit_mask_0 & io_commit_uops_0_fu_code_5_0; // @[Mux.scala:30:73]
wire _flush_uop_T_295 = flush_commit_mask_1 & io_commit_uops_1_fu_code_5_0; // @[Mux.scala:30:73]
wire _flush_uop_T_296 = _flush_uop_T_294 | _flush_uop_T_295; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_101 = _flush_uop_T_296; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_5 = _flush_uop_WIRE_101; // @[Mux.scala:30:73]
wire _flush_uop_T_297 = flush_commit_mask_0 & io_commit_uops_0_fu_code_6_0; // @[Mux.scala:30:73]
wire _flush_uop_T_298 = flush_commit_mask_1 & io_commit_uops_1_fu_code_6_0; // @[Mux.scala:30:73]
wire _flush_uop_T_299 = _flush_uop_T_297 | _flush_uop_T_298; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_102 = _flush_uop_T_299; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_6 = _flush_uop_WIRE_102; // @[Mux.scala:30:73]
wire _flush_uop_T_300 = flush_commit_mask_0 & io_commit_uops_0_fu_code_7_0; // @[Mux.scala:30:73]
wire _flush_uop_T_301 = flush_commit_mask_1 & io_commit_uops_1_fu_code_7_0; // @[Mux.scala:30:73]
wire _flush_uop_T_302 = _flush_uop_T_300 | _flush_uop_T_301; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_103 = _flush_uop_T_302; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_7 = _flush_uop_WIRE_103; // @[Mux.scala:30:73]
wire _flush_uop_T_303 = flush_commit_mask_0 & io_commit_uops_0_fu_code_8_0; // @[Mux.scala:30:73]
wire _flush_uop_T_304 = flush_commit_mask_1 & io_commit_uops_1_fu_code_8_0; // @[Mux.scala:30:73]
wire _flush_uop_T_305 = _flush_uop_T_303 | _flush_uop_T_304; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_104 = _flush_uop_T_305; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_8 = _flush_uop_WIRE_104; // @[Mux.scala:30:73]
wire _flush_uop_T_306 = flush_commit_mask_0 & io_commit_uops_0_fu_code_9_0; // @[Mux.scala:30:73]
wire _flush_uop_T_307 = flush_commit_mask_1 & io_commit_uops_1_fu_code_9_0; // @[Mux.scala:30:73]
wire _flush_uop_T_308 = _flush_uop_T_306 | _flush_uop_T_307; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_105 = _flush_uop_T_308; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_95_9 = _flush_uop_WIRE_105; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_107; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iq_type_0 = _flush_uop_WIRE_106_0; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_108; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iq_type_1 = _flush_uop_WIRE_106_1; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_109; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iq_type_2 = _flush_uop_WIRE_106_2; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_110; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_iq_type_3 = _flush_uop_WIRE_106_3; // @[Mux.scala:30:73]
wire _flush_uop_T_309 = flush_commit_mask_0 & io_commit_uops_0_iq_type_0_0; // @[Mux.scala:30:73]
wire _flush_uop_T_310 = flush_commit_mask_1 & io_commit_uops_1_iq_type_0_0; // @[Mux.scala:30:73]
wire _flush_uop_T_311 = _flush_uop_T_309 | _flush_uop_T_310; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_107 = _flush_uop_T_311; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_106_0 = _flush_uop_WIRE_107; // @[Mux.scala:30:73]
wire _flush_uop_T_312 = flush_commit_mask_0 & io_commit_uops_0_iq_type_1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_313 = flush_commit_mask_1 & io_commit_uops_1_iq_type_1_0; // @[Mux.scala:30:73]
wire _flush_uop_T_314 = _flush_uop_T_312 | _flush_uop_T_313; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_108 = _flush_uop_T_314; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_106_1 = _flush_uop_WIRE_108; // @[Mux.scala:30:73]
wire _flush_uop_T_315 = flush_commit_mask_0 & io_commit_uops_0_iq_type_2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_316 = flush_commit_mask_1 & io_commit_uops_1_iq_type_2_0; // @[Mux.scala:30:73]
wire _flush_uop_T_317 = _flush_uop_T_315 | _flush_uop_T_316; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_109 = _flush_uop_T_317; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_106_2 = _flush_uop_WIRE_109; // @[Mux.scala:30:73]
wire _flush_uop_T_318 = flush_commit_mask_0 & io_commit_uops_0_iq_type_3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_319 = flush_commit_mask_1 & io_commit_uops_1_iq_type_3_0; // @[Mux.scala:30:73]
wire _flush_uop_T_320 = _flush_uop_T_318 | _flush_uop_T_319; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_110 = _flush_uop_T_320; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_106_3 = _flush_uop_WIRE_110; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_321 = flush_commit_mask_0 ? io_commit_uops_0_debug_pc_0 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_322 = flush_commit_mask_1 ? io_commit_uops_1_debug_pc_0 : 40'h0; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_T_323 = _flush_uop_T_321 | _flush_uop_T_322; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_111 = _flush_uop_T_323; // @[Mux.scala:30:73]
wire [39:0] _flush_uop_WIRE_debug_pc = _flush_uop_WIRE_111; // @[Mux.scala:30:73]
wire _flush_uop_T_324 = flush_commit_mask_0 & io_commit_uops_0_is_rvc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_325 = flush_commit_mask_1 & io_commit_uops_1_is_rvc_0; // @[Mux.scala:30:73]
wire _flush_uop_T_326 = _flush_uop_T_324 | _flush_uop_T_325; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_112 = _flush_uop_T_326; // @[Mux.scala:30:73]
wire _flush_uop_WIRE_is_rvc = _flush_uop_WIRE_112; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_327 = flush_commit_mask_0 ? io_commit_uops_0_debug_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_328 = flush_commit_mask_1 ? io_commit_uops_1_debug_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_329 = _flush_uop_T_327 | _flush_uop_T_328; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_113 = _flush_uop_T_329; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_debug_inst = _flush_uop_WIRE_113; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_330 = flush_commit_mask_0 ? io_commit_uops_0_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_331 = flush_commit_mask_1 ? io_commit_uops_1_inst_0 : 32'h0; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_T_332 = _flush_uop_T_330 | _flush_uop_T_331; // @[Mux.scala:30:73]
assign _flush_uop_WIRE_114 = _flush_uop_T_332; // @[Mux.scala:30:73]
wire [31:0] _flush_uop_WIRE_inst = _flush_uop_WIRE_114; // @[Mux.scala:30:73]
wire [31:0] flush_uop_inst = exception_thrown ? com_xcpt_uop_inst : _flush_uop_WIRE_inst; // @[Mux.scala:30:73, :50:70]
wire [31:0] flush_uop_debug_inst = exception_thrown ? com_xcpt_uop_debug_inst : _flush_uop_WIRE_debug_inst; // @[Mux.scala:30:73, :50:70]
assign flush_uop_is_rvc = exception_thrown ? com_xcpt_uop_is_rvc : _flush_uop_WIRE_is_rvc; // @[Mux.scala:30:73, :50:70]
wire [39:0] flush_uop_debug_pc = exception_thrown ? com_xcpt_uop_debug_pc : _flush_uop_WIRE_debug_pc; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iq_type_0 = exception_thrown ? com_xcpt_uop_iq_type_0 : _flush_uop_WIRE_iq_type_0; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iq_type_1 = exception_thrown ? com_xcpt_uop_iq_type_1 : _flush_uop_WIRE_iq_type_1; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iq_type_2 = exception_thrown ? com_xcpt_uop_iq_type_2 : _flush_uop_WIRE_iq_type_2; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iq_type_3 = exception_thrown ? com_xcpt_uop_iq_type_3 : _flush_uop_WIRE_iq_type_3; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_0 = exception_thrown ? com_xcpt_uop_fu_code_0 : _flush_uop_WIRE_fu_code_0; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_1 = exception_thrown ? com_xcpt_uop_fu_code_1 : _flush_uop_WIRE_fu_code_1; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_2 = exception_thrown ? com_xcpt_uop_fu_code_2 : _flush_uop_WIRE_fu_code_2; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_3 = exception_thrown ? com_xcpt_uop_fu_code_3 : _flush_uop_WIRE_fu_code_3; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_4 = exception_thrown ? com_xcpt_uop_fu_code_4 : _flush_uop_WIRE_fu_code_4; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_5 = exception_thrown ? com_xcpt_uop_fu_code_5 : _flush_uop_WIRE_fu_code_5; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_6 = exception_thrown ? com_xcpt_uop_fu_code_6 : _flush_uop_WIRE_fu_code_6; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_7 = exception_thrown ? com_xcpt_uop_fu_code_7 : _flush_uop_WIRE_fu_code_7; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_8 = exception_thrown ? com_xcpt_uop_fu_code_8 : _flush_uop_WIRE_fu_code_8; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fu_code_9 = exception_thrown ? com_xcpt_uop_fu_code_9 : _flush_uop_WIRE_fu_code_9; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_issued = exception_thrown ? com_xcpt_uop_iw_issued : _flush_uop_WIRE_iw_issued; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_issued_partial_agen = exception_thrown ? com_xcpt_uop_iw_issued_partial_agen : _flush_uop_WIRE_iw_issued_partial_agen; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_issued_partial_dgen = exception_thrown ? com_xcpt_uop_iw_issued_partial_dgen : _flush_uop_WIRE_iw_issued_partial_dgen; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_iw_p1_speculative_child = exception_thrown ? com_xcpt_uop_iw_p1_speculative_child : _flush_uop_WIRE_iw_p1_speculative_child; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_iw_p2_speculative_child = exception_thrown ? com_xcpt_uop_iw_p2_speculative_child : _flush_uop_WIRE_iw_p2_speculative_child; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_p1_bypass_hint = exception_thrown ? com_xcpt_uop_iw_p1_bypass_hint : _flush_uop_WIRE_iw_p1_bypass_hint; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_p2_bypass_hint = exception_thrown ? com_xcpt_uop_iw_p2_bypass_hint : _flush_uop_WIRE_iw_p2_bypass_hint; // @[Mux.scala:30:73, :50:70]
wire flush_uop_iw_p3_bypass_hint = exception_thrown ? com_xcpt_uop_iw_p3_bypass_hint : _flush_uop_WIRE_iw_p3_bypass_hint; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_dis_col_sel = exception_thrown ? com_xcpt_uop_dis_col_sel : _flush_uop_WIRE_dis_col_sel; // @[Mux.scala:30:73, :50:70]
wire [11:0] flush_uop_br_mask = exception_thrown ? com_xcpt_uop_br_mask : _flush_uop_WIRE_br_mask; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_br_tag = exception_thrown ? com_xcpt_uop_br_tag : _flush_uop_WIRE_br_tag; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_br_type = exception_thrown ? com_xcpt_uop_br_type : _flush_uop_WIRE_br_type; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_sfb = exception_thrown ? com_xcpt_uop_is_sfb : _flush_uop_WIRE_is_sfb; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_fence = exception_thrown ? com_xcpt_uop_is_fence : _flush_uop_WIRE_is_fence; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_fencei = exception_thrown ? com_xcpt_uop_is_fencei : _flush_uop_WIRE_is_fencei; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_sfence = exception_thrown ? com_xcpt_uop_is_sfence : _flush_uop_WIRE_is_sfence; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_amo = exception_thrown ? com_xcpt_uop_is_amo : _flush_uop_WIRE_is_amo; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_eret = exception_thrown ? com_xcpt_uop_is_eret : _flush_uop_WIRE_is_eret; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_sys_pc2epc = exception_thrown ? com_xcpt_uop_is_sys_pc2epc : _flush_uop_WIRE_is_sys_pc2epc; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_rocc = exception_thrown ? com_xcpt_uop_is_rocc : _flush_uop_WIRE_is_rocc; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_mov = exception_thrown ? com_xcpt_uop_is_mov : _flush_uop_WIRE_is_mov; // @[Mux.scala:30:73, :50:70]
assign flush_uop_ftq_idx = exception_thrown ? com_xcpt_uop_ftq_idx : _flush_uop_WIRE_ftq_idx; // @[Mux.scala:30:73, :50:70]
assign flush_uop_edge_inst = exception_thrown ? com_xcpt_uop_edge_inst : _flush_uop_WIRE_edge_inst; // @[Mux.scala:30:73, :50:70]
assign flush_uop_pc_lob = exception_thrown ? com_xcpt_uop_pc_lob : _flush_uop_WIRE_pc_lob; // @[Mux.scala:30:73, :50:70]
wire flush_uop_taken = exception_thrown ? com_xcpt_uop_taken : _flush_uop_WIRE_taken; // @[Mux.scala:30:73, :50:70]
wire flush_uop_imm_rename = exception_thrown ? com_xcpt_uop_imm_rename : _flush_uop_WIRE_imm_rename; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_imm_sel = exception_thrown ? com_xcpt_uop_imm_sel : _flush_uop_WIRE_imm_sel; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_pimm = exception_thrown ? com_xcpt_uop_pimm : _flush_uop_WIRE_pimm; // @[Mux.scala:30:73, :50:70]
wire [19:0] flush_uop_imm_packed = exception_thrown ? com_xcpt_uop_imm_packed : _flush_uop_WIRE_imm_packed; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_op1_sel = exception_thrown ? com_xcpt_uop_op1_sel : _flush_uop_WIRE_op1_sel; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_op2_sel = exception_thrown ? com_xcpt_uop_op2_sel : _flush_uop_WIRE_op2_sel; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_ldst = exception_thrown ? com_xcpt_uop_fp_ctrl_ldst : _flush_uop_WIRE_fp_ctrl_ldst; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_wen = exception_thrown ? com_xcpt_uop_fp_ctrl_wen : _flush_uop_WIRE_fp_ctrl_wen; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_ren1 = exception_thrown ? com_xcpt_uop_fp_ctrl_ren1 : _flush_uop_WIRE_fp_ctrl_ren1; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_ren2 = exception_thrown ? com_xcpt_uop_fp_ctrl_ren2 : _flush_uop_WIRE_fp_ctrl_ren2; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_ren3 = exception_thrown ? com_xcpt_uop_fp_ctrl_ren3 : _flush_uop_WIRE_fp_ctrl_ren3; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_swap12 = exception_thrown ? com_xcpt_uop_fp_ctrl_swap12 : _flush_uop_WIRE_fp_ctrl_swap12; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_swap23 = exception_thrown ? com_xcpt_uop_fp_ctrl_swap23 : _flush_uop_WIRE_fp_ctrl_swap23; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_fp_ctrl_typeTagIn = exception_thrown ? com_xcpt_uop_fp_ctrl_typeTagIn : _flush_uop_WIRE_fp_ctrl_typeTagIn; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_fp_ctrl_typeTagOut = exception_thrown ? com_xcpt_uop_fp_ctrl_typeTagOut : _flush_uop_WIRE_fp_ctrl_typeTagOut; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_fromint = exception_thrown ? com_xcpt_uop_fp_ctrl_fromint : _flush_uop_WIRE_fp_ctrl_fromint; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_toint = exception_thrown ? com_xcpt_uop_fp_ctrl_toint : _flush_uop_WIRE_fp_ctrl_toint; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_fastpipe = exception_thrown ? com_xcpt_uop_fp_ctrl_fastpipe : _flush_uop_WIRE_fp_ctrl_fastpipe; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_fma = exception_thrown ? com_xcpt_uop_fp_ctrl_fma : _flush_uop_WIRE_fp_ctrl_fma; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_div = exception_thrown ? com_xcpt_uop_fp_ctrl_div : _flush_uop_WIRE_fp_ctrl_div; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_sqrt = exception_thrown ? com_xcpt_uop_fp_ctrl_sqrt : _flush_uop_WIRE_fp_ctrl_sqrt; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_wflags = exception_thrown ? com_xcpt_uop_fp_ctrl_wflags : _flush_uop_WIRE_fp_ctrl_wflags; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_ctrl_vec = exception_thrown ? com_xcpt_uop_fp_ctrl_vec : _flush_uop_WIRE_fp_ctrl_vec; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_rob_idx = exception_thrown ? com_xcpt_uop_rob_idx : _flush_uop_WIRE_rob_idx; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_ldq_idx = exception_thrown ? com_xcpt_uop_ldq_idx : _flush_uop_WIRE_ldq_idx; // @[Mux.scala:30:73, :50:70]
wire [3:0] flush_uop_stq_idx = exception_thrown ? com_xcpt_uop_stq_idx : _flush_uop_WIRE_stq_idx; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_rxq_idx = exception_thrown ? com_xcpt_uop_rxq_idx : _flush_uop_WIRE_rxq_idx; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_pdst = exception_thrown ? com_xcpt_uop_pdst : _flush_uop_WIRE_pdst; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs1 = exception_thrown ? com_xcpt_uop_prs1 : _flush_uop_WIRE_prs1; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs2 = exception_thrown ? com_xcpt_uop_prs2 : _flush_uop_WIRE_prs2; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_prs3 = exception_thrown ? com_xcpt_uop_prs3 : _flush_uop_WIRE_prs3; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_ppred = exception_thrown ? com_xcpt_uop_ppred : _flush_uop_WIRE_ppred; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs1_busy = exception_thrown ? com_xcpt_uop_prs1_busy : _flush_uop_WIRE_prs1_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs2_busy = exception_thrown ? com_xcpt_uop_prs2_busy : _flush_uop_WIRE_prs2_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_prs3_busy = exception_thrown ? com_xcpt_uop_prs3_busy : _flush_uop_WIRE_prs3_busy; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ppred_busy = exception_thrown ? com_xcpt_uop_ppred_busy : _flush_uop_WIRE_ppred_busy; // @[Mux.scala:30:73, :50:70]
wire [6:0] flush_uop_stale_pdst = exception_thrown ? com_xcpt_uop_stale_pdst : _flush_uop_WIRE_stale_pdst; // @[Mux.scala:30:73, :50:70]
wire flush_uop_exception = exception_thrown ? com_xcpt_uop_exception : _flush_uop_WIRE_exception; // @[Mux.scala:30:73, :50:70]
wire [63:0] flush_uop_exc_cause = exception_thrown ? com_xcpt_uop_exc_cause : _flush_uop_WIRE_exc_cause; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_mem_cmd = exception_thrown ? com_xcpt_uop_mem_cmd : _flush_uop_WIRE_mem_cmd; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_mem_size = exception_thrown ? com_xcpt_uop_mem_size : _flush_uop_WIRE_mem_size; // @[Mux.scala:30:73, :50:70]
wire flush_uop_mem_signed = exception_thrown ? com_xcpt_uop_mem_signed : _flush_uop_WIRE_mem_signed; // @[Mux.scala:30:73, :50:70]
wire flush_uop_uses_ldq = exception_thrown ? com_xcpt_uop_uses_ldq : _flush_uop_WIRE_uses_ldq; // @[Mux.scala:30:73, :50:70]
wire flush_uop_uses_stq = exception_thrown ? com_xcpt_uop_uses_stq : _flush_uop_WIRE_uses_stq; // @[Mux.scala:30:73, :50:70]
wire flush_uop_is_unique = exception_thrown ? com_xcpt_uop_is_unique : _flush_uop_WIRE_is_unique; // @[Mux.scala:30:73, :50:70]
wire flush_uop_flush_on_commit = exception_thrown ? com_xcpt_uop_flush_on_commit : _flush_uop_WIRE_flush_on_commit; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_csr_cmd = exception_thrown ? com_xcpt_uop_csr_cmd : _flush_uop_WIRE_csr_cmd; // @[Mux.scala:30:73, :50:70]
wire flush_uop_ldst_is_rs1 = exception_thrown ? com_xcpt_uop_ldst_is_rs1 : _flush_uop_WIRE_ldst_is_rs1; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_ldst = exception_thrown ? com_xcpt_uop_ldst : _flush_uop_WIRE_ldst; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs1 = exception_thrown ? com_xcpt_uop_lrs1 : _flush_uop_WIRE_lrs1; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs2 = exception_thrown ? com_xcpt_uop_lrs2 : _flush_uop_WIRE_lrs2; // @[Mux.scala:30:73, :50:70]
wire [5:0] flush_uop_lrs3 = exception_thrown ? com_xcpt_uop_lrs3 : _flush_uop_WIRE_lrs3; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_dst_rtype = exception_thrown ? com_xcpt_uop_dst_rtype : _flush_uop_WIRE_dst_rtype; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_lrs1_rtype = exception_thrown ? com_xcpt_uop_lrs1_rtype : _flush_uop_WIRE_lrs1_rtype; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_lrs2_rtype = exception_thrown ? com_xcpt_uop_lrs2_rtype : _flush_uop_WIRE_lrs2_rtype; // @[Mux.scala:30:73, :50:70]
wire flush_uop_frs3_en = exception_thrown ? com_xcpt_uop_frs3_en : _flush_uop_WIRE_frs3_en; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fcn_dw = exception_thrown ? com_xcpt_uop_fcn_dw : _flush_uop_WIRE_fcn_dw; // @[Mux.scala:30:73, :50:70]
wire [4:0] flush_uop_fcn_op = exception_thrown ? com_xcpt_uop_fcn_op : _flush_uop_WIRE_fcn_op; // @[Mux.scala:30:73, :50:70]
wire flush_uop_fp_val = exception_thrown ? com_xcpt_uop_fp_val : _flush_uop_WIRE_fp_val; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_fp_rm = exception_thrown ? com_xcpt_uop_fp_rm : _flush_uop_WIRE_fp_rm; // @[Mux.scala:30:73, :50:70]
wire [1:0] flush_uop_fp_typ = exception_thrown ? com_xcpt_uop_fp_typ : _flush_uop_WIRE_fp_typ; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_pf_if = exception_thrown ? com_xcpt_uop_xcpt_pf_if : _flush_uop_WIRE_xcpt_pf_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_ae_if = exception_thrown ? com_xcpt_uop_xcpt_ae_if : _flush_uop_WIRE_xcpt_ae_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_xcpt_ma_if = exception_thrown ? com_xcpt_uop_xcpt_ma_if : _flush_uop_WIRE_xcpt_ma_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_bp_debug_if = exception_thrown ? com_xcpt_uop_bp_debug_if : _flush_uop_WIRE_bp_debug_if; // @[Mux.scala:30:73, :50:70]
wire flush_uop_bp_xcpt_if = exception_thrown ? com_xcpt_uop_bp_xcpt_if : _flush_uop_WIRE_bp_xcpt_if; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_debug_fsrc = exception_thrown ? com_xcpt_uop_debug_fsrc : _flush_uop_WIRE_debug_fsrc; // @[Mux.scala:30:73, :50:70]
wire [2:0] flush_uop_debug_tsrc = exception_thrown ? com_xcpt_uop_debug_tsrc : _flush_uop_WIRE_debug_tsrc; // @[Mux.scala:30:73, :50:70]
assign io_flush_bits_is_rvc_0 = flush_uop_is_rvc; // @[rob.scala:199:7, :606:22]
assign io_flush_bits_ftq_idx_0 = flush_uop_ftq_idx; // @[rob.scala:199:7, :606:22]
assign io_flush_bits_edge_inst_0 = flush_uop_edge_inst; // @[rob.scala:199:7, :606:22]
assign io_flush_bits_pc_lob_0 = flush_uop_pc_lob; // @[rob.scala:199:7, :606:22]
wire _io_flush_bits_flush_typ_T = ~is_mini_exception; // @[package.scala:81:59]
wire _io_flush_bits_flush_typ_T_1 = exception_thrown & _io_flush_bits_flush_typ_T; // @[rob.scala:240:30, :617:{66,69}]
wire _io_flush_bits_flush_typ_T_2 = flush_commit & flush_uop_is_eret; // @[rob.scala:600:48, :606:22, :618:62]
wire _io_flush_bits_flush_typ_ret_T = ~flush_val; // @[rob.scala:160:11, :601:36]
wire [2:0] _io_flush_bits_flush_typ_ret_T_1 = refetch_inst ? 3'h2 : 3'h4; // @[rob.scala:163:10, :592:39]
wire [2:0] _io_flush_bits_flush_typ_ret_T_2 = _io_flush_bits_flush_typ_T_1 ? 3'h1 : _io_flush_bits_flush_typ_ret_T_1; // @[rob.scala:162:10, :163:10, :617:66]
wire [2:0] _io_flush_bits_flush_typ_ret_T_3 = _io_flush_bits_flush_typ_T_2 ? 3'h3 : _io_flush_bits_flush_typ_ret_T_2; // @[rob.scala:161:10, :162:10, :618:62]
assign io_flush_bits_flush_typ_ret = _io_flush_bits_flush_typ_ret_T ? 3'h0 : _io_flush_bits_flush_typ_ret_T_3; // @[rob.scala:160:{10,11}, :161:10]
assign io_flush_bits_flush_typ_0 = io_flush_bits_flush_typ_ret; // @[rob.scala:160:10, :199:7]
assign _io_rollback_T = &rob_state; // @[rob.scala:207:26, :470:21, :621:28]
assign io_rollback_0 = _io_rollback_T; // @[rob.scala:199:7, :621:28]
wire _fflags_val_0_T; // @[rob.scala:631:47]
wire _fflags_val_1_T; // @[rob.scala:631:47]
wire fflags_val_0; // @[rob.scala:627:24]
wire fflags_val_1; // @[rob.scala:627:24]
wire [4:0] _fflags_0_T; // @[rob.scala:632:21]
wire [4:0] _fflags_1_T; // @[rob.scala:632:21]
wire [4:0] fflags_0; // @[rob.scala:628:24]
wire [4:0] fflags_1; // @[rob.scala:628:24]
assign _fflags_val_0_T = rob_head_fflags_0_valid & io_commit_valids_0_0; // @[rob.scala:199:7, :238:33, :631:47]
assign fflags_val_0 = _fflags_val_0_T; // @[rob.scala:627:24, :631:47]
assign _fflags_0_T = fflags_val_0 ? rob_head_fflags_0_bits : 5'h0; // @[rob.scala:238:33, :627:24, :632:21]
assign fflags_0 = _fflags_0_T; // @[rob.scala:628:24, :632:21]
assign _fflags_val_1_T = rob_head_fflags_1_valid & io_commit_valids_1_0; // @[rob.scala:199:7, :238:33, :631:47]
assign fflags_val_1 = _fflags_val_1_T; // @[rob.scala:627:24, :631:47]
assign _fflags_1_T = fflags_val_1 ? rob_head_fflags_1_bits : 5'h0; // @[rob.scala:238:33, :627:24, :632:21]
assign fflags_1 = _fflags_1_T; // @[rob.scala:628:24, :632:21]
assign _io_commit_fflags_valid_T = fflags_val_0 | fflags_val_1; // @[rob.scala:627:24, :650:48]
assign io_commit_fflags_valid_0 = _io_commit_fflags_valid_T; // @[rob.scala:199:7, :650:48]
assign _io_commit_fflags_bits_T = fflags_0 | fflags_1; // @[rob.scala:628:24, :651:44]
assign io_commit_fflags_bits_0 = _io_commit_fflags_bits_T; // @[rob.scala:199:7, :651:44]
wire next_xcpt_uop_iq_type_0; // @[rob.scala:657:27]
wire next_xcpt_uop_iq_type_1; // @[rob.scala:657:27]
wire next_xcpt_uop_iq_type_2; // @[rob.scala:657:27]
wire next_xcpt_uop_iq_type_3; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_0; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_1; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_2; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_3; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_4; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_5; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_6; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_7; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_8; // @[rob.scala:657:27]
wire next_xcpt_uop_fu_code_9; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_ldst; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_wen; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_ren1; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_ren2; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_ren3; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_swap12; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_swap23; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_fp_ctrl_typeTagIn; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_fp_ctrl_typeTagOut; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_fromint; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_toint; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_fastpipe; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_fma; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_div; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_sqrt; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_wflags; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_ctrl_vec; // @[rob.scala:657:27]
wire [31:0] next_xcpt_uop_inst; // @[rob.scala:657:27]
wire [31:0] next_xcpt_uop_debug_inst; // @[rob.scala:657:27]
wire next_xcpt_uop_is_rvc; // @[rob.scala:657:27]
wire [39:0] next_xcpt_uop_debug_pc; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_issued; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_issued_partial_agen; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_issued_partial_dgen; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_iw_p1_speculative_child; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_iw_p2_speculative_child; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_p1_bypass_hint; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_p2_bypass_hint; // @[rob.scala:657:27]
wire next_xcpt_uop_iw_p3_bypass_hint; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_dis_col_sel; // @[rob.scala:657:27]
wire [11:0] next_xcpt_uop_br_mask; // @[rob.scala:657:27]
wire [3:0] next_xcpt_uop_br_tag; // @[rob.scala:657:27]
wire [3:0] next_xcpt_uop_br_type; // @[rob.scala:657:27]
wire next_xcpt_uop_is_sfb; // @[rob.scala:657:27]
wire next_xcpt_uop_is_fence; // @[rob.scala:657:27]
wire next_xcpt_uop_is_fencei; // @[rob.scala:657:27]
wire next_xcpt_uop_is_sfence; // @[rob.scala:657:27]
wire next_xcpt_uop_is_amo; // @[rob.scala:657:27]
wire next_xcpt_uop_is_eret; // @[rob.scala:657:27]
wire next_xcpt_uop_is_sys_pc2epc; // @[rob.scala:657:27]
wire next_xcpt_uop_is_rocc; // @[rob.scala:657:27]
wire next_xcpt_uop_is_mov; // @[rob.scala:657:27]
wire [4:0] next_xcpt_uop_ftq_idx; // @[rob.scala:657:27]
wire next_xcpt_uop_edge_inst; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_pc_lob; // @[rob.scala:657:27]
wire next_xcpt_uop_taken; // @[rob.scala:657:27]
wire next_xcpt_uop_imm_rename; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_imm_sel; // @[rob.scala:657:27]
wire [4:0] next_xcpt_uop_pimm; // @[rob.scala:657:27]
wire [19:0] next_xcpt_uop_imm_packed; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_op1_sel; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_op2_sel; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_rob_idx; // @[rob.scala:657:27]
wire [3:0] next_xcpt_uop_ldq_idx; // @[rob.scala:657:27]
wire [3:0] next_xcpt_uop_stq_idx; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_rxq_idx; // @[rob.scala:657:27]
wire [6:0] next_xcpt_uop_pdst; // @[rob.scala:657:27]
wire [6:0] next_xcpt_uop_prs1; // @[rob.scala:657:27]
wire [6:0] next_xcpt_uop_prs2; // @[rob.scala:657:27]
wire [6:0] next_xcpt_uop_prs3; // @[rob.scala:657:27]
wire [4:0] next_xcpt_uop_ppred; // @[rob.scala:657:27]
wire next_xcpt_uop_prs1_busy; // @[rob.scala:657:27]
wire next_xcpt_uop_prs2_busy; // @[rob.scala:657:27]
wire next_xcpt_uop_prs3_busy; // @[rob.scala:657:27]
wire next_xcpt_uop_ppred_busy; // @[rob.scala:657:27]
wire [6:0] next_xcpt_uop_stale_pdst; // @[rob.scala:657:27]
wire next_xcpt_uop_exception; // @[rob.scala:657:27]
wire [63:0] next_xcpt_uop_exc_cause; // @[rob.scala:657:27]
wire [4:0] next_xcpt_uop_mem_cmd; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_mem_size; // @[rob.scala:657:27]
wire next_xcpt_uop_mem_signed; // @[rob.scala:657:27]
wire next_xcpt_uop_uses_ldq; // @[rob.scala:657:27]
wire next_xcpt_uop_uses_stq; // @[rob.scala:657:27]
wire next_xcpt_uop_is_unique; // @[rob.scala:657:27]
wire next_xcpt_uop_flush_on_commit; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_csr_cmd; // @[rob.scala:657:27]
wire next_xcpt_uop_ldst_is_rs1; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_ldst; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_lrs1; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_lrs2; // @[rob.scala:657:27]
wire [5:0] next_xcpt_uop_lrs3; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_dst_rtype; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_lrs1_rtype; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_lrs2_rtype; // @[rob.scala:657:27]
wire next_xcpt_uop_frs3_en; // @[rob.scala:657:27]
wire next_xcpt_uop_fcn_dw; // @[rob.scala:657:27]
wire [4:0] next_xcpt_uop_fcn_op; // @[rob.scala:657:27]
wire next_xcpt_uop_fp_val; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_fp_rm; // @[rob.scala:657:27]
wire [1:0] next_xcpt_uop_fp_typ; // @[rob.scala:657:27]
wire next_xcpt_uop_xcpt_pf_if; // @[rob.scala:657:27]
wire next_xcpt_uop_xcpt_ae_if; // @[rob.scala:657:27]
wire next_xcpt_uop_xcpt_ma_if; // @[rob.scala:657:27]
wire next_xcpt_uop_bp_debug_if; // @[rob.scala:657:27]
wire next_xcpt_uop_bp_xcpt_if; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_debug_fsrc; // @[rob.scala:657:27]
wire [2:0] next_xcpt_uop_debug_tsrc; // @[rob.scala:657:27]
wire _enq_xcpts_0_T; // @[rob.scala:661:38]
wire _enq_xcpts_1_T; // @[rob.scala:661:38]
wire enq_xcpts_0; // @[rob.scala:659:23]
wire enq_xcpts_1; // @[rob.scala:659:23]
assign _enq_xcpts_0_T = io_enq_valids_0_0 & io_enq_uops_0_exception_0; // @[rob.scala:199:7, :661:38]
assign enq_xcpts_0 = _enq_xcpts_0_T; // @[rob.scala:659:23, :661:38]
assign _enq_xcpts_1_T = io_enq_valids_1_0 & io_enq_uops_1_exception_0; // @[rob.scala:199:7, :661:38]
assign enq_xcpts_1 = _enq_xcpts_1_T; // @[rob.scala:659:23, :661:38]
wire _T_1227 = io_flush_valid_0 | exception_thrown; // @[rob.scala:199:7, :240:30, :664:26]
wire _lxcpt_older_T_1 = io_lxcpt_bits_uop_rob_idx_0 < io_csr_replay_bits_uop_rob_idx_0; // @[util.scala:364:52]
wire _lxcpt_older_T_2 = io_lxcpt_bits_uop_rob_idx_0 < rob_head_idx; // @[util.scala:364:64]
wire _lxcpt_older_T_3 = _lxcpt_older_T_1 ^ _lxcpt_older_T_2; // @[util.scala:364:{52,58,64}]
wire _lxcpt_older_T_4 = io_csr_replay_bits_uop_rob_idx_0 < rob_head_idx; // @[util.scala:364:78]
wire _lxcpt_older_T_5 = _lxcpt_older_T_3 ^ _lxcpt_older_T_4; // @[util.scala:364:{58,72,78}]
wire _lxcpt_older_T_6 = _lxcpt_older_T_5 & io_lxcpt_valid_0; // @[util.scala:364:72]
wire _T_1235 = ~r_xcpt_val | new_xcpt_uop_rob_idx < r_xcpt_uop_rob_idx ^ new_xcpt_uop_rob_idx < rob_head_idx ^ r_xcpt_uop_rob_idx < rob_head_idx; // @[util.scala:364:{52,58,64,72,78}]
wire _T_1238 = ~r_xcpt_val & (enq_xcpts_0 | enq_xcpts_1); // @[rob.scala:244:33, :659:23, :677:{18,30,51}]
wire idx = ~enq_xcpts_0; // @[rob.scala:659:23, :678:37]
wire [5:0] _GEN_240 = idx ? io_enq_uops_1_pc_lob_0 : io_enq_uops_0_pc_lob_0; // @[rob.scala:199:7, :678:37, :682:23]
assign next_xcpt_uop_inst = _T_1227 ? r_xcpt_uop_inst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_inst : r_xcpt_uop_inst) : _T_1238 ? (idx ? io_enq_uops_1_inst_0 : io_enq_uops_0_inst_0) : r_xcpt_uop_inst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_debug_inst = _T_1227 ? r_xcpt_uop_debug_inst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_debug_inst : r_xcpt_uop_debug_inst) : _T_1238 ? (idx ? io_enq_uops_1_debug_inst_0 : io_enq_uops_0_debug_inst_0) : r_xcpt_uop_debug_inst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_rvc = _T_1227 ? r_xcpt_uop_is_rvc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_rvc : r_xcpt_uop_is_rvc) : _T_1238 ? (idx ? io_enq_uops_1_is_rvc_0 : io_enq_uops_0_is_rvc_0) : r_xcpt_uop_is_rvc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_debug_pc = _T_1227 ? r_xcpt_uop_debug_pc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_debug_pc : r_xcpt_uop_debug_pc) : _T_1238 ? (idx ? io_enq_uops_1_debug_pc_0 : io_enq_uops_0_debug_pc_0) : r_xcpt_uop_debug_pc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iq_type_0 = _T_1227 ? r_xcpt_uop_iq_type_0 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iq_type_0 : r_xcpt_uop_iq_type_0) : _T_1238 ? (idx ? io_enq_uops_1_iq_type_0_0 : io_enq_uops_0_iq_type_0_0) : r_xcpt_uop_iq_type_0; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iq_type_1 = _T_1227 ? r_xcpt_uop_iq_type_1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iq_type_1 : r_xcpt_uop_iq_type_1) : _T_1238 ? (idx ? io_enq_uops_1_iq_type_1_0 : io_enq_uops_0_iq_type_1_0) : r_xcpt_uop_iq_type_1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iq_type_2 = _T_1227 ? r_xcpt_uop_iq_type_2 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iq_type_2 : r_xcpt_uop_iq_type_2) : _T_1238 ? (idx ? io_enq_uops_1_iq_type_2_0 : io_enq_uops_0_iq_type_2_0) : r_xcpt_uop_iq_type_2; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iq_type_3 = _T_1227 ? r_xcpt_uop_iq_type_3 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iq_type_3 : r_xcpt_uop_iq_type_3) : _T_1238 ? (idx ? io_enq_uops_1_iq_type_3_0 : io_enq_uops_0_iq_type_3_0) : r_xcpt_uop_iq_type_3; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_0 = _T_1227 ? r_xcpt_uop_fu_code_0 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_0 : r_xcpt_uop_fu_code_0) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_0_0 : io_enq_uops_0_fu_code_0_0) : r_xcpt_uop_fu_code_0; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_1 = _T_1227 ? r_xcpt_uop_fu_code_1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_1 : r_xcpt_uop_fu_code_1) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_1_0 : io_enq_uops_0_fu_code_1_0) : r_xcpt_uop_fu_code_1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_2 = _T_1227 ? r_xcpt_uop_fu_code_2 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_2 : r_xcpt_uop_fu_code_2) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_2_0 : io_enq_uops_0_fu_code_2_0) : r_xcpt_uop_fu_code_2; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_3 = _T_1227 ? r_xcpt_uop_fu_code_3 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_3 : r_xcpt_uop_fu_code_3) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_3_0 : io_enq_uops_0_fu_code_3_0) : r_xcpt_uop_fu_code_3; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_4 = _T_1227 ? r_xcpt_uop_fu_code_4 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_4 : r_xcpt_uop_fu_code_4) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_4_0 : io_enq_uops_0_fu_code_4_0) : r_xcpt_uop_fu_code_4; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_5 = _T_1227 ? r_xcpt_uop_fu_code_5 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_5 : r_xcpt_uop_fu_code_5) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_5_0 : io_enq_uops_0_fu_code_5_0) : r_xcpt_uop_fu_code_5; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_6 = _T_1227 ? r_xcpt_uop_fu_code_6 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_6 : r_xcpt_uop_fu_code_6) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_6_0 : io_enq_uops_0_fu_code_6_0) : r_xcpt_uop_fu_code_6; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_7 = _T_1227 ? r_xcpt_uop_fu_code_7 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_7 : r_xcpt_uop_fu_code_7) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_7_0 : io_enq_uops_0_fu_code_7_0) : r_xcpt_uop_fu_code_7; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_8 = _T_1227 ? r_xcpt_uop_fu_code_8 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_8 : r_xcpt_uop_fu_code_8) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_8_0 : io_enq_uops_0_fu_code_8_0) : r_xcpt_uop_fu_code_8; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fu_code_9 = _T_1227 ? r_xcpt_uop_fu_code_9 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fu_code_9 : r_xcpt_uop_fu_code_9) : _T_1238 ? (idx ? io_enq_uops_1_fu_code_9_0 : io_enq_uops_0_fu_code_9_0) : r_xcpt_uop_fu_code_9; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_issued = _T_1227 ? r_xcpt_uop_iw_issued : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_issued : r_xcpt_uop_iw_issued) : _T_1238 ? (idx ? io_enq_uops_1_iw_issued_0 : io_enq_uops_0_iw_issued_0) : r_xcpt_uop_iw_issued; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_issued_partial_agen = _T_1227 ? r_xcpt_uop_iw_issued_partial_agen : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_issued_partial_agen : r_xcpt_uop_iw_issued_partial_agen) : _T_1238 ? (idx ? io_enq_uops_1_iw_issued_partial_agen_0 : io_enq_uops_0_iw_issued_partial_agen_0) : r_xcpt_uop_iw_issued_partial_agen; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_issued_partial_dgen = _T_1227 ? r_xcpt_uop_iw_issued_partial_dgen : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_issued_partial_dgen : r_xcpt_uop_iw_issued_partial_dgen) : _T_1238 ? (idx ? io_enq_uops_1_iw_issued_partial_dgen_0 : io_enq_uops_0_iw_issued_partial_dgen_0) : r_xcpt_uop_iw_issued_partial_dgen; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_p1_speculative_child = _T_1227 ? r_xcpt_uop_iw_p1_speculative_child : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_p1_speculative_child : r_xcpt_uop_iw_p1_speculative_child) : _T_1238 ? (idx ? io_enq_uops_1_iw_p1_speculative_child_0 : io_enq_uops_0_iw_p1_speculative_child_0) : r_xcpt_uop_iw_p1_speculative_child; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_p2_speculative_child = _T_1227 ? r_xcpt_uop_iw_p2_speculative_child : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_p2_speculative_child : r_xcpt_uop_iw_p2_speculative_child) : _T_1238 ? (idx ? io_enq_uops_1_iw_p2_speculative_child_0 : io_enq_uops_0_iw_p2_speculative_child_0) : r_xcpt_uop_iw_p2_speculative_child; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_p1_bypass_hint = _T_1227 ? r_xcpt_uop_iw_p1_bypass_hint : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_p1_bypass_hint : r_xcpt_uop_iw_p1_bypass_hint) : _T_1238 ? (idx ? io_enq_uops_1_iw_p1_bypass_hint_0 : io_enq_uops_0_iw_p1_bypass_hint_0) : r_xcpt_uop_iw_p1_bypass_hint; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_p2_bypass_hint = _T_1227 ? r_xcpt_uop_iw_p2_bypass_hint : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_p2_bypass_hint : r_xcpt_uop_iw_p2_bypass_hint) : _T_1238 ? (idx ? io_enq_uops_1_iw_p2_bypass_hint_0 : io_enq_uops_0_iw_p2_bypass_hint_0) : r_xcpt_uop_iw_p2_bypass_hint; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_iw_p3_bypass_hint = _T_1227 ? r_xcpt_uop_iw_p3_bypass_hint : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_iw_p3_bypass_hint : r_xcpt_uop_iw_p3_bypass_hint) : _T_1238 ? (idx ? io_enq_uops_1_iw_p3_bypass_hint_0 : io_enq_uops_0_iw_p3_bypass_hint_0) : r_xcpt_uop_iw_p3_bypass_hint; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_dis_col_sel = _T_1227 ? r_xcpt_uop_dis_col_sel : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_dis_col_sel : r_xcpt_uop_dis_col_sel) : _T_1238 ? (idx ? io_enq_uops_1_dis_col_sel_0 : io_enq_uops_0_dis_col_sel_0) : r_xcpt_uop_dis_col_sel; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_br_mask = _T_1227 ? r_xcpt_uop_br_mask : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_br_mask : r_xcpt_uop_br_mask) : _T_1238 ? (idx ? io_enq_uops_1_br_mask_0 : io_enq_uops_0_br_mask_0) : r_xcpt_uop_br_mask; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_br_tag = _T_1227 ? r_xcpt_uop_br_tag : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_br_tag : r_xcpt_uop_br_tag) : _T_1238 ? (idx ? io_enq_uops_1_br_tag_0 : io_enq_uops_0_br_tag_0) : r_xcpt_uop_br_tag; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_br_type = _T_1227 ? r_xcpt_uop_br_type : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_br_type : r_xcpt_uop_br_type) : _T_1238 ? (idx ? io_enq_uops_1_br_type_0 : io_enq_uops_0_br_type_0) : r_xcpt_uop_br_type; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_sfb = _T_1227 ? r_xcpt_uop_is_sfb : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_sfb : r_xcpt_uop_is_sfb) : _T_1238 ? (idx ? io_enq_uops_1_is_sfb_0 : io_enq_uops_0_is_sfb_0) : r_xcpt_uop_is_sfb; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_fence = _T_1227 ? r_xcpt_uop_is_fence : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_fence : r_xcpt_uop_is_fence) : _T_1238 ? (idx ? io_enq_uops_1_is_fence_0 : io_enq_uops_0_is_fence_0) : r_xcpt_uop_is_fence; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_fencei = _T_1227 ? r_xcpt_uop_is_fencei : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_fencei : r_xcpt_uop_is_fencei) : _T_1238 ? (idx ? io_enq_uops_1_is_fencei_0 : io_enq_uops_0_is_fencei_0) : r_xcpt_uop_is_fencei; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_sfence = _T_1227 ? r_xcpt_uop_is_sfence : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_sfence : r_xcpt_uop_is_sfence) : _T_1238 ? (idx ? io_enq_uops_1_is_sfence_0 : io_enq_uops_0_is_sfence_0) : r_xcpt_uop_is_sfence; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_amo = _T_1227 ? r_xcpt_uop_is_amo : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_amo : r_xcpt_uop_is_amo) : _T_1238 ? (idx ? io_enq_uops_1_is_amo_0 : io_enq_uops_0_is_amo_0) : r_xcpt_uop_is_amo; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_eret = _T_1227 ? r_xcpt_uop_is_eret : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_eret : r_xcpt_uop_is_eret) : _T_1238 ? (idx ? io_enq_uops_1_is_eret_0 : io_enq_uops_0_is_eret_0) : r_xcpt_uop_is_eret; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_sys_pc2epc = _T_1227 ? r_xcpt_uop_is_sys_pc2epc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_sys_pc2epc : r_xcpt_uop_is_sys_pc2epc) : _T_1238 ? (idx ? io_enq_uops_1_is_sys_pc2epc_0 : io_enq_uops_0_is_sys_pc2epc_0) : r_xcpt_uop_is_sys_pc2epc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_rocc = _T_1227 ? r_xcpt_uop_is_rocc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_rocc : r_xcpt_uop_is_rocc) : _T_1238 ? (idx ? io_enq_uops_1_is_rocc_0 : io_enq_uops_0_is_rocc_0) : r_xcpt_uop_is_rocc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_mov = _T_1227 ? r_xcpt_uop_is_mov : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_mov : r_xcpt_uop_is_mov) : _T_1238 ? (idx ? io_enq_uops_1_is_mov_0 : io_enq_uops_0_is_mov_0) : r_xcpt_uop_is_mov; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ftq_idx = _T_1227 ? r_xcpt_uop_ftq_idx : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ftq_idx : r_xcpt_uop_ftq_idx) : _T_1238 ? (idx ? io_enq_uops_1_ftq_idx_0 : io_enq_uops_0_ftq_idx_0) : r_xcpt_uop_ftq_idx; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_edge_inst = _T_1227 ? r_xcpt_uop_edge_inst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_edge_inst : r_xcpt_uop_edge_inst) : _T_1238 ? (idx ? io_enq_uops_1_edge_inst_0 : io_enq_uops_0_edge_inst_0) : r_xcpt_uop_edge_inst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_pc_lob = _T_1227 ? r_xcpt_uop_pc_lob : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_pc_lob : r_xcpt_uop_pc_lob) : _T_1238 ? _GEN_240 : r_xcpt_uop_pc_lob; // @[rob.scala:245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :682:23]
assign next_xcpt_uop_taken = _T_1227 ? r_xcpt_uop_taken : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_taken : r_xcpt_uop_taken) : _T_1238 ? (idx ? io_enq_uops_1_taken_0 : io_enq_uops_0_taken_0) : r_xcpt_uop_taken; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_imm_rename = _T_1227 ? r_xcpt_uop_imm_rename : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_imm_rename : r_xcpt_uop_imm_rename) : _T_1238 ? (idx ? io_enq_uops_1_imm_rename_0 : io_enq_uops_0_imm_rename_0) : r_xcpt_uop_imm_rename; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_imm_sel = _T_1227 ? r_xcpt_uop_imm_sel : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_imm_sel : r_xcpt_uop_imm_sel) : _T_1238 ? (idx ? io_enq_uops_1_imm_sel_0 : io_enq_uops_0_imm_sel_0) : r_xcpt_uop_imm_sel; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_pimm = _T_1227 ? r_xcpt_uop_pimm : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_pimm : r_xcpt_uop_pimm) : _T_1238 ? (idx ? io_enq_uops_1_pimm_0 : io_enq_uops_0_pimm_0) : r_xcpt_uop_pimm; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_imm_packed = _T_1227 ? r_xcpt_uop_imm_packed : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_imm_packed : r_xcpt_uop_imm_packed) : _T_1238 ? (idx ? io_enq_uops_1_imm_packed_0 : io_enq_uops_0_imm_packed_0) : r_xcpt_uop_imm_packed; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_op1_sel = _T_1227 ? r_xcpt_uop_op1_sel : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_op1_sel : r_xcpt_uop_op1_sel) : _T_1238 ? (idx ? io_enq_uops_1_op1_sel_0 : io_enq_uops_0_op1_sel_0) : r_xcpt_uop_op1_sel; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_op2_sel = _T_1227 ? r_xcpt_uop_op2_sel : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_op2_sel : r_xcpt_uop_op2_sel) : _T_1238 ? (idx ? io_enq_uops_1_op2_sel_0 : io_enq_uops_0_op2_sel_0) : r_xcpt_uop_op2_sel; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_ldst = _T_1227 ? r_xcpt_uop_fp_ctrl_ldst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_ldst : r_xcpt_uop_fp_ctrl_ldst) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_ldst_0 : io_enq_uops_0_fp_ctrl_ldst_0) : r_xcpt_uop_fp_ctrl_ldst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_wen = _T_1227 ? r_xcpt_uop_fp_ctrl_wen : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_wen : r_xcpt_uop_fp_ctrl_wen) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_wen_0 : io_enq_uops_0_fp_ctrl_wen_0) : r_xcpt_uop_fp_ctrl_wen; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_ren1 = _T_1227 ? r_xcpt_uop_fp_ctrl_ren1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_ren1 : r_xcpt_uop_fp_ctrl_ren1) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_ren1_0 : io_enq_uops_0_fp_ctrl_ren1_0) : r_xcpt_uop_fp_ctrl_ren1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_ren2 = _T_1227 ? r_xcpt_uop_fp_ctrl_ren2 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_ren2 : r_xcpt_uop_fp_ctrl_ren2) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_ren2_0 : io_enq_uops_0_fp_ctrl_ren2_0) : r_xcpt_uop_fp_ctrl_ren2; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_ren3 = _T_1227 ? r_xcpt_uop_fp_ctrl_ren3 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_ren3 : r_xcpt_uop_fp_ctrl_ren3) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_ren3_0 : io_enq_uops_0_fp_ctrl_ren3_0) : r_xcpt_uop_fp_ctrl_ren3; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_swap12 = _T_1227 ? r_xcpt_uop_fp_ctrl_swap12 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_swap12 : r_xcpt_uop_fp_ctrl_swap12) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_swap12_0 : io_enq_uops_0_fp_ctrl_swap12_0) : r_xcpt_uop_fp_ctrl_swap12; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_swap23 = _T_1227 ? r_xcpt_uop_fp_ctrl_swap23 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_swap23 : r_xcpt_uop_fp_ctrl_swap23) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_swap23_0 : io_enq_uops_0_fp_ctrl_swap23_0) : r_xcpt_uop_fp_ctrl_swap23; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_typeTagIn = _T_1227 ? r_xcpt_uop_fp_ctrl_typeTagIn : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_typeTagIn : r_xcpt_uop_fp_ctrl_typeTagIn) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_typeTagIn_0 : io_enq_uops_0_fp_ctrl_typeTagIn_0) : r_xcpt_uop_fp_ctrl_typeTagIn; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_typeTagOut = _T_1227 ? r_xcpt_uop_fp_ctrl_typeTagOut : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_typeTagOut : r_xcpt_uop_fp_ctrl_typeTagOut) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_typeTagOut_0 : io_enq_uops_0_fp_ctrl_typeTagOut_0) : r_xcpt_uop_fp_ctrl_typeTagOut; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_fromint = _T_1227 ? r_xcpt_uop_fp_ctrl_fromint : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_fromint : r_xcpt_uop_fp_ctrl_fromint) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_fromint_0 : io_enq_uops_0_fp_ctrl_fromint_0) : r_xcpt_uop_fp_ctrl_fromint; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_toint = _T_1227 ? r_xcpt_uop_fp_ctrl_toint : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_toint : r_xcpt_uop_fp_ctrl_toint) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_toint_0 : io_enq_uops_0_fp_ctrl_toint_0) : r_xcpt_uop_fp_ctrl_toint; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_fastpipe = _T_1227 ? r_xcpt_uop_fp_ctrl_fastpipe : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_fastpipe : r_xcpt_uop_fp_ctrl_fastpipe) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_fastpipe_0 : io_enq_uops_0_fp_ctrl_fastpipe_0) : r_xcpt_uop_fp_ctrl_fastpipe; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_fma = _T_1227 ? r_xcpt_uop_fp_ctrl_fma : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_fma : r_xcpt_uop_fp_ctrl_fma) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_fma_0 : io_enq_uops_0_fp_ctrl_fma_0) : r_xcpt_uop_fp_ctrl_fma; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_div = _T_1227 ? r_xcpt_uop_fp_ctrl_div : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_div : r_xcpt_uop_fp_ctrl_div) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_div_0 : io_enq_uops_0_fp_ctrl_div_0) : r_xcpt_uop_fp_ctrl_div; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_sqrt = _T_1227 ? r_xcpt_uop_fp_ctrl_sqrt : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_sqrt : r_xcpt_uop_fp_ctrl_sqrt) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_sqrt_0 : io_enq_uops_0_fp_ctrl_sqrt_0) : r_xcpt_uop_fp_ctrl_sqrt; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_wflags = _T_1227 ? r_xcpt_uop_fp_ctrl_wflags : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_wflags : r_xcpt_uop_fp_ctrl_wflags) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_wflags_0 : io_enq_uops_0_fp_ctrl_wflags_0) : r_xcpt_uop_fp_ctrl_wflags; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_ctrl_vec = _T_1227 ? r_xcpt_uop_fp_ctrl_vec : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_ctrl_vec : r_xcpt_uop_fp_ctrl_vec) : _T_1238 ? (idx ? io_enq_uops_1_fp_ctrl_vec_0 : io_enq_uops_0_fp_ctrl_vec_0) : r_xcpt_uop_fp_ctrl_vec; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_rob_idx = _T_1227 ? r_xcpt_uop_rob_idx : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_rob_idx : r_xcpt_uop_rob_idx) : _T_1238 ? (idx ? io_enq_uops_1_rob_idx_0 : io_enq_uops_0_rob_idx_0) : r_xcpt_uop_rob_idx; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ldq_idx = _T_1227 ? r_xcpt_uop_ldq_idx : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ldq_idx : r_xcpt_uop_ldq_idx) : _T_1238 ? (idx ? io_enq_uops_1_ldq_idx_0 : io_enq_uops_0_ldq_idx_0) : r_xcpt_uop_ldq_idx; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_stq_idx = _T_1227 ? r_xcpt_uop_stq_idx : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_stq_idx : r_xcpt_uop_stq_idx) : _T_1238 ? (idx ? io_enq_uops_1_stq_idx_0 : io_enq_uops_0_stq_idx_0) : r_xcpt_uop_stq_idx; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_rxq_idx = _T_1227 ? r_xcpt_uop_rxq_idx : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_rxq_idx : r_xcpt_uop_rxq_idx) : _T_1238 ? (idx ? io_enq_uops_1_rxq_idx_0 : io_enq_uops_0_rxq_idx_0) : r_xcpt_uop_rxq_idx; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_pdst = _T_1227 ? r_xcpt_uop_pdst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_pdst : r_xcpt_uop_pdst) : _T_1238 ? (idx ? io_enq_uops_1_pdst_0 : io_enq_uops_0_pdst_0) : r_xcpt_uop_pdst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs1 = _T_1227 ? r_xcpt_uop_prs1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs1 : r_xcpt_uop_prs1) : _T_1238 ? (idx ? io_enq_uops_1_prs1_0 : io_enq_uops_0_prs1_0) : r_xcpt_uop_prs1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs2 = _T_1227 ? r_xcpt_uop_prs2 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs2 : r_xcpt_uop_prs2) : _T_1238 ? (idx ? io_enq_uops_1_prs2_0 : io_enq_uops_0_prs2_0) : r_xcpt_uop_prs2; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs3 = _T_1227 ? r_xcpt_uop_prs3 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs3 : r_xcpt_uop_prs3) : _T_1238 ? (idx ? io_enq_uops_1_prs3_0 : io_enq_uops_0_prs3_0) : r_xcpt_uop_prs3; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ppred = _T_1227 ? r_xcpt_uop_ppred : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ppred : r_xcpt_uop_ppred) : _T_1238 ? (idx ? io_enq_uops_1_ppred_0 : io_enq_uops_0_ppred_0) : r_xcpt_uop_ppred; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs1_busy = _T_1227 ? r_xcpt_uop_prs1_busy : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs1_busy : r_xcpt_uop_prs1_busy) : _T_1238 ? (idx ? io_enq_uops_1_prs1_busy_0 : io_enq_uops_0_prs1_busy_0) : r_xcpt_uop_prs1_busy; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs2_busy = _T_1227 ? r_xcpt_uop_prs2_busy : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs2_busy : r_xcpt_uop_prs2_busy) : _T_1238 ? (idx ? io_enq_uops_1_prs2_busy_0 : io_enq_uops_0_prs2_busy_0) : r_xcpt_uop_prs2_busy; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_prs3_busy = _T_1227 ? r_xcpt_uop_prs3_busy : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_prs3_busy : r_xcpt_uop_prs3_busy) : _T_1238 ? (idx ? io_enq_uops_1_prs3_busy_0 : io_enq_uops_0_prs3_busy_0) : r_xcpt_uop_prs3_busy; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ppred_busy = _T_1227 ? r_xcpt_uop_ppred_busy : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ppred_busy : r_xcpt_uop_ppred_busy) : _T_1238 ? (idx ? io_enq_uops_1_ppred_busy_0 : io_enq_uops_0_ppred_busy_0) : r_xcpt_uop_ppred_busy; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_stale_pdst = _T_1227 ? r_xcpt_uop_stale_pdst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_stale_pdst : r_xcpt_uop_stale_pdst) : _T_1238 ? (idx ? io_enq_uops_1_stale_pdst_0 : io_enq_uops_0_stale_pdst_0) : r_xcpt_uop_stale_pdst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_exception = _T_1227 ? r_xcpt_uop_exception : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_exception : r_xcpt_uop_exception) : _T_1238 ? (idx ? io_enq_uops_1_exception_0 : io_enq_uops_0_exception_0) : r_xcpt_uop_exception; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_exc_cause = _T_1227 ? r_xcpt_uop_exc_cause : new_xcpt_valid ? (_T_1235 ? {59'h0, new_xcpt_cause} : r_xcpt_uop_exc_cause) : _T_1238 ? (idx ? io_enq_uops_1_exc_cause_0 : io_enq_uops_0_exc_cause_0) : r_xcpt_uop_exc_cause; // @[package.scala:16:47]
assign next_xcpt_uop_mem_cmd = _T_1227 ? r_xcpt_uop_mem_cmd : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_mem_cmd : r_xcpt_uop_mem_cmd) : _T_1238 ? (idx ? io_enq_uops_1_mem_cmd_0 : io_enq_uops_0_mem_cmd_0) : r_xcpt_uop_mem_cmd; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_mem_size = _T_1227 ? r_xcpt_uop_mem_size : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_mem_size : r_xcpt_uop_mem_size) : _T_1238 ? (idx ? io_enq_uops_1_mem_size_0 : io_enq_uops_0_mem_size_0) : r_xcpt_uop_mem_size; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_mem_signed = _T_1227 ? r_xcpt_uop_mem_signed : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_mem_signed : r_xcpt_uop_mem_signed) : _T_1238 ? (idx ? io_enq_uops_1_mem_signed_0 : io_enq_uops_0_mem_signed_0) : r_xcpt_uop_mem_signed; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_uses_ldq = _T_1227 ? r_xcpt_uop_uses_ldq : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_uses_ldq : r_xcpt_uop_uses_ldq) : _T_1238 ? (idx ? io_enq_uops_1_uses_ldq_0 : io_enq_uops_0_uses_ldq_0) : r_xcpt_uop_uses_ldq; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_uses_stq = _T_1227 ? r_xcpt_uop_uses_stq : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_uses_stq : r_xcpt_uop_uses_stq) : _T_1238 ? (idx ? io_enq_uops_1_uses_stq_0 : io_enq_uops_0_uses_stq_0) : r_xcpt_uop_uses_stq; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_is_unique = _T_1227 ? r_xcpt_uop_is_unique : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_is_unique : r_xcpt_uop_is_unique) : _T_1238 ? (idx ? io_enq_uops_1_is_unique_0 : io_enq_uops_0_is_unique_0) : r_xcpt_uop_is_unique; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_flush_on_commit = _T_1227 ? r_xcpt_uop_flush_on_commit : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_flush_on_commit : r_xcpt_uop_flush_on_commit) : _T_1238 ? (idx ? io_enq_uops_1_flush_on_commit_0 : io_enq_uops_0_flush_on_commit_0) : r_xcpt_uop_flush_on_commit; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_csr_cmd = _T_1227 ? r_xcpt_uop_csr_cmd : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_csr_cmd : r_xcpt_uop_csr_cmd) : _T_1238 ? (idx ? io_enq_uops_1_csr_cmd_0 : io_enq_uops_0_csr_cmd_0) : r_xcpt_uop_csr_cmd; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ldst_is_rs1 = _T_1227 ? r_xcpt_uop_ldst_is_rs1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ldst_is_rs1 : r_xcpt_uop_ldst_is_rs1) : _T_1238 ? (idx ? io_enq_uops_1_ldst_is_rs1_0 : io_enq_uops_0_ldst_is_rs1_0) : r_xcpt_uop_ldst_is_rs1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_ldst = _T_1227 ? r_xcpt_uop_ldst : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_ldst : r_xcpt_uop_ldst) : _T_1238 ? (idx ? io_enq_uops_1_ldst_0 : io_enq_uops_0_ldst_0) : r_xcpt_uop_ldst; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_lrs1 = _T_1227 ? r_xcpt_uop_lrs1 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_lrs1 : r_xcpt_uop_lrs1) : _T_1238 ? (idx ? io_enq_uops_1_lrs1_0 : io_enq_uops_0_lrs1_0) : r_xcpt_uop_lrs1; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_lrs2 = _T_1227 ? r_xcpt_uop_lrs2 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_lrs2 : r_xcpt_uop_lrs2) : _T_1238 ? (idx ? io_enq_uops_1_lrs2_0 : io_enq_uops_0_lrs2_0) : r_xcpt_uop_lrs2; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_lrs3 = _T_1227 ? r_xcpt_uop_lrs3 : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_lrs3 : r_xcpt_uop_lrs3) : _T_1238 ? (idx ? io_enq_uops_1_lrs3_0 : io_enq_uops_0_lrs3_0) : r_xcpt_uop_lrs3; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_dst_rtype = _T_1227 ? r_xcpt_uop_dst_rtype : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_dst_rtype : r_xcpt_uop_dst_rtype) : _T_1238 ? (idx ? io_enq_uops_1_dst_rtype_0 : io_enq_uops_0_dst_rtype_0) : r_xcpt_uop_dst_rtype; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_lrs1_rtype = _T_1227 ? r_xcpt_uop_lrs1_rtype : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_lrs1_rtype : r_xcpt_uop_lrs1_rtype) : _T_1238 ? (idx ? io_enq_uops_1_lrs1_rtype_0 : io_enq_uops_0_lrs1_rtype_0) : r_xcpt_uop_lrs1_rtype; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_lrs2_rtype = _T_1227 ? r_xcpt_uop_lrs2_rtype : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_lrs2_rtype : r_xcpt_uop_lrs2_rtype) : _T_1238 ? (idx ? io_enq_uops_1_lrs2_rtype_0 : io_enq_uops_0_lrs2_rtype_0) : r_xcpt_uop_lrs2_rtype; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_frs3_en = _T_1227 ? r_xcpt_uop_frs3_en : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_frs3_en : r_xcpt_uop_frs3_en) : _T_1238 ? (idx ? io_enq_uops_1_frs3_en_0 : io_enq_uops_0_frs3_en_0) : r_xcpt_uop_frs3_en; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fcn_dw = _T_1227 ? r_xcpt_uop_fcn_dw : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fcn_dw : r_xcpt_uop_fcn_dw) : _T_1238 ? (idx ? io_enq_uops_1_fcn_dw_0 : io_enq_uops_0_fcn_dw_0) : r_xcpt_uop_fcn_dw; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fcn_op = _T_1227 ? r_xcpt_uop_fcn_op : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fcn_op : r_xcpt_uop_fcn_op) : _T_1238 ? (idx ? io_enq_uops_1_fcn_op_0 : io_enq_uops_0_fcn_op_0) : r_xcpt_uop_fcn_op; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_val = _T_1227 ? r_xcpt_uop_fp_val : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_val : r_xcpt_uop_fp_val) : _T_1238 ? (idx ? io_enq_uops_1_fp_val_0 : io_enq_uops_0_fp_val_0) : r_xcpt_uop_fp_val; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_rm = _T_1227 ? r_xcpt_uop_fp_rm : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_rm : r_xcpt_uop_fp_rm) : _T_1238 ? (idx ? io_enq_uops_1_fp_rm_0 : io_enq_uops_0_fp_rm_0) : r_xcpt_uop_fp_rm; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_fp_typ = _T_1227 ? r_xcpt_uop_fp_typ : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_fp_typ : r_xcpt_uop_fp_typ) : _T_1238 ? (idx ? io_enq_uops_1_fp_typ_0 : io_enq_uops_0_fp_typ_0) : r_xcpt_uop_fp_typ; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_xcpt_pf_if = _T_1227 ? r_xcpt_uop_xcpt_pf_if : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_xcpt_pf_if : r_xcpt_uop_xcpt_pf_if) : _T_1238 ? (idx ? io_enq_uops_1_xcpt_pf_if_0 : io_enq_uops_0_xcpt_pf_if_0) : r_xcpt_uop_xcpt_pf_if; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_xcpt_ae_if = _T_1227 ? r_xcpt_uop_xcpt_ae_if : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_xcpt_ae_if : r_xcpt_uop_xcpt_ae_if) : _T_1238 ? (idx ? io_enq_uops_1_xcpt_ae_if_0 : io_enq_uops_0_xcpt_ae_if_0) : r_xcpt_uop_xcpt_ae_if; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_xcpt_ma_if = _T_1227 ? r_xcpt_uop_xcpt_ma_if : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_xcpt_ma_if : r_xcpt_uop_xcpt_ma_if) : _T_1238 ? (idx ? io_enq_uops_1_xcpt_ma_if_0 : io_enq_uops_0_xcpt_ma_if_0) : r_xcpt_uop_xcpt_ma_if; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_bp_debug_if = _T_1227 ? r_xcpt_uop_bp_debug_if : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_bp_debug_if : r_xcpt_uop_bp_debug_if) : _T_1238 ? (idx ? io_enq_uops_1_bp_debug_if_0 : io_enq_uops_0_bp_debug_if_0) : r_xcpt_uop_bp_debug_if; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_bp_xcpt_if = _T_1227 ? r_xcpt_uop_bp_xcpt_if : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_bp_xcpt_if : r_xcpt_uop_bp_xcpt_if) : _T_1238 ? (idx ? io_enq_uops_1_bp_xcpt_if_0 : io_enq_uops_0_bp_xcpt_if_0) : r_xcpt_uop_bp_xcpt_if; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_debug_fsrc = _T_1227 ? r_xcpt_uop_debug_fsrc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_debug_fsrc : r_xcpt_uop_debug_fsrc) : _T_1238 ? (idx ? io_enq_uops_1_debug_fsrc_0 : io_enq_uops_0_debug_fsrc_0) : r_xcpt_uop_debug_fsrc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
assign next_xcpt_uop_debug_tsrc = _T_1227 ? r_xcpt_uop_debug_tsrc : new_xcpt_valid ? (_T_1235 ? new_xcpt_uop_debug_tsrc : r_xcpt_uop_debug_tsrc) : _T_1238 ? (idx ? io_enq_uops_1_debug_tsrc_0 : io_enq_uops_0_debug_tsrc_0) : r_xcpt_uop_debug_tsrc; // @[rob.scala:199:7, :245:29, :657:27, :658:17, :664:{26,48}, :665:41, :668:23, :670:27, :671:{25,93}, :673:33, :677:{30,56}, :678:37, :682:23]
wire [39:0] _r_xcpt_badvaddr_T = ~io_xcpt_fetch_pc_0; // @[util.scala:245:7]
wire [39:0] _r_xcpt_badvaddr_T_1 = {_r_xcpt_badvaddr_T[39:6], 6'h3F}; // @[util.scala:245:{7,11}]
wire [39:0] _r_xcpt_badvaddr_T_2 = ~_r_xcpt_badvaddr_T_1; // @[util.scala:245:{5,11}]
wire [39:0] _r_xcpt_badvaddr_T_3 = {_r_xcpt_badvaddr_T_2[39:6], _r_xcpt_badvaddr_T_2[5:0] | _GEN_240}; // @[util.scala:245:5]
wire [11:0] _r_xcpt_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
wire [11:0] _r_xcpt_uop_br_mask_T_1 = next_xcpt_uop_br_mask & _r_xcpt_uop_br_mask_T; // @[util.scala:93:{25,27}]
reg r_partial_row; // @[rob.scala:712:30]
wire [1:0] _finished_committing_row_T = {io_commit_valids_1_0, io_commit_valids_0_0}; // @[rob.scala:199:7, :715:23]
wire _finished_committing_row_T_1 = |_finished_committing_row_T; // @[rob.scala:715:{23,30}]
wire [1:0] _finished_committing_row_T_2 = {will_commit_1, will_commit_0}; // @[rob.scala:229:33, :716:19]
wire [1:0] _GEN_241 = {rob_head_vals_1, rob_head_vals_0}; // @[rob.scala:234:33, :716:42]
wire [1:0] _finished_committing_row_T_3; // @[rob.scala:716:42]
assign _finished_committing_row_T_3 = _GEN_241; // @[rob.scala:716:42]
wire [1:0] _rob_head_lsb_T; // @[rob.scala:725:62]
assign _rob_head_lsb_T = _GEN_241; // @[rob.scala:716:42, :725:62]
wire [1:0] _empty_T_1; // @[rob.scala:793:59]
assign _empty_T_1 = _GEN_241; // @[rob.scala:716:42, :793:59]
wire [1:0] _io_com_load_is_at_rob_head_T; // @[rob.scala:838:89]
assign _io_com_load_is_at_rob_head_T = _GEN_241; // @[rob.scala:716:42, :838:89]
wire [1:0] _finished_committing_row_T_4 = _finished_committing_row_T_2 ^ _finished_committing_row_T_3; // @[rob.scala:716:{19,26,42}]
wire _finished_committing_row_T_5 = _finished_committing_row_T_4 == 2'h0; // @[rob.scala:716:{26,50}]
wire _finished_committing_row_T_6 = _finished_committing_row_T_1 & _finished_committing_row_T_5; // @[rob.scala:715:{30,39}, :716:50]
wire _GEN_242 = rob_head == rob_tail; // @[rob.scala:210:29, :214:29, :717:33]
wire _finished_committing_row_T_7; // @[rob.scala:717:33]
assign _finished_committing_row_T_7 = _GEN_242; // @[rob.scala:717:33]
wire _empty_T; // @[rob.scala:793:27]
assign _empty_T = _GEN_242; // @[rob.scala:717:33, :793:27]
wire _finished_committing_row_T_8 = r_partial_row & _finished_committing_row_T_7; // @[rob.scala:712:30, :717:{21,33}]
wire _finished_committing_row_T_9 = ~io_brupdate_b2_mispredict_0; // @[rob.scala:199:7, :451:84, :717:49]
wire _finished_committing_row_T_10 = _finished_committing_row_T_8 & _finished_committing_row_T_9; // @[rob.scala:717:{21,46,49}]
wire _finished_committing_row_T_11 = ~_finished_committing_row_T_10; // @[rob.scala:717:{5,46}]
wire finished_committing_row = _finished_committing_row_T_6 & _finished_committing_row_T_11; // @[rob.scala:715:39, :716:59, :717:5]
wire [5:0] _next_rob_head_T = _GEN_1 + 6'h1; // @[util.scala:211:14, :372:11]
wire [4:0] _next_rob_head_T_1 = _next_rob_head_T[4:0]; // @[util.scala:211:14]
wire [4:0] _next_rob_head_T_2 = _next_rob_head_T_1; // @[util.scala:211:{14,20}]
assign next_rob_head = finished_committing_row ? _next_rob_head_T_2 : rob_head; // @[util.scala:211:20]
wire _rob_head_lsb_T_1 = _rob_head_lsb_T[0]; // @[OneHot.scala:85:71]
wire _rob_head_lsb_T_2 = _rob_head_lsb_T[1]; // @[OneHot.scala:85:71]
wire [1:0] _rob_head_lsb_T_3 = {_rob_head_lsb_T_2, 1'h0}; // @[OneHot.scala:85:71]
wire [1:0] _rob_head_lsb_T_4 = _rob_head_lsb_T_1 ? 2'h1 : _rob_head_lsb_T_3; // @[OneHot.scala:85:71]
wire _rob_head_lsb_T_5 = _rob_head_lsb_T_4[1]; // @[Mux.scala:50:70]
wire _T_1305 = rob_state == 2'h1; // @[rob.scala:207:26, :744:33]
wire _safe_to_inc_T; // @[rob.scala:744:33]
assign _safe_to_inc_T = _T_1305; // @[rob.scala:744:33]
wire _io_ready_T; // @[rob.scala:799:33]
assign _io_ready_T = _T_1305; // @[rob.scala:744:33, :799:33]
wire _safe_to_inc_T_1 = rob_state == 2'h2; // @[rob.scala:207:26, :744:59]
wire safe_to_inc = _safe_to_inc_T | _safe_to_inc_T_1; // @[rob.scala:744:{33,46,59}]
wire _do_inc_row_T = rob_pnr_unsafe_0 | rob_pnr_unsafe_1; // @[rob.scala:233:33, :745:46]
wire _do_inc_row_T_1 = ~_do_inc_row_T; // @[rob.scala:745:{22,46}]
wire _do_inc_row_T_2 = rob_pnr == rob_tail; // @[rob.scala:214:29, :218:29, :745:64]
wire _do_inc_row_T_3 = ~io_brupdate_b2_mispredict_0; // @[rob.scala:199:7, :451:84, :745:80]
wire _do_inc_row_T_4 = _do_inc_row_T_2 & _do_inc_row_T_3; // @[rob.scala:745:{64,77,80}]
wire _do_inc_row_T_5 = ~_do_inc_row_T_4; // @[rob.scala:745:{54,77}]
wire do_inc_row = _do_inc_row_T_1 & _do_inc_row_T_5; // @[rob.scala:745:{22,51,54}]
wire _rob_pnr_lsb_T = ~io_enq_valids_0_0; // @[Mux.scala:50:70]
wire [5:0] _rob_pnr_T = {1'h0, rob_pnr} + 6'h1; // @[util.scala:211:14]
wire [4:0] _rob_pnr_T_1 = _rob_pnr_T[4:0]; // @[util.scala:211:14]
wire [4:0] _rob_pnr_T_2 = _rob_pnr_T_1; // @[util.scala:211:{14,20}]
wire _rob_pnr_lsb_T_1 = ~rob_pnr_unsafe_0; // @[Mux.scala:50:70]
wire [1:0] _rob_pnr_lsb_T_2 = {rob_pnr_unsafe_1, rob_pnr_unsafe_0}; // @[rob.scala:233:33, :762:53]
wire [1:0] _rob_pnr_lsb_T_3 = {rob_tail_vals_1, rob_tail_vals_0}; // @[rob.scala:235:33, :762:87]
wire [1:0] _rob_pnr_lsb_T_4 = _rob_pnr_lsb_T_3; // @[util.scala:383:29]
wire [1:0] _rob_pnr_lsb_T_5 = {1'h0, _rob_pnr_lsb_T_3[1]}; // @[util.scala:383:29]
wire [1:0] _rob_pnr_lsb_T_6 = _rob_pnr_lsb_T_4 | _rob_pnr_lsb_T_5; // @[util.scala:383:{29,45}]
wire [1:0] _rob_pnr_lsb_T_7 = ~_rob_pnr_lsb_T_6; // @[util.scala:383:45]
wire [1:0] _rob_pnr_lsb_T_8 = _rob_pnr_lsb_T_2 | _rob_pnr_lsb_T_7; // @[rob.scala:762:{53,60,62}]
wire _rob_pnr_lsb_T_9 = _rob_pnr_lsb_T_8[0]; // @[OneHot.scala:48:45]
wire _rob_pnr_lsb_T_10 = _rob_pnr_lsb_T_8[1]; // @[OneHot.scala:48:45]
wire _rob_pnr_lsb_T_11 = ~_rob_pnr_lsb_T_9; // @[OneHot.scala:48:45] |
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
| module Tile_64( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_320 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.log2Up
import scala.math._
import consts._
class RecFNToIN(expWidth: Int, sigWidth: Int, intWidth: Int) extends chisel3.Module
{
override def desiredName = s"RecFNToIN_e${expWidth}_s${sigWidth}_i${intWidth}"
val io = IO(new Bundle {
val in = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val signedOut = Input(Bool())
val out = Output(Bits(intWidth.W))
val intExceptionFlags = Output(Bits(3.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(expWidth, sigWidth, io.in)
val magGeOne = rawIn.sExp(expWidth)
val posExp = rawIn.sExp(expWidth - 1, 0)
val magJustBelowOne = !magGeOne && posExp.andR
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
/*------------------------------------------------------------------------
| Assuming the input floating-point value is not a NaN, its magnitude is
| at least 1, and it is not obviously so large as to lead to overflow,
| convert its significand to fixed-point (i.e., with the binary point in a
| fixed location). For a non-NaN input with a magnitude less than 1, this
| expression contrives to ensure that the integer bits of 'alignedSig'
| will all be zeros.
*------------------------------------------------------------------------*/
val shiftedSig =
(magGeOne ## rawIn.sig(sigWidth - 2, 0))<<
Mux(magGeOne,
rawIn.sExp(min(expWidth - 2, log2Up(intWidth) - 1), 0),
0.U
)
val alignedSig =
(shiftedSig>>(sigWidth - 2)) ## shiftedSig(sigWidth - 3, 0).orR
val unroundedInt = 0.U(intWidth.W) | alignedSig>>2
val common_inexact = Mux(magGeOne, alignedSig(1, 0).orR, !rawIn.isZero)
val roundIncr_near_even =
(magGeOne && (alignedSig(2, 1).andR || alignedSig(1, 0).andR)) ||
(magJustBelowOne && alignedSig(1, 0).orR)
val roundIncr_near_maxMag = (magGeOne && alignedSig(1)) || magJustBelowOne
val roundIncr =
(roundingMode_near_even && roundIncr_near_even ) ||
(roundingMode_near_maxMag && roundIncr_near_maxMag) ||
((roundingMode_min || roundingMode_odd) &&
(rawIn.sign && common_inexact)) ||
(roundingMode_max && (!rawIn.sign && common_inexact))
val complUnroundedInt = Mux(rawIn.sign, ~unroundedInt, unroundedInt)
val roundedInt =
Mux(roundIncr ^ rawIn.sign,
complUnroundedInt + 1.U,
complUnroundedInt
) | (roundingMode_odd && common_inexact)
val magGeOne_atOverflowEdge = (posExp === (intWidth - 1).U)
//*** CHANGE TO TAKE BITS FROM THE ORIGINAL 'rawIn.sig' INSTEAD OF FROM
//*** 'unroundedInt'?:
val roundCarryBut2 = unroundedInt(intWidth - 3, 0).andR && roundIncr
val common_overflow =
Mux(magGeOne,
(posExp >= intWidth.U) ||
Mux(io.signedOut,
Mux(rawIn.sign,
magGeOne_atOverflowEdge &&
(unroundedInt(intWidth - 2, 0).orR || roundIncr),
magGeOne_atOverflowEdge ||
((posExp === (intWidth - 2).U) && roundCarryBut2)
),
rawIn.sign ||
(magGeOne_atOverflowEdge &&
unroundedInt(intWidth - 2) && roundCarryBut2)
),
!io.signedOut && rawIn.sign && roundIncr
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val invalidExc = rawIn.isNaN || rawIn.isInf
val overflow = !invalidExc && common_overflow
val inexact = !invalidExc && !common_overflow && common_inexact
val excSign = !rawIn.isNaN && rawIn.sign
val excOut =
Mux((io.signedOut === excSign),
(BigInt(1)<<(intWidth - 1)).U,
0.U
) |
Mux(!excSign, ((BigInt(1)<<(intWidth - 1)) - 1).U, 0.U)
io.out := Mux(invalidExc || common_overflow, excOut, roundedInt)
io.intExceptionFlags := invalidExc ## overflow ## inexact
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToIN_e11_s53_i32_5( // @[RecFNToIN.scala:46:7]
input clock, // @[RecFNToIN.scala:46:7]
input reset, // @[RecFNToIN.scala:46:7]
input [64:0] io_in, // @[RecFNToIN.scala:49:16]
input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16]
input io_signedOut, // @[RecFNToIN.scala:49:16]
output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7]
wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7]
wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18]
wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52]
wire [31:0] io_out; // @[RecFNToIN.scala:46:7]
wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23]
wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27]
wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47]
wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53]
wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}]
wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23]
wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27]
wire [83:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16]
wire [32:0] _alignedSig_T = shiftedSig[83:51]; // @[RecFNToIN.scala:83:49, :89:20]
wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51]
wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}]
wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}]
wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52]
wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}]
wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50]
wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64]
wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39]
wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}]
wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23]
wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}]
wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39]
wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}]
wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}]
wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}]
wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}]
wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}]
wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}]
wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26]
wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56]
wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}]
wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}]
wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35]
wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35]
wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35]
wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28]
wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26]
wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49]
wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}]
wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}]
wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27]
wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45]
wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23]
wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31]
wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31]
wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31]
wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31]
wire [31:0] roundedInt = {_roundedInt_T_3[31:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}]
wire magGeOne_atOverflowEdge = posExp == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43]
wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38]
wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}]
wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}]
wire _common_overflow_T = |(posExp[10:5]); // @[RecFNToIN.scala:62:28, :116:21]
wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42]
wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}]
wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}]
wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64]
wire _common_overflow_T_5 = posExp == 11'h1E; // @[RecFNToIN.scala:62:28, :122:38]
wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}]
wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60]
wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42]
wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42]
wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57]
wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32]
wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20]
wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13]
wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}]
wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41]
wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20]
wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}]
wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20]
wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35]
wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}]
wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}]
wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27]
wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}]
wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13]
wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}]
wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12]
wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30]
assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}]
assign io_out = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18]
wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40]
assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}]
assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52]
assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File INToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class INToRecFN(intWidth: Int, expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"INToRecFN_i${intWidth}_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val signedIn = Input(Bool())
val in = Input(Bits(intWidth.W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val intAsRawFloat = rawFloatFromIN(io.signedIn, io.in);
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
intAsRawFloat.expWidth,
intWidth,
expWidth,
sigWidth,
flRoundOpt_sigMSBitAlwaysZero | flRoundOpt_neverUnderflows
))
roundAnyRawFNToRecFN.io.invalidExc := false.B
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := intAsRawFloat
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromIN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
object rawFloatFromIN
{
def apply(signedIn: Bool, in: Bits): RawFloat =
{
val expWidth = log2Up(in.getWidth) + 1
//*** CHANGE THIS; CAN BE VERY LARGE:
val extIntWidth = 1<<(expWidth - 1)
val sign = signedIn && in(in.getWidth - 1)
val absIn = Mux(sign, -in.asUInt, in.asUInt)
val extAbsIn = (0.U(extIntWidth.W) ## absIn)(extIntWidth - 1, 0)
val adjustedNormDist = countLeadingZeros(extAbsIn)
val sig =
(extAbsIn<<adjustedNormDist)(
extIntWidth - 1, extIntWidth - in.getWidth)
val out = Wire(new RawFloat(expWidth, in.getWidth))
out.isNaN := false.B
out.isInf := false.B
out.isZero := ! sig(in.getWidth - 1)
out.sign := sign
out.sExp := (2.U(2.W) ## ~adjustedNormDist(expWidth - 2, 0)).zext
out.sig := sig
out
}
}
| module INToRecFN_i64_e8_s24_7( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [32:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [32:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_7 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_468( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFN_e8_s24_75( // @[MulAddRecFN.scala:300:7]
input [32:0] io_a, // @[MulAddRecFN.scala:303:16]
input [32:0] io_b, // @[MulAddRecFN.scala:303:16]
input [32:0] io_c, // @[MulAddRecFN.scala:303:16]
output [32:0] io_out // @[MulAddRecFN.scala:303:16]
);
wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15]
wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15]
wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15]
wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15]
wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15]
wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15]
wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15]
wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15]
wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15]
wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15]
wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7]
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7]
wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15]
wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15]
wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7]
wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7]
wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45]
wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50]
MulAddRecFNToRaw_preMul_e8_s24_75 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15]
.io_a (io_a_0), // @[MulAddRecFN.scala:300:7]
.io_b (io_b_0), // @[MulAddRecFN.scala:300:7]
.io_c (io_c_0), // @[MulAddRecFN.scala:300:7]
.io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA),
.io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB),
.io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC),
.io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny),
.io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB),
.io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA),
.io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA),
.io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB),
.io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB),
.io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd),
.io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC),
.io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC),
.io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC),
.io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum),
.io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags),
.io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant),
.io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist),
.io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC),
.io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC)
); // @[MulAddRecFN.scala:317:15]
MulAddRecFNToRaw_postMul_e8_s24_75 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15]
.io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15]
.io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc),
.io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN),
.io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf),
.io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero),
.io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign),
.io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp),
.io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig)
); // @[MulAddRecFN.scala:319:15]
RoundRawFNToRecFN_e8_s24_121 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15]
.io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15]
.io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15]
.io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15]
.io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15]
.io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15]
.io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15]
.io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulAddRecFN.scala:339:15]
assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_50( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundRawFNToRecFN_e8_s24_84( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_84 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Periphery.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.devices.debug
import chisel3._
import chisel3.experimental.{noPrefix, IntParam}
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters}
import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource}
import freechips.rocketchip.jtag.JTAGIO
import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation}
import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget}
import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
/** Protocols used for communicating with external debugging tools */
sealed trait DebugExportProtocol
case object DMI extends DebugExportProtocol
case object JTAG extends DebugExportProtocol
case object CJTAG extends DebugExportProtocol
case object APB extends DebugExportProtocol
/** Options for possible debug interfaces */
case class DebugAttachParams(
protocols: Set[DebugExportProtocol] = Set(DMI),
externalDisable: Boolean = false,
masterWhere: TLBusWrapperLocation = FBUS,
slaveWhere: TLBusWrapperLocation = CBUS
) {
def dmi = protocols.contains(DMI)
def jtag = protocols.contains(JTAG)
def cjtag = protocols.contains(CJTAG)
def apb = protocols.contains(APB)
}
case object ExportDebug extends Field(DebugAttachParams())
class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) {
val clock = Clock()
val reset = Reset()
}
class DebugIO(implicit val p: Parameters) extends Bundle {
val clock = Input(Clock())
val reset = Input(Reset())
val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO()))
val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO)
val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32))))
//------------------------------
val ndreset = Output(Bool())
val dmactive = Output(Bool())
val dmactiveAck = Input(Bool())
val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO())
val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool()))
}
class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO {
}
class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle {
val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool())))
val hartIsInReset = Input(Vec(nComponents, Bool()))
}
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), or exports and hooks up APB,
* based on a global parameter.
*/
trait HasPeripheryDebug { this: BaseSubsystem =>
private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere)
lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
val debugTLDomainOpt = p(DebugModuleKey).map { _ =>
val domain = ClockSinkNode(Seq(ClockSinkParameters()))
domain := tlbus.fixedClockNode
domain
}
lazy val debugOpt = p(DebugModuleKey).map { params =>
val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes))
tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ }
tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
(apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) =>
slave := master
}
tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") {
_ := TLWidthWidget(1) := sb2tl.node
}
}
tlDM
}
val debugNode = debugOpt.map(_.intnode)
val psd = InModuleBody {
val psd = IO(new PSDIO)
psd
}
val resetctrl = InModuleBody {
debugOpt.map { debug =>
debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset
debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock
val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size))
debug.module.io.hartIsInReset := resetctrl.hartIsInReset
resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }}
resetctrl
}
}
// noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603
val debug = InModuleBody { noPrefix(debugOpt.map { debugmod =>
val debug = IO(new DebugIO)
require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined),
"You cannot have both DMI and JTAG interface in HasPeripheryDebug")
require(!(debug.clockeddmi.isDefined && debug.apb.isDefined),
"You cannot have both DMI and APB interface in HasPeripheryDebug")
require(!(debug.systemjtag.isDefined && debug.apb.isDefined),
"You cannot have both APB and JTAG interface in HasPeripheryDebug")
debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg }
(debug.apb
zip apbDebugNodeOpt
zip debugmod.module.io.apb_clock
zip debugmod.module.io.apb_reset).foreach {
case (((io, apb), c ), r) =>
apb.out(0)._1 <> io
c:= io.clock
r:= io.reset
}
debugmod.module.io.debug_reset := debug.reset
debugmod.module.io.debug_clock := debug.clock
debug.ndreset := debugmod.module.io.ctrl.ndreset
debug.dmactive := debugmod.module.io.ctrl.dmactive
debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck
debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}}
// TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down"
debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B }
debug
})}
val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) }
def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey)))
dtm.io.jtag <> sj.jtag
debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS | x }) // force TMS high when debug is disabled
dtm.io.jtag_clock := sj.jtag.TCK
dtm.io.jtag_reset := sj.reset
dtm.io.jtag_mfr_id := sj.mfr_id
dtm.io.jtag_part_number := sj.part_number
dtm.io.jtag_version := sj.version
dtm.rf_reset := sj.reset
debugOpt.map { outerdebug =>
outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi
outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK
outerdebug.module.io.dmi.get.dmiReset := sj.reset
}
dtm
}
}
/** BlackBox to export DMI interface */
class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle {
val clk = Input(Clock())
val reset = Input(Bool())
val debug = new DMIIO
val exit = Output(UInt(32.W))
})
def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = {
io.clk := tbclk
io.reset := tbreset
dutio.dmi <> io.debug
dutio.dmiClock := tbclk
dutio.dmiReset := tbreset
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimDTM.v")
addResource("/csrc/SimDTM.cc")
}
/** BlackBox to export JTAG interface */
class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay)))
with HasBlackBoxResource {
val io = IO(new Bundle {
val clock = Input(Clock())
val reset = Input(Bool())
val jtag = new JTAGIO(hasTRSTn = true)
val enable = Input(Bool())
val init_done = Input(Bool())
val exit = Output(UInt(32.W))
})
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio.TCK := io.jtag.TCK
dutio.TMS := io.jtag.TMS
dutio.TDI := io.jtag.TDI
io.jtag.TDO := dutio.TDO
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
tbsuccess := io.exit === 1.U
assert(io.exit < 2.U, "*** FAILED *** (exit code = %d)\n", io.exit >> 1.U)
}
addResource("/vsrc/SimJTAG.v")
addResource("/csrc/SimJTAG.cc")
addResource("/csrc/remote_bitbang.h")
addResource("/csrc/remote_bitbang.cc")
}
object Debug {
def connectDebug(
debugOpt: Option[DebugIO],
resetctrlOpt: Option[ResetCtrlIO],
psdio: PSDIO,
c: Clock,
r: Bool,
out: Bool,
tckHalfPeriod: Int = 2,
cmdDelay: Int = 2,
psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode()))
(implicit p: Parameters): Unit = {
connectDebugClockAndReset(debugOpt, c)
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }}
debugOpt.map { debug =>
debug.clockeddmi.foreach { d =>
val dtm = Module(new SimDTM).connect(c, r, d, out)
}
debug.systemjtag.foreach { sj =>
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r.asAsyncReset
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
sj.version := p(JtagDTMKey).idcodeVersion.U(4.W)
}
debug.apb.foreach { apb =>
require(false, "No support for connectDebug for an APB debug connection.")
}
psdio.psd.foreach { _ <> psd }
debug.disableDebug.foreach { x => x := false.B }
}
}
def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
debugOpt.foreach { debug =>
val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) |
debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) |
debug.apb.map(_.reset.asBool).getOrElse(false.B)
connectDebugClockHelper(debug, dmi_reset, c, sync)
}
}
def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = {
val debug_reset = Wire(Bool())
withClockAndReset(c, dmi_reset) {
val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset
debug_reset := debug_reset_syncd
}
// Need to clock DM during debug_reset because of synchronous reset, so keep
// the clock alive for one cycle after debug_reset asserts to action this behavior.
// The unit should also be clocked when dmactive is high.
withClockAndReset(c, debug_reset.asAsyncReset) {
val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive
val clock_en = RegNext(next=dmactiveAck, init=true.B)
val gated_clock =
if (!p(DebugModuleKey).get.clockGate) c
else ClockGate(c, clock_en, "debug_clock_gate")
debug.clock := gated_clock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset)
debug.dmactiveAck := dmactiveAck
}
}
def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = {
psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } )
resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }}
debugOpt.map { debug =>
debug.clock := true.B.asClock
debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset)
debug.systemjtag.foreach { sj =>
sj.jtag.TCK := true.B.asClock
sj.jtag.TMS := true.B
sj.jtag.TDI := true.B
sj.jtag.TRSTn.foreach { r => r := true.B }
sj.reset := true.B.asAsyncReset
sj.mfr_id := 0.U
sj.part_number := 0.U
sj.version := 0.U
}
debug.clockeddmi.foreach { d =>
d.dmi.req.valid := false.B
d.dmi.req.bits.addr := 0.U
d.dmi.req.bits.data := 0.U
d.dmi.req.bits.op := 0.U
d.dmi.resp.ready := true.B
d.dmiClock := false.B.asClock
d.dmiReset := true.B.asAsyncReset
}
debug.apb.foreach { apb =>
apb.clock := false.B.asClock
apb.reset := true.B.asAsyncReset
apb.pready := false.B
apb.pslverr := false.B
apb.prdata := 0.U
apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser))
apb.psel := false.B
apb.penable := false.B
}
debug.extTrigger.foreach { t =>
t.in.req := false.B
t.out.ack := t.out.req
}
debug.disableDebug.foreach { x => x := false.B }
debug.dmactiveAck := false.B
debug.ndreset
}.getOrElse(false.B)
}
}
File HasChipyardPRCI.scala:
package chipyard.clocking
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
import testchipip.boot.{TLTileResetCtrl}
import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
case class ChipyardPRCIControlParams(
slaveWhere: TLBusWrapperLocation = CBUS,
baseAddress: BigInt = 0x100000,
enableTileClockGating: Boolean = true,
enableTileResetSetting: Boolean = true,
enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems
) {
def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
}
case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements =>
require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks")
val prciParams = p(ChipyardPRCIControlKey)
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLBuffer()
:= _)
})
// Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
// The diplomatic clocks in the subsystem are routed to this allClockGroupsNode
val clockNamePrefixer = ClockGroupNamePrefixer()
(allClockGroupsNode
:*= clockNamePrefixer
:*= aggregator)
// Once all the clocks are gathered in the aggregator node, several steps remain
// 1. Assign frequencies to any clock groups which did not specify a frequency.
// 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain)
// 3. Synchronize reset to each clock group
// 4. Clock gate the clock groups corresponding to Tiles (if desired).
// 5. Add reset control registers to the tiles (if desired)
// The final clock group here contains physically distinct clock domains, which some PRCI node in a
// diplomatic IOBinder should drive
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
val clockGroupCombiner = ClockGroupCombiner()
val resetSynchronizer = prci_ctrl_domain {
if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer()
}
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
clock_gater
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
reset_setter
} }
if (!prciParams.enableResetSynchronizers) {
println(Console.RED + s"""
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
WARNING:
DISABLING THE RESET SYNCHRONIZERS RESULTS IN
A BROKEN DESIGN THAT WILL NOT BEHAVE
PROPERLY AS ASIC OR FPGA.
THESE SHOULD ONLY BE DISABLED TO WORK AROUND
LIMITATIONS IN ASYNC RESET INITIALIZATION IN
RTL SIMULATORS, NAMELY VERILATOR.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
""" + Console.RESET)
}
// The chiptopClockGroupsNode shouuld be what ClockBinders attach to
val chiptopClockGroupsNode = ClockGroupEphemeralNode()
(aggregator
:= frequencySpecifier
:= clockGroupCombiner
:= resetSynchronizer
:= tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= chiptopClockGroupsNode)
}
File UART.scala:
package sifive.blocks.devices.uart
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.prci._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.util._
/** UART parameters
*
* @param address uart device TL base address
* @param dataBits number of bits in data frame
* @param stopBits number of stop bits
* @param divisorBits width of baud rate divisor
* @param oversample constructs the times of sampling for every data bit
* @param nSamples number of reserved Rx sampling result for decide one data bit
* @param nTxEntries number of entries in fifo between TL bus and Tx
* @param nRxEntries number of entries in fifo between TL bus and Rx
* @param includeFourWire additional CTS/RTS ports for flow control
* @param includeParity parity support
* @param includeIndependentParity Tx and Rx have opposite parity modes
* @param initBaudRate initial baud rate
*
* @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit.
* Calculated in [[UARTAttachParams.attachTo()]]
*
* @example To configure a 8N1 UART with features below:
* {{{
* 8 entries of Tx and Rx fifo
* Baud rate = 115200
* Rx samples each data bit 16 times
* Uses 3 sample result for each data bit
* }}}
* Set the stopBits as below and keep the other parameter unchanged
* {{{
* stopBits = 1
* }}}
*
*/
case class UARTParams(
address: BigInt,
dataBits: Int = 8,
stopBits: Int = 2,
divisorBits: Int = 16,
oversample: Int = 4,
nSamples: Int = 3,
nTxEntries: Int = 8,
nRxEntries: Int = 8,
includeFourWire: Boolean = false,
includeParity: Boolean = false,
includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes
initBaudRate: BigInt = BigInt(115200),
) extends DeviceParams
{
def oversampleFactor = 1 << oversample
require(divisorBits > oversample)
require(oversampleFactor > nSamples)
require((dataBits == 8) || (dataBits == 9))
}
class UARTPortIO(val c: UARTParams) extends Bundle {
val txd = Output(Bool())
val rxd = Input(Bool())
val cts_n = c.includeFourWire.option(Input(Bool()))
val rts_n = c.includeFourWire.option(Output(Bool()))
}
class UARTInterrupts extends Bundle {
val rxwm = Bool()
val txwm = Bool()
}
//abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
/** UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters.
*
* ==Component==
* - Tx
* - Tx fifo
* - Rx
* - Rx fifo
* - TL bus to soc
*
* ==IO==
* [[UARTPortIO]]
*
* ==Datapass==
* {{{
* TL bus -> Tx fifo -> Tx
* TL bus <- Rx fifo <- Rx
* }}}
*
* @param divisorInit: number of clk period for one data bit
*/
class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0)
(implicit p: Parameters)
extends IORegisterRouter(
RegisterRouterParams(
name = "serial",
compat = Seq("sifive,uart0"),
base = c.address,
beatBytes = busWidthBytes),
new UARTPortIO(c))
//with HasInterruptSources {
with HasInterruptSources with HasTLControlRegMap {
def nInterrupts = 1 + c.includeParity.toInt
ResourceBinding {
Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label))
}
require(divisorInit != 0, "UART divisor wasn't initialized during instantiation")
require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit")
lazy val module = new LazyModuleImp(this) {
val txm = Module(new UARTTx(c))
val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries))
val rxm = Module(new UARTRx(c))
val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries))
val div = RegInit(divisorInit.U(c.divisorBits.W))
private val stopCountBits = log2Up(c.stopBits)
private val txCountBits = log2Floor(c.nTxEntries) + 1
private val rxCountBits = log2Floor(c.nRxEntries) + 1
val txen = RegInit(false.B)
val rxen = RegInit(false.B)
val enwire4 = RegInit(false.B)
val invpol = RegInit(false.B)
val enparity = RegInit(false.B)
val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0
val errorparity = RegInit(false.B)
val errie = RegInit(false.B)
val txwm = RegInit(0.U(txCountBits.W))
val rxwm = RegInit(0.U(rxCountBits.W))
val nstop = RegInit(0.U(stopCountBits.W))
val data8or9 = RegInit(true.B)
if (c.includeFourWire){
txm.io.en := txen && (!port.cts_n.get || !enwire4)
txm.io.cts_n.get := port.cts_n.get
}
else
txm.io.en := txen
txm.io.in <> txq.io.deq
txm.io.div := div
txm.io.nstop := nstop
port.txd := txm.io.out
if (c.dataBits == 9) {
txm.io.data8or9.get := data8or9
rxm.io.data8or9.get := data8or9
}
rxm.io.en := rxen
rxm.io.in := port.rxd
rxq.io.enq.valid := rxm.io.out.valid
rxq.io.enq.bits := rxm.io.out.bits
rxm.io.div := div
val tx_busy = (txm.io.tx_busy || txq.io.count.orR) && txen
port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) }
if (c.includeParity) {
txm.io.enparity.get := enparity
txm.io.parity.get := parity
rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx
rxm.io.enparity.get := enparity
errorparity := rxm.io.errorparity.get || errorparity
interrupts(1) := errorparity && errie
}
val ie = RegInit(0.U.asTypeOf(new UARTInterrupts()))
val ip = Wire(new UARTInterrupts)
ip.txwm := (txq.io.count < txwm)
ip.rxwm := (rxq.io.count > rxwm)
interrupts(0) := (ip.txwm && ie.txwm) || (ip.rxwm && ie.rxwm)
val mapping = Seq(
UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"),
NonBlockingEnqueue(txq.io.enq)),
UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"),
NonBlockingDequeue(rxq.io.deq)),
UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq(
RegField(1, txen,
RegFieldDesc("txen","Transmit enable", reset=Some(0))),
RegField(stopCountBits, nstop,
RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))),
UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen,
RegFieldDesc("rxen","Receive enable", reset=Some(0)))),
UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm,
RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))),
UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm,
RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))),
UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq(
RegField(1, ie.txwm,
RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))),
RegField(1, ie.rxwm,
RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))),
UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq(
RegField.r(1, ip.txwm,
RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)),
RegField.r(1, ip.rxwm,
RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))),
UARTCtrlRegs.div -> Seq(
RegField(c.divisorBits, div,
RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit))))
)
val optionalparity = if (c.includeParity) Seq(
UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq(
RegField(1, enparity,
RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))),
RegField(1, parity,
RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))),
RegField(1, errorparity,
RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))),
RegField(1, errie,
RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil
val optionalwire4 = if (c.includeFourWire) Seq(
UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq(
RegField(1, enwire4,
RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))),
RegField(1, invpol,
RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0)))
))) else Nil
val optional8or9 = if (c.dataBits == 9) Seq(
UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq(
RegField(1, data8or9,
RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil
regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_*)
}
}
class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters)
extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap
case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil)
case class UARTAttachParams(
device: UARTParams,
controlWhere: TLBusWrapperLocation = PBUS,
blockerAddr: Option[BigInt] = None,
controlXType: ClockCrossingType = NoCrossing,
intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams
{
def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where {
val name = s"uart_${UART.nextId()}"
val tlbus = where.locateTLBusWrapper(controlWhere)
val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt
val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART")))
val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) }
uart.suggestName(name)
tlbus.coupleTo(s"device_named_$name") { bus =>
val blockerOpt = blockerAddr.map { a =>
val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes)))
tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ }
blocker
}
uartClockDomainWrapper.clockNode := (controlXType match {
case _: SynchronousCrossing =>
tlbus.dtsClk.map(_.bind(uart.device))
tlbus.fixedClockNode
case _: RationalCrossing =>
tlbus.clockNode
case _: AsynchronousCrossing =>
val uartClockGroup = ClockGroup()
uartClockGroup := where.allClockGroupsNode
blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup }
})
(uart.controlXing(controlXType)
:= TLFragmenter(tlbus, Some("UART"))
:= blockerOpt.map { _.node := bus } .getOrElse { bus })
}
(intXType match {
case _: SynchronousCrossing => where.ibus.fromSync
case _: RationalCrossing => where.ibus.fromRational
case _: AsynchronousCrossing => where.ibus.fromAsync
}) := uart.intXing(intXType)
uart
}
}
object UART {
val nextId = { var i = -1; () => { i += 1; i} }
def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = {
val uartNode = node.makeSink()
InModuleBody { uartNode.makeIO()(ValName(name)) }
}
def tieoff(port: UARTPortIO) {
port.rxd := 1.U
if (port.c.includeFourWire) {
port.cts_n.foreach { ct => ct := false.B } // active-low
}
}
def loopback(port: UARTPortIO) {
port.rxd := port.txd
if (port.c.includeFourWire) {
port.cts_n.get := port.rts_n.get
}
}
}
/*
Copyright 2016 SiFive, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File CanHaveClockTap.scala:
package chipyard.clocking
import chisel3._
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
case object ClockTapKey extends Field[Boolean](true)
trait CanHaveClockTap { this: BaseSubsystem =>
require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO")
val clockTapNode = Option.when(p(ClockTapKey)) {
val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
clockTap := ClockGroup() := allClockGroupsNode
clockTap
}
val clockTapIO = clockTapNode.map { node => InModuleBody {
val clock_tap = IO(Output(Clock()))
clock_tap := node.in.head._1.clock
clock_tap
}}
}
File PeripheryBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices}
import freechips.rocketchip.diplomacy.BufferParams
import freechips.rocketchip.tilelink.{
RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode,
TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge
}
import freechips.rocketchip.util.Location
case class BusAtomics(
arithmetic: Boolean = true,
buffer: BufferParams = BufferParams.default,
widenBytes: Option[Int] = None
)
case class PeripheryBusParams(
beatBytes: Int,
blockBytes: Int,
atomics: Option[BusAtomics] = Some(BusAtomics()),
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with HasRegionReplicatorParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = {
val pbus = LazyModule(new PeripheryBus(this, loc.name))
pbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> pbus)
pbus
}
}
class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
override lazy val desiredName = s"PeripheryBus_$name"
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
private val node: TLNode = params.atomics.map { pa =>
val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in")))
val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out")))
val fixer_node = replicator.map(fixer.node :*= _.node).getOrElse(fixer.node)
(out_xbar.node
:*= fixer_node
:*= TLBuffer(pa.buffer)
:*= (pa.widenBytes.filter(_ > beatBytes).map { w =>
TLWidthWidget(w) :*= TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name))
} .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) })
:*= in_xbar.node)
} .getOrElse { TLXbar() :*= fixer.node }
def inwardNode: TLInwardNode = node
def outwardNode: TLOutwardNode = node
def busView: TLEdge = fixer.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File HasTiles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering}
import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink}
import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq}
import freechips.rocketchip.tilelink.TLWidthWidget
import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing}
import freechips.rocketchip.rocket.TracedInstruction
import freechips.rocketchip.util.TraceCoreInterface
import scala.collection.immutable.SortedMap
/** Entry point for Config-uring the presence of Tiles */
case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil)
/** List of HierarchicalLocations which might contain a Tile */
case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil)
/** For determining static tile id */
case object NumTiles extends Field[Int](0)
/** Whether to add timing-closure registers along the path of the hart id
* as it propagates through the subsystem and into the tile.
*
* These are typically only desirable when a dynamically programmable prefix is being combined
* with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]].
*/
case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false)
/** Whether per-tile hart ids are going to be driven as inputs into a HasTiles block,
* and if so, what their width should be.
*/
case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None)
/** Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block.
*
* Unlike the hart ids, the reset vector width is determined by the sinks within the tiles,
* based on the size of the address map visible to the tiles.
*/
case object HasTilesExternalResetVectorKey extends Field[Boolean](true)
/** These are sources of "constants" that are driven into the tile.
*
* While they are not expected to change dyanmically while the tile is executing code,
* they may be either tied to a contant value or programmed during boot or reset.
* They need to be instantiated before tiles are attached within the subsystem containing them.
*/
trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements =>
/** tileHartIdNode is used to collect publishers and subscribers of hartids. */
val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes.
*
* Each "prefix" input is actually the same full width as the outer hart id; the expected usage
* is that each prefix source would set only some non-overlapping portion of the bits to non-zero values.
* This node orReduces them, and further combines the reduction with the static ids assigned to each tile,
* producing a unique, dynamic hart id for each tile.
*
* If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered.
*
* The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into
* the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous.
*/
val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i =>
val y = dontTouch(prefix | totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup
if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y
},
default = Some(() => 0.U(p(MaxHartIdBits).W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
// TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs
/** tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. */
val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i =>
(i, BundleBridgeEphemeralNode[UInt]())
}.to(SortedMap)
/** tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. */
val tileResetVectorNexusNode = BundleBroadcast[UInt](
inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below
)
/** tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids.
*
* Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile.
*/
val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match {
case Some(w) => (0 until nTotalTiles).map { i =>
val hartIdSource = BundleBridgeSource(() => UInt(w.W))
tileHartIdNodes(i) := hartIdSource
hartIdSource
}
case None => {
(0 until nTotalTiles).map { i => tileHartIdNodes(i) :*= tileHartIdNexusNode }
Nil
}
}
/** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors.
*
* Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile.
*/
val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match {
case true => (0 until nTotalTiles).map { i =>
val resetVectorSource = BundleBridgeSource[UInt]()
tileResetVectorNodes(i) := resetVectorSource
resetVectorSource
}
case false => {
(0 until nTotalTiles).map { i => tileResetVectorNodes(i) :*= tileResetVectorNexusNode }
Nil
}
}
}
/** These are sinks of notifications that are driven out from the tile.
*
* They need to be instantiated before tiles are attached to the subsystem containing them.
*/
trait HasTileNotificationSinks { this: LazyModule =>
val tileHaltXbarNode = IntXbar()
val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
tileHaltSinkNode := tileHaltXbarNode
val tileWFIXbarNode = IntXbar()
val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
tileWFISinkNode := tileWFIXbarNode
val tileCeaseXbarNode = IntXbar()
val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
tileCeaseSinkNode := tileCeaseXbarNode
}
/** Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources.
*
* Sub-classes of this trait can optionally override the individual connect functions in order to specialize
* their attachment behaviors, but most use cases should be be handled simply by changing the implementation
* of the injectNode functions in crossingParams.
*/
trait CanAttachTile {
type TileType <: BaseTile
type TileContextType <: DefaultHierarchicalElementContextType
def tileParams: InstantiableTileParams[TileType]
def crossingParams: HierarchicalElementCrossingParamsLike
/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
})
tile_prci_domain
}
/** A default set of connections that need to occur for most tile types */
def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
connectMasterPorts(domain, context)
connectSlavePorts(domain, context)
connectInterrupts(domain, context)
connectPRC(domain, context)
connectOutputNotifications(domain, context)
connectInputConstants(domain, context)
connectTrace(domain, context)
}
/** Connect the port where the tile is the master to a TileLink interconnect. */
def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
val dataBus = context.locateTLBusWrapper(crossingParams.master.where)
dataBus.coupleFrom(tileParams.baseName) { bus =>
bus :=* crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType)
}
}
/** Connect the port where the tile is the slave to a TileLink interconnect. */
def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = {
implicit val p = context.p
DisableMonitors { implicit p =>
val controlBus = context.locateTLBusWrapper(crossingParams.slave.where)
controlBus.coupleTo(tileParams.baseName) { bus =>
domain.crossSlavePort(crossingParams.crossingType) :*= crossingParams.slave.injectNode(context) :*= TLWidthWidget(controlBus.beatBytes) :*= bus
}
}
}
/** Connect the various interrupts sent to and and raised by the tile. */
def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
// NOTE: The order of calls to := matters! They must match how interrupts
// are decoded from tile.intInwardNode inside the tile. For this reason,
// we stub out missing interrupts with constant sources here.
// 1. Debug interrupt is definitely asynchronous in all cases.
domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } :=
context.debugNodes(domain.element.tileId)
// 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively,
// so might need to be synchronized depending on the Tile's crossing type.
// From CLINT: "msip" and "mtip"
context.msipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.msipNodes(domain.element.tileId)
}
// From PLIC: "meip"
context.meipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.meipNodes(domain.element.tileId)
}
// From PLIC: "seip" (only if supervisor mode is enabled)
if (domain.element.tileParams.core.hasSupervisorMode) {
context.seipDomain {
domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) :=
context.seipNodes(domain.element.tileId)
}
}
// 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock.
// (they are connected to domain.element.intInwardNode in a seperate trait)
// 4. Interrupts coming out of the tile are sent to the PLIC,
// so might need to be synchronized depending on the Tile's crossing type.
context.tileToPlicNodes.get(domain.element.tileId).foreach { node =>
FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out =>
context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) }
}}
}
// 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock.
domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId))
}
/** Notifications of tile status are connected to be broadcast without needing to be clock-crossed. */
def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
domain {
context.tileHaltXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.haltNode)
context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode)
context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode)
}
// TODO should context be forced to have a trace sink connected here?
// for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally
}
/** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. */
def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere)
domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId)
domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId)
tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ }
}
/** Connect power/reset/clock resources. */
def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where)
(crossingParams.crossingType match {
case _: SynchronousCrossing | _: CreditedCrossing =>
if (crossingParams.forceSeparateClockReset) {
domain.clockNode := tlBusToGetClockDriverFrom.clockNode
} else {
domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode
}
case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode
case _: AsynchronousCrossing => {
val tileClockGroup = ClockGroup()
tileClockGroup := context.allClockGroupsNode
domain.clockNode := tileClockGroup
}
})
domain {
domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode
}
}
/** Function to handle all trace crossings when tile is instantiated inside domains */
def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = {
implicit val p = context.p
val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle](
resetCrossingType = crossingParams.resetCrossingType)
context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode
val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface](
resetCrossingType = crossingParams.resetCrossingType)
context.traceCoreNodes(domain.element.tileId) :*= traceCoreCrossingNode := domain.element.traceCoreNode
}
}
case class CloneTileAttachParams(
sourceTileId: Int,
cloneParams: CanAttachTile
) extends CanAttachTile {
type TileType = cloneParams.TileType
type TileContextType = cloneParams.TileContextType
def tileParams = cloneParams.tileParams
def crossingParams = cloneParams.crossingParams
override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = {
require(instantiatedTiles.contains(sourceTileId))
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName))
val tile_prci_domain = CloneLazyModule(
new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self =>
val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) }
},
instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]]
)
tile_prci_domain
}
}
File BusWrapper.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding}
// TODO This class should be moved to package subsystem to resolve
// the dependency awkwardness of the following imports
import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices}
import freechips.rocketchip.prci.{
ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode,
FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain,
ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing
}
import freechips.rocketchip.subsystem.{
HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations,
CanInstantiateWithinContextThatHasTileLinkLocations
}
import freechips.rocketchip.util.Location
/** Specifies widths of various attachement points in the SoC */
trait HasTLBusParams {
def beatBytes: Int
def blockBytes: Int
def beatBits: Int = beatBytes * 8
def blockBits: Int = blockBytes * 8
def blockBeats: Int = blockBytes / beatBytes
def blockOffset: Int = log2Up(blockBytes)
def dtsFrequency: Option[BigInt]
def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0))
require (isPow2(beatBytes))
require (isPow2(blockBytes))
}
abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters)
extends ClockDomain
with HasTLBusParams
with CanHaveBuiltInDevices
{
private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups")
private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true })
val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here
val clockNode = clockGroup.node
val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here
private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt)))
clockGroup.node := clockGroupAggregator.node
fixedClockNode := clockGroup.node // first member of group is always domain's own clock
clockSinkNode := fixedClockNode
InModuleBody {
// make sure the above connections work properly because mismatched-by-name signals will just be ignored.
(clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) =>
require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}")
}
}
def clockBundle = clockSinkNode.in.head._1
def beatBytes = params.beatBytes
def blockBytes = params.blockBytes
def dtsFrequency = params.dtsFrequency
val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption
/* If you violate this requirement, you will have a rough time.
* The codebase is riddled with the assumption that this is true.
*/
require(blockBytes >= beatBytes)
def inwardNode: TLInwardNode
def outwardNode: TLOutwardNode
def busView: TLEdge
def prefixNode: Option[BundleBridgeNode[UInt]]
def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers)
def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing"))
def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing"))
def generateSynchronousDomain(domainName: String): ClockSinkDomain = {
val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName)))
domain.clockNode := fixedClockNode
domain
}
def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("")
protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W)))
def to[T](name: String)(body: => T): T = {
this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } }
}
def from[T](name: String)(body: => T): T = {
this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } }
}
def coupleTo[T](name: String)(gen: TLOutwardNode => T): T =
to(name) { gen(TLNameNode("tl") :*=* outwardNode) }
def coupleFrom[T](name: String)(gen: TLInwardNode => T): T =
from(name) { gen(inwardNode :*=* TLNameNode("tl")) }
def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
coupleTo(s"bus_named_${bus.busName}") {
bus.crossInHelper(xType) :*= TLWidthWidget(beatBytes) :*= _
}
}
def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = {
bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode)
coupleFrom(s"bus_named_${bus.busName}") {
_ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType)
}
}
}
trait TLBusWrapperInstantiationLike {
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper
}
trait TLBusWrapperConnectionLike {
val xType: ClockCrossingType
def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit
}
object TLBusWrapperConnection {
/** Backwards compatibility factory for master driving clock and slave setting cardinality */
def crossTo(
xType: ClockCrossingType,
driveClockFromMaster: Option[Boolean] = Some(true),
nodeBinding: NodeBinding = BIND_STAR,
flipRendering: Boolean = false) = {
apply(xType, driveClockFromMaster, nodeBinding, flipRendering)(
slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) })
}
/** Backwards compatibility factory for slave driving clock and master setting cardinality */
def crossFrom(
xType: ClockCrossingType,
driveClockFromMaster: Option[Boolean] = Some(false),
nodeBinding: NodeBinding = BIND_QUERY,
flipRendering: Boolean = true) = {
apply(xType, driveClockFromMaster, nodeBinding, flipRendering)(
masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) })
}
/** Factory for making generic connections between TLBusWrappers */
def apply
(xType: ClockCrossingType = NoCrossing,
driveClockFromMaster: Option[Boolean] = None,
nodeBinding: NodeBinding = BIND_ONCE,
flipRendering: Boolean = false)(
slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode },
masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode },
inject: Parameters => TLNode = { _ => TLTempNode() }) = {
new TLBusWrapperConnection(
xType, driveClockFromMaster, nodeBinding, flipRendering)(
slaveNodeView, masterNodeView, inject)
}
}
/** TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers.
* It has the following serializable parameters:
* - xType: What type of TL clock crossing adapter to insert between the buses.
* The appropriate half of the crossing adapter ends up inside each bus.
* - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode,
* otherwise have either the master or the slave bus bind the other one's clockGroupNode,
* assuming the inserted crossing type is not asynchronous.
* - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection.
* - flipRendering: fine-grained control of the graphML rendering of the connection.
* If has the following non-serializable parameters:
* - slaveNodeView: programmatic control of the specific attachment point within the slave bus.
* - masterNodeView: programmatic control of the specific attachment point within the master bus.
* - injectNode: programmatic injection of additional nodes into the middle of the connection.
* The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s.
*/
class TLBusWrapperConnection
(val xType: ClockCrossingType,
val driveClockFromMaster: Option[Boolean],
val nodeBinding: NodeBinding,
val flipRendering: Boolean)
(slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode,
masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode,
inject: Parameters => TLNode)
extends TLBusWrapperConnectionLike
{
def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = {
val masterTLBus = context.locateTLBusWrapper(master)
val slaveTLBus = context.locateTLBusWrapper(slave)
def bindClocks(implicit p: Parameters) = driveClockFromMaster match {
case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode)
case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode)
case None =>
}
def bindTLNodes(implicit p: Parameters) = nodeBinding match {
case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p)
case BIND_QUERY => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p)
case BIND_STAR => slaveNodeView(slaveTLBus, p) :*= TLWidthWidget(masterTLBus.beatBytes) :*= inject(p) :*= masterNodeView(masterTLBus, p)
case BIND_FLEX => slaveNodeView(slaveTLBus, p) :*=* TLWidthWidget(masterTLBus.beatBytes) :*=* inject(p) :*=* masterNodeView(masterTLBus, p)
}
if (flipRendering) { FlipRendering { implicit p =>
bindClocks(implicitly[Parameters])
slaveTLBus.from(s"bus_named_${masterTLBus.busName}") {
bindTLNodes(implicitly[Parameters])
}
} } else {
bindClocks(implicitly[Parameters])
masterTLBus.to (s"bus_named_${slaveTLBus.busName}") {
bindTLNodes(implicitly[Parameters])
}
}
}
}
class TLBusWrapperTopology(
val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)],
val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)]
) extends CanInstantiateWithinContextThatHasTileLinkLocations
with CanConnectWithinContextThatHasTileLinkLocations
{
def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = {
instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } }
}
def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = {
connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } }
}
}
trait HasTLXbarPhy { this: TLBusWrapper =>
private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar")
override def shouldBeInlined = xbar.node.circuitIdentity
def inwardNode: TLInwardNode = xbar.node
def outwardNode: TLOutwardNode = xbar.node
def busView: TLEdge = xbar.node.edges.in.head
}
case class AddressAdjusterWrapperParams(
blockBytes: Int,
beatBytes: Int,
replication: Option[ReplicatedRegion],
forceLocal: Seq[AddressSet] = Nil,
localBaseAddressDefault: Option[BigInt] = None,
policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile,
ordered: Boolean = true
)
extends HasTLBusParams
with TLBusWrapperInstantiationLike
{
val dtsFrequency = None
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = {
val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name))
aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper")
context.tlBusWrapperLocationMap += (loc -> aaWrapper)
aaWrapper
}
}
class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) {
private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) }
private val viewNode = TLIdentityNode()
val inwardNode: TLInwardNode = address_adjuster.map(_.node :*=* TLFIFOFixer(params.policy) :*=* viewNode).getOrElse(viewNode)
def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode)
def busView: TLEdge = viewNode.edges.in.head
val prefixNode = address_adjuster.map { a =>
a.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
val builtInDevices = BuiltInDevices.none
override def shouldBeInlined = !params.replication.isDefined
}
case class TLJBarWrapperParams(
blockBytes: Int,
beatBytes: Int
)
extends HasTLBusParams
with TLBusWrapperInstantiationLike
{
val dtsFrequency = None
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = {
val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name))
jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper")
context.tlBusWrapperLocationMap += (loc -> jbarWrapper)
jbarWrapper
}
}
class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) {
private val jbar = LazyModule(new TLJbar)
val inwardNode: TLInwardNode = jbar.node
val outwardNode: TLOutwardNode = jbar.node
def busView: TLEdge = jbar.node.edges.in.head
val prefixNode = None
val builtInDevices = BuiltInDevices.none
override def shouldBeInlined = jbar.node.circuitIdentity
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File ClockGroupCombiner.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
object ClockGroupCombiner {
def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = {
LazyModule(new ClockGroupCombiner()).node
}
}
case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil)
// All clock groups with a name containing any substring in names will be combined into a single clock group
class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => {
case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) =>
(grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n)))
}
})
/** This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey
* The ClockGroupCombinersKey contains a list of tuples of:
* - The name of the combined group
* - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node
* This node will fail if
* - Multiple grouping functions match a single clock group
* - A grouping function matches zero clock groups
* - A grouping function matches clock groups with different requested frequncies
*/
class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule {
val combiners = p(ClockGroupCombinerKey)
val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m }
val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u =>
var i = 0
val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) =>
val (g, r) = rest.partition(c(_))
val name = combiners(i)._1
i = i + 1
require(g.size >= 1)
val names = g.map(_.name.getOrElse("unamed"))
val takes = g.map(_.take).flatten
require(takes.distinct.size <= 1,
s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}")
require(takes.size > 0,
s"Clock group '$name' has no inheritable frequencies")
(grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r)
}
ClockGroupSinkParameters(
name = u.name,
members = grouped ++ rest
)
}
val node = ClockGroupAdapterNode(sourceFn, sinkFn)
lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, oe), (i, ie)) =>
{
val inMap = (i.member.data zip ie.sink.members).map { case (id, im) =>
im.name.get -> id
}.toMap
(o.member.data zip oe.sink.members).map { case (od, om) =>
val matches = combiners.filter(c => c._2(om))
require(matches.size <= 1)
if (matches.size == 0) {
od := inMap(om.name.get)
} else {
od := inMap(matches(0)._1)
}
}
}
}
}
}
File Integration.scala:
package rerocc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem._
import boom.v4.common.{BoomTile}
import shuttle.common.{ShuttleTile}
import rerocc.client._
import rerocc.manager._
import rerocc.bus._
case object ReRoCCControlBus extends Field[TLBusWrapperLocation](CBUS)
case object ReRoCCNoCKey extends Field[Option[ReRoCCNoCParams]](None)
trait CanHaveReRoCCTiles { this: BaseSubsystem with InstantiatesHierarchicalElements with constellation.soc.CanHaveGlobalNoC =>
// WARNING: Not multi-clock safe
val reRoCCClients = totalTiles.values.map { t => t match {
case r: RocketTile => r.roccs collect { case r: ReRoCCClient => (t, r) }
case b: BoomTile => b.roccs collect { case r: ReRoCCClient => (t, r) }
case s: ShuttleTile => s.roccs collect { case r: ReRoCCClient => (t, r) } // Added for shuttle
case _ => Nil
}}.flatten
val reRoCCManagerIds = (0 until p(ReRoCCTileKey).size)
val reRoCCManagerIdNexusNode = LazyModule(new BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](false) _,
outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => {
dontTouch(prefix | reRoCCManagerIds(i).U(7.W)) // dontTouch to keep constant prop from breaking tile dedup
}},
default = Some(() => 0.U(7.W)),
inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below
shouldBeInlined = false // can't inline something whose output we are are dontTouching
)).node
val reRoCCManagers = p(ReRoCCTileKey).zipWithIndex.map { case (g,i) =>
val rerocc_prci_domain = locateTLBusWrapper(SBUS).generateSynchronousDomain.suggestName(s"rerocc_prci_domain_$i")
val rerocc_tile = rerocc_prci_domain { LazyModule(new ReRoCCManagerTile(
g.copy(reroccId = i, pgLevels = reRoCCClients.head._2.pgLevels), p)) }
println(s"ReRoCC Manager id $i is a ${rerocc_tile.rocc}")
locateTLBusWrapper(SBUS).coupleFrom(s"port_named_rerocc_$i") {
(_ :=* TLBuffer() :=* rerocc_tile.tlNode)
}
locateTLBusWrapper(SBUS).coupleTo(s"sport_named_rerocc_$i") {
(rerocc_tile.stlNode :*= TLBuffer() :*= TLWidthWidget(locateTLBusWrapper(SBUS).beatBytes) :*= TLBuffer() :*= _)
}
val ctrlBus = locateTLBusWrapper(p(ReRoCCControlBus))
ctrlBus.coupleTo(s"port_named_rerocc_ctrl_$i") {
val remapper = ctrlBus { LazyModule(new ReRoCCManagerControlRemapper(i)) }
(rerocc_tile.ctrl.ctrlNode := remapper.node := _)
}
rerocc_tile.reroccManagerIdSinkNode := reRoCCManagerIdNexusNode
rerocc_tile
}
require(!(reRoCCManagers.isEmpty ^ reRoCCClients.isEmpty))
if (!reRoCCClients.isEmpty) {
require(reRoCCClients.map(_._2).forall(_.pgLevels == reRoCCClients.head._2.pgLevels))
require(reRoCCClients.map(_._2).forall(_.xLen == 64))
val rerocc_bus_domain = locateTLBusWrapper(SBUS).generateSynchronousDomain
rerocc_bus_domain {
val rerocc_bus = p(ReRoCCNoCKey).map { k =>
if (k.useGlobalNoC) {
globalNoCDomain { LazyModule(new ReRoCCGlobalNoC(k)) }
} else {
LazyModule(new ReRoCCNoC(k))
}
}.getOrElse(LazyModule(new ReRoCCXbar()))
reRoCCClients.foreach { case (t, c) => rerocc_bus.node := ReRoCCBuffer() := t { ReRoCCBuffer() := c.reRoCCNode } }
reRoCCManagers.foreach { m => m.reRoCCNode := rerocc_bus.node }
}
}
}
File DigitalTop.scala:
package chipyard
import chisel3._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.system._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.devices.tilelink._
// ------------------------------------
// BOOM and/or Rocket Top Level Systems
// ------------------------------------
// DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface
with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface
with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C
with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device
with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller
with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget
with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget
with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators
{
override lazy val module = new DigitalTopModule(this)
}
class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l)
with freechips.rocketchip.util.DontTouch
// DOC include end: DigitalTop
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File FrontBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams}
import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy}
import freechips.rocketchip.util.{Location}
case class FrontBusParams(
beatBytes: Int,
blockBytes: Int,
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = {
val fbus = LazyModule(new FrontBus(this, loc.name))
fbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> fbus)
fbus
}
}
class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters)
extends TLBusWrapper(params, name)
with HasTLXbarPhy {
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
val prefixNode = None
}
File PeripheryTLSerial.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.prci._
import testchipip.util.{ClockedIO}
import testchipip.soc.{OBUS}
// Parameters for a read-only-memory that appears over serial-TL
case class ManagerROMParams(
address: BigInt = 0x20000,
size: Int = 0x10000,
contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE
// Parameters for a read/write memory that appears over serial-TL
case class ManagerRAMParams(
address: BigInt,
size: BigInt)
// Parameters for a coherent cacheable read/write memory that appears over serial-TL
case class ManagerCOHParams(
address: BigInt,
size: BigInt)
// Parameters for a set of memory regions that appear over serial-TL
case class SerialTLManagerParams(
memParams: Seq[ManagerRAMParams] = Nil,
romParams: Seq[ManagerROMParams] = Nil,
cohParams: Seq[ManagerCOHParams] = Nil,
isMemoryDevice: Boolean = false,
sinkIdBits: Int = 8,
totalIdBits: Int = 8,
cacheIdBits: Int = 2,
slaveWhere: TLBusWrapperLocation = OBUS
)
// Parameters for a TL client which may probe this system over serial-TL
case class SerialTLClientParams(
totalIdBits: Int = 8,
cacheIdBits: Int = 2,
masterWhere: TLBusWrapperLocation = FBUS,
supportsProbe: Boolean = false
)
// The SerialTL can be configured to be bidirectional if serialTLManagerParams is set
case class SerialTLParams(
client: Option[SerialTLClientParams] = None,
manager: Option[SerialTLManagerParams] = None,
phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(),
bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS)
case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil)
trait CanHavePeripheryTLSerial { this: BaseSubsystem =>
private val portName = "serial-tl"
val tlChannels = 5
val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) =>
val name = s"serial_tl_$sid"
lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere))
lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere))
val clientPortParams = params.client.map { c => TLMasterPortParameters.v1(
clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1(
name = s"serial_tl_${sid}_${i}",
sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)),
supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none
)}
)}
val managerPortParams = params.manager.map { m =>
val memParams = m.memParams
val romParams = m.romParams
val cohParams = m.cohParams
val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil)
val romDevice = new SimpleDevice("lbwif-readonly", Nil)
val blockBytes = manager_bus.get.blockBytes
TLSlavePortParameters.v1(
managers = memParams.map { memParams => TLSlaveParameters.v1(
address = AddressSet.misaligned(memParams.address, memParams.size),
resources = memDevice.reg,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsGet = TransferSizes(1, blockBytes),
supportsPutFull = TransferSizes(1, blockBytes),
supportsPutPartial = TransferSizes(1, blockBytes)
)} ++ romParams.map { romParams => TLSlaveParameters.v1(
address = List(AddressSet(romParams.address, romParams.size-1)),
resources = romDevice.reg,
regionType = RegionType.UNCACHED, // cacheable
executable = true,
supportsGet = TransferSizes(1, blockBytes),
fifoId = Some(0)
)} ++ cohParams.map { cohParams => TLSlaveParameters.v1(
address = AddressSet.misaligned(cohParams.address, cohParams.size),
regionType = RegionType.TRACKED, // cacheable
executable = true,
supportsAcquireT = TransferSizes(1, blockBytes),
supportsAcquireB = TransferSizes(1, blockBytes),
supportsGet = TransferSizes(1, blockBytes),
supportsPutFull = TransferSizes(1, blockBytes),
supportsPutPartial = TransferSizes(1, blockBytes)
)},
beatBytes = manager_bus.get.beatBytes,
endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits),
minLatency = 1
)
}
val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid")))
serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode
if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined,
s"Manager bus ${manager_bus.get.busName} must provide a frequency")
if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined,
s"Client bus ${client_bus.get.busName} must provide a frequency")
if (manager_bus.isDefined && client_bus.isDefined) {
val managerFreq = manager_bus.get.dtsFrequency.get
val clientFreq = client_bus.get.dtsFrequency.get
require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq")
}
val serdesser = serial_tl_domain { LazyModule(new TLSerdesser(
flitWidth = params.phyParams.flitWidth,
clientPortParams = clientPortParams,
managerPortParams = managerPortParams,
bundleParams = params.bundleParams,
nameSuffix = Some(name)
)) }
serdesser.managerNode.foreach { managerNode =>
val maxClients = 1 << params.manager.get.cacheIdBits
val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits)
manager_bus.get.coupleTo(s"port_named_${name}_out") {
(managerNode
:= TLProbeBlocker(p(CacheBlockBytes))
:= TLSourceAdjuster(maxClients, maxIdsPerClient)
:= TLSourceCombiner(maxIdsPerClient)
:= TLWidthWidget(manager_bus.get.beatBytes)
:= _)
}
}
serdesser.clientNode.foreach { clientNode =>
client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode }
}
// If we provide a clock, generate a clock domain for the outgoing clock
val serial_tl_clock_freqMHz = params.phyParams match {
case params: InternalSyncSerialPhyParams => Some(params.freqMHz)
case params: ExternalSyncSerialPhyParams => None
case params: SourceSyncSerialPhyParams => Some(params.freqMHz)
}
val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f =>
serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) }
}
serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode)
val inner_io = serial_tl_domain { InModuleBody {
val inner_io = IO(params.phyParams.genIO).suggestName(name)
inner_io match {
case io: InternalSyncPhitIO => {
// Outer clock comes from the clock node. Synchronize the serdesser's reset to that
// clock to get the outer reset
val outer_clock = serial_tl_clock_node.get.in.head._1.clock
io.clock_out := outer_clock
val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams))
phy.io.outer_clock := outer_clock
phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool)
phy.io.inner_clock := serdesser.module.clock
phy.io.inner_reset := serdesser.module.reset
phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth))
phy.io.inner_ser <> serdesser.module.io.ser
}
case io: ExternalSyncPhitIO => {
// Outer clock comes from the IO. Synchronize the serdesser's reset to that
// clock to get the outer reset
val outer_clock = io.clock_in
val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool)
val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams))
phy.io.outer_clock := outer_clock
phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool)
phy.io.inner_clock := serdesser.module.clock
phy.io.inner_reset := serdesser.module.reset
phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth))
phy.io.inner_ser <> serdesser.module.io.ser
}
case io: SourceSyncPhitIO => {
// 3 clock domains -
// - serdesser's "Inner clock": synchronizes signals going to the digital logic
// - outgoing clock: synchronizes signals going out
// - incoming clock: synchronizes signals coming in
val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock
val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool)
val incoming_clock = io.clock_in
val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool)
io.clock_out := outgoing_clock
io.reset_out := outgoing_reset.asAsyncReset
val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams))
phy.io.incoming_clock := incoming_clock
phy.io.incoming_reset := incoming_reset
phy.io.outgoing_clock := outgoing_clock
phy.io.outgoing_reset := outgoing_reset
phy.io.inner_clock := serdesser.module.clock
phy.io.inner_reset := serdesser.module.reset
phy.io.inner_ser <> serdesser.module.io.ser
phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth))
}
}
inner_io
}}
val outer_io = InModuleBody {
val outer_io = IO(params.phyParams.genIO).suggestName(name)
outer_io <> inner_io
outer_io
}
val inner_debug_io = serial_tl_domain { InModuleBody {
val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug")
inner_debug_io := serdesser.module.io.debug
inner_debug_io
}}
val outer_debug_io = InModuleBody {
val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug")
outer_debug_io := inner_debug_io
outer_debug_io
}
(serdesser, outer_io, outer_debug_io)
}.unzip3
}
File CustomBootPin.scala:
package testchipip.boot
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
case class CustomBootPinParams(
customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE
masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS
)
case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None)
trait CanHavePeripheryCustomBootPin { this: BaseSubsystem =>
val custom_boot_pin = p(CustomBootPinKey).map { params =>
require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg")
val tlbus = locateTLBusWrapper(params.masterWhere)
val clientParams = TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1(
name = "custom-boot",
sourceId = IdRange(0, 1),
)),
minLatency = 1
)
val inner_io = tlbus {
val node = TLClientNode(Seq(clientParams))
tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node })
InModuleBody {
val custom_boot = IO(Input(Bool())).suggestName("custom_boot")
val (tl, edge) = node.out(0)
val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6)
val state = RegInit(inactive)
tl.a.valid := false.B
tl.a.bits := DontCare
tl.d.ready := true.B
switch (state) {
is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } }
is (waiting_bootaddr_reg_a) {
tl.a.valid := true.B
tl.a.bits := edge.Put(
toAddress = p(BootAddrRegKey).get.bootRegAddress.U,
fromSource = 0.U,
lgSize = 2.U,
data = params.customBootAddress.U
)._2
when (tl.a.fire) { state := waiting_bootaddr_reg_d }
}
is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } }
is (waiting_msip_a) {
tl.a.valid := true.B
tl.a.bits := edge.Put(
toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0
fromSource = 0.U,
lgSize = log2Ceil(CLINTConsts.msipBytes).U,
data = 1.U
)._2
when (tl.a.fire) { state := waiting_msip_d }
}
is (waiting_msip_d) { when (tl.d.fire) { state := dead } }
is (dead) { when (!custom_boot) { state := inactive } }
}
custom_boot
}
}
val outer_io = InModuleBody {
val custom_boot = IO(Input(Bool())).suggestName("custom_boot")
inner_io := custom_boot
custom_boot
}
outer_io
}
}
File SystemBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.tilelink.{
BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams
}
import freechips.rocketchip.tilelink.{
TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper,
TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode,
TLFIFOFixer, TLTempNode
}
import freechips.rocketchip.util.Location
case class SystemBusParams(
beatBytes: Int,
blockBytes: Int,
policy: TLArbiter.Policy = TLArbiter.roundRobin,
dtsFrequency: Option[BigInt] = None,
zeroDevice: Option[BuiltInZeroDeviceParams] = None,
errorDevice: Option[BuiltInErrorDeviceParams] = None,
replication: Option[ReplicatedRegion] = None)
extends HasTLBusParams
with HasBuiltInDeviceParams
with TLBusWrapperInstantiationLike
{
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = {
val sbus = LazyModule(new SystemBus(this, loc.name))
sbus.suggestName(loc.name)
context.tlBusWrapperLocationMap += (loc -> sbus)
sbus
}
}
class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters)
extends TLBusWrapper(params, name)
{
private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r)))
val prefixNode = replicator.map { r =>
r.prefix := addressPrefixNexusNode
addressPrefixNexusNode
}
private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name)))
val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode())
val outwardNode: TLOutwardNode = system_bus_xbar.node
def busView: TLEdge = system_bus_xbar.node.edges.in.head
val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode)
}
File ClockGroupNamePrefixer.scala:
package chipyard.clocking
import chisel3._
import org.chipsalliance.cde.config.{Parameters, Config, Field}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
case object ClockFrequencyAssignersKey extends Field[Seq[(String) => Option[Double]]](Seq.empty)
class ClockNameMatchesAssignment(name: String, fMHz: Double) extends Config((site, here, up) => {
case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
Seq((cName: String) => if (cName == name) Some(fMHz) else None)
})
class ClockNameContainsAssignment(name: String, fMHz: Double) extends Config((site, here, up) => {
case ClockFrequencyAssignersKey => up(ClockFrequencyAssignersKey, site) ++
Seq((cName: String) => if (cName.contains(name)) Some(fMHz) else None)
})
/**
* This sort of node can be used when it is a connectivity passthrough, but modifies
* the flow of parameters (which may result in changing the names of the underlying signals).
*/
class ClockGroupParameterModifier(
sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m },
sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { s => s })(
implicit p: Parameters, v: ValName) extends LazyModule {
val node = ClockGroupAdapterNode(sourceFn, sinkFn)
override def shouldBeInlined = true
lazy val module = new LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, _), (i, _)) =>
(o.member.data zip i.member.data).foreach { case (oD, iD) => oD := iD }
}
}
}
/**
* Pushes the ClockGroup's name into each member's name field as a prefix. This is
* intended to be used before a ClockGroupAggregator so that sources from
* different aggregated ClockGroups can be disambiguated by their names.
*/
object ClockGroupNamePrefixer {
def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode =
LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.zipWithIndex.map { case (m, idx) =>
m.copy(name = m.name match {
// This matches what the chisel would do if the names were not modified
case Some(clockName) => Some(s"${s.name}_${clockName}")
case None => Some(s"${s.name}_${idx}")
})
})})).node
}
/**
* [Word from on high is that Strings are in...]
* Overrides the take field of all clocks in a group, by attempting to apply a
* series of assignment functions:
* (name: String) => freq-in-MHz: Option[Double]
* to each sink. Later functions that return non-empty values take priority.
* The default if all functions return None.
*/
object ClockGroupFrequencySpecifier {
def apply(assigners: Seq[(String) => Option[Double]])(
implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = {
def lookupFrequencyForName(clock: ClockSinkParameters): ClockSinkParameters = clock.copy(take = clock.take match {
case Some(cp) =>
println(s"Clock ${clock.name.get}: using diplomatically specified frequency of ${cp.freqMHz}.")
Some(cp)
case None => {
val freqs = assigners.map { f => f(clock.name.get) }.flatten
if (freqs.size > 0) {
println(s"Clock ${clock.name.get}: using specified frequency of ${freqs.last}")
Some(ClockParameters(freqs.last))
} else {
None
}
}
})
LazyModule(new ClockGroupParameterModifier(sinkFn = { s => s.copy(members = s.members.map(lookupFrequencyForName)) })).node
}
}
File InterruptBus.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.subsystem
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings}
import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple}
import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain}
import freechips.rocketchip.interrupts.IntClockDomainCrossing
/** Collects interrupts from internal and external devices and feeds them into the PLIC */
class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain {
override def shouldBeInlined = true
val int_bus = LazyModule(new IntXbar) // Interrupt crossbar
private val int_in_xing = this.crossIn(int_bus.intnode)
private val int_out_xing = this.crossOut(int_bus.intnode)
def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) :=* IntNameNode(name)
def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) :*= int_out_xing(xing)
def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3))
def fromRational: IntInwardNode = from(None)(RationalCrossing())
def fromSync: IntInwardNode = int_bus.intnode
def toPLIC: IntOutwardNode = int_bus.intnode
}
/** Specifies the number of external interrupts */
case object NExtTopInterrupts extends Field[Int](0)
/** This trait adds externally driven interrupts to the system.
* However, it should not be used directly; instead one of the below
* synchronization wiring child traits should be used.
*/
abstract trait HasExtInterrupts { this: BaseSubsystem =>
private val device = new Device with DeviceInterrupts {
def describe(resources: ResourceBindings): Description = {
Description("soc/external-interrupts", describeInterrupts(resources))
}
}
val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
}
/** This trait should be used if the External Interrupts have NOT
* already been synchronized to the Periphery (PLIC) Clock.
*/
trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem =>
if (nExtInterrupts > 0) {
ibus { ibus.fromAsync := extInterrupts }
}
}
/** This trait can be used if the External Interrupts have already been synchronized
* to the Periphery (PLIC) Clock.
*/
trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem =>
if (nExtInterrupts > 0) {
ibus { ibus.fromSync := extInterrupts }
}
}
/** Common io name and methods for propagating or tying off the port bundle */
trait HasExtInterruptsBundle {
val interrupts: UInt
def tieOffInterrupts(dummy: Int = 1): Unit = {
interrupts := 0.U
}
}
/** This trait performs the translation from a UInt IO into Diplomatic Interrupts.
* The wiring must be done in the concrete LazyModuleImp.
*/
trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle {
val outer: HasExtInterrupts
val interrupts = IO(Input(UInt(outer.nExtInterrupts.W)))
outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
}
File GlobalNoC.scala:
package constellation.soc
import chisel3._
import chisel3.util._
import constellation.channel._
import constellation.noc._
import constellation.protocol._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.prci._
case class GlobalNoCParams(
nocParams: NoCParams = NoCParams()
)
trait CanAttachToGlobalNoC {
val protocolParams: ProtocolParams
val io_global: Data
}
case object GlobalNoCKey extends Field[GlobalNoCParams](GlobalNoCParams())
class GlobalNoCDomain(implicit p: Parameters) extends ClockSinkDomain()(p) {
InModuleBody {
val interfaces = getChildren.map(_.module).collect {
case a: CanAttachToGlobalNoC => a
}.toSeq
if (interfaces.size > 0) {
val noc = Module(new ProtocolNoC(ProtocolNoCParams(
p(GlobalNoCKey).nocParams,
interfaces.map(_.protocolParams)
)))
(interfaces zip noc.io.protocol).foreach { case (l,r) =>
l.io_global <> r
}
}
}
}
trait CanHaveGlobalNoC { this: BaseSubsystem =>
lazy val globalNoCDomain = LazyModule(new GlobalNoCDomain)
globalNoCDomain.clockNode := locateTLBusWrapper(SBUS).fixedClockNode
}
File BundleBridgeNexus.scala:
package org.chipsalliance.diplomacy.bundlebridge
import chisel3.{chiselTypeOf, ActualDirection, Data, Reg}
import chisel3.reflect.DataMirror
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp}
class BundleBridgeNexus[T <: Data](
inputFn: Seq[T] => T,
outputFn: (T, Int) => Seq[T],
default: Option[() => T] = None,
inputRequiresOutput: Boolean = false,
override val shouldBeInlined: Boolean = true
)(
implicit p: Parameters)
extends LazyModule {
val node = BundleBridgeNexusNode[T](default, inputRequiresOutput)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val defaultWireOpt = default.map(_())
val inputs: Seq[T] = node.in.map(_._1)
inputs.foreach { i =>
require(
DataMirror.checkTypeEquivalence(i, inputs.head),
s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}"
)
}
inputs.flatMap(getElements).foreach { elt =>
DataMirror.directionOf(elt) match {
case ActualDirection.Output => ()
case ActualDirection.Unspecified => ()
case _ => require(false, s"${node.context} can only be used with Output-directed Bundles")
}
}
val outputs: Seq[T] =
if (node.out.size > 0) {
val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get
outputFn(broadcast, node.out.size)
} else { Nil }
val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput")
override def desiredName = s"BundleBridgeNexus_$typeName"
node.out.map(_._1).foreach { o =>
require(
DataMirror.checkTypeEquivalence(o, outputs.head),
s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}"
)
}
require(
outputs.size == node.out.size,
s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}"
)
node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast }
}
}
object BundleBridgeNexus {
def safeRegNext[T <: Data](x: T): T = {
val reg = Reg(chiselTypeOf(x))
reg := x
reg
}
def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = {
require(seq.size == 1, "BundleBroadcast default requires one input")
if (registered) safeRegNext(seq.head) else seq.head
}
def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = {
val x = seq.reduce((a, b) => (a.asUInt | b.asUInt).asTypeOf(seq.head))
if (registered) safeRegNext(x) else x
}
def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) {
if (registered) safeRegNext(x) else x
}
def apply[T <: Data](
inputFn: Seq[T] => T = orReduction[T](false) _,
outputFn: (T, Int) => Seq[T] = fillN[T](false) _,
default: Option[() => T] = None,
inputRequiresOutput: Boolean = false,
shouldBeInlined: Boolean = true
)(
implicit p: Parameters
): BundleBridgeNexusNode[T] = {
val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined))
nexus.node
}
}
File BundleBridgeSink.scala:
package org.chipsalliance.diplomacy.bundlebridge
import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output}
import chisel3.reflect.DataMirror
import chisel3.reflect.DataMirror.internal.chiselTypeClone
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.nodes.SinkNode
case class BundleBridgeSink[T <: Data](
genOpt: Option[() => T] = None
)(
implicit valName: ValName)
extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) {
def bundle: T = in(0)._1
private def inferOutput = getElements(bundle).forall { elt =>
DataMirror.directionOf(elt) == ActualDirection.Unspecified
}
def makeIO(
)(
implicit valName: ValName
): T = {
val io: T = IO(
if (inferOutput) Output(chiselTypeOf(bundle))
else chiselTypeClone(bundle)
)
io.suggestName(valName.value)
io <> bundle
io
}
def makeIO(name: String): T = makeIO()(ValName(name))
}
object BundleBridgeSink {
def apply[T <: Data](
)(
implicit valName: ValName
): BundleBridgeSink[T] = {
BundleBridgeSink(None)
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
class IntXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o := cat }
}
}
class IntSyncXbar()(implicit p: Parameters) extends LazyModule
{
val intnode = new IntSyncNexusNode(
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq =>
IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
}.flatten)
})
{
override def circuitIdentity = outputs == 1 && inputs == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}"
val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
intnode.out.foreach { case (o, _) => o.sync := cat }
}
}
object IntXbar {
def apply()(implicit p: Parameters): IntNode = {
val xbar = LazyModule(new IntXbar)
xbar.intnode
}
}
object IntSyncXbar {
def apply()(implicit p: Parameters): IntSyncNode = {
val xbar = LazyModule(new IntSyncXbar)
xbar.intnode
}
}
| module DigitalTop( // @[DigitalTop.scala:47:7]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25]
output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25]
input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25]
input debug_clock, // @[Periphery.scala:125:19]
input debug_reset, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19]
input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19]
output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19]
input debug_systemjtag_reset, // @[Periphery.scala:125:19]
output debug_dmactive, // @[Periphery.scala:125:19]
input debug_dmactiveAck, // @[Periphery.scala:125:19]
input custom_boot, // @[CustomBootPin.scala:73:27]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24]
input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24]
output uart_0_txd, // @[BundleBridgeSink.scala:25:19]
input uart_0_rxd, // @[BundleBridgeSink.scala:25:19]
output clock_tap // @[CanHaveClockTap.scala:23:23]
);
wire clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21]
wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21]
wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21]
wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21]
wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28]
wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [6:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44]
wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44]
wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44]
wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44]
wire [10:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44]
wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44]
wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38]
wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38]
wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38]
wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38]
wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38]
wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_ser_busy; // @[PeripheryTLSerial.scala:116:38]
wire _serial_tl_domain_serial_tl_0_debug_des_busy; // @[PeripheryTLSerial.scala:116:38]
wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28]
wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28]
wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26]
wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26]
wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26]
wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26]
wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26]
wire [10:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26]
wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26]
wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26]
wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26]
wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26]
wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _plic_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28]
wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28]
wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28]
wire [10:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28]
wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28]
wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28]
wire _clint_domain_clock; // @[BusWrapper.scala:89:28]
wire _clint_domain_reset; // @[BusWrapper.scala:89:28]
wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39]
wire _tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode; // @[HasTiles.scala:163:38]
wire [1:0] _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size; // @[HasTiles.scala:163:38]
wire [6:0] _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38]
wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38]
wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38]
wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38]
wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [31:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [3:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [31:0] _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [5:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26]
wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26]
wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26]
wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26]
wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26]
wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26]
wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26]
wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26]
wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26]
wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26]
wire [10:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26]
wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26]
wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26]
wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26]
wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26]
wire [6:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26]
wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26]
wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26]
wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26]
wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26]
wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26]
wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26]
wire [5:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26]
wire [31:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26]
wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26]
wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26]
wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_2_reset; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26]
wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock; // @[DigitalTop.scala:47:7]
wire auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset; // @[DigitalTop.scala:47:7]
wire resetctrl_hartIsInReset_0_0 = resetctrl_hartIsInReset_0; // @[DigitalTop.scala:47:7]
wire debug_clock_0 = debug_clock; // @[DigitalTop.scala:47:7]
wire debug_reset_0 = debug_reset; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TCK_0 = debug_systemjtag_jtag_TCK; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TMS_0 = debug_systemjtag_jtag_TMS; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDI_0 = debug_systemjtag_jtag_TDI; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_reset_0 = debug_systemjtag_reset; // @[DigitalTop.scala:47:7]
wire debug_dmactiveAck_0 = debug_dmactiveAck; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_valid_0 = serial_tl_0_in_valid; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_in_bits_phit_0 = serial_tl_0_in_bits_phit; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_ready_0 = serial_tl_0_out_ready; // @[DigitalTop.scala:47:7]
wire serial_tl_0_clock_in_0 = serial_tl_0_clock_in; // @[DigitalTop.scala:47:7]
wire uart_0_rxd_0 = uart_0_rxd; // @[DigitalTop.scala:47:7]
wire [10:0] debug_systemjtag_mfr_id = 11'h0; // @[DigitalTop.scala:47:7]
wire [15:0] debug_systemjtag_part_number = 16'h0; // @[DigitalTop.scala:47:7]
wire [3:0] debug_systemjtag_version = 4'h0; // @[DigitalTop.scala:47:7]
wire [3:0] nexus_1_auto_in_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_in_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_group_0_itype = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_auto_out_priv = 4'h0; // @[BundleBridgeNexus.scala:20:9]
wire [3:0] nexus_1_nodeIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] nexus_1_nodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] nexus_1_nodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreNodesIn_group_0_itype = 4'h0; // @[MixedNode.scala:551:17]
wire [3:0] traceCoreNodesIn_priv = 4'h0; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_auto_in = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_auto_out = 32'h10000; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] broadcast_nodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] broadcast_nodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [31:0] bootROMResetVectorSourceNodeOut = 32'h10000; // @[MixedNode.scala:542:17]
wire [63:0] nexus_auto_in_time = 64'h0; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_auto_out_time = 64'h0; // @[BundleBridgeNexus.scala:20:9]
wire [63:0] nexus_nodeIn_time = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] nexus_nodeOut_time = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceNodesIn_time = 64'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_auto_in_insns_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_in_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_in_insns_0_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_in_insns_0_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_insn = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_auto_out_insns_0_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_nodeIn_insns_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeIn_insns_0_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeIn_insns_0_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_nodeOut_insns_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_nodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_nodeOut_insns_0_cause = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_nodeOut_insns_0_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_auto_in_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_in_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_group_0_iaddr = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_tval = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_auto_out_cause = 32'h0; // @[BundleBridgeNexus.scala:20:9]
wire [31:0] nexus_1_nodeIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] nexus_1_nodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] nexus_1_nodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreNodesIn_group_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceCoreNodesIn_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceNodesIn_insns_0_iaddr = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceNodesIn_insns_0_insn = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceNodesIn_insns_0_cause = 32'h0; // @[MixedNode.scala:551:17]
wire [31:0] traceNodesIn_insns_0_tval = 32'h0; // @[MixedNode.scala:551:17]
wire [2:0] nexus_auto_in_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_auto_out_insns_0_priv = 3'h0; // @[BundleBridgeNexus.scala:20:9]
wire [2:0] nexus_nodeIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] nexus_nodeOut_insns_0_priv = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] traceNodesIn_insns_0_priv = 3'h0; // @[MixedNode.scala:551:17]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire ibus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_auto_in_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_in_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_valid = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_exception = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_auto_out_insns_0_interrupt = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_nodeIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_nodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_nodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_nodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_auto_in_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_in_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_iretire = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_auto_out_group_0_ilastsize = 1'h0; // @[BundleBridgeNexus.scala:20:9]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_nodeIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire nexus_1_nodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockNamePrefixer_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockNamePrefixer__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire frequencySpecifier_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire frequencySpecifier_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire frequencySpecifier__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockTapNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockTapNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockTapNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire tileHaltSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileWFISinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire tileCeaseSinkNodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_iretire = 1'h0; // @[MixedNode.scala:551:17]
wire traceCoreNodesIn_group_0_ilastsize = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_valid = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_exception = 1'h0; // @[MixedNode.scala:551:17]
wire traceNodesIn_insns_0_interrupt = 1'h0; // @[MixedNode.scala:551:17]
wire ioNodeIn_txd; // @[MixedNode.scala:551:17]
wire ioNodeIn_rxd = uart_0_rxd_0; // @[MixedNode.scala:551:17]
wire auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
wire auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
wire debug_systemjtag_jtag_TDO_driven; // @[DigitalTop.scala:47:7]
wire debug_ndreset; // @[DigitalTop.scala:47:7]
wire debug_dmactive_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
wire [31:0] serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
wire serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
wire uart_0_txd_0; // @[DigitalTop.scala:47:7]
wire clockTapIn_clock; // @[MixedNode.scala:551:17]
wire ibus_clockNodeIn_clock = ibus_auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_in_0; // @[ClockDomain.scala:14:9]
wire ibus_clockNodeIn_reset = ibus_auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire ibus_auto_int_bus_anon_out_0; // @[ClockDomain.scala:14:9]
wire ibus_childClock; // @[LazyModuleImp.scala:155:31]
wire ibus_childReset; // @[LazyModuleImp.scala:158:31]
assign ibus_childClock = ibus_clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign ibus_childReset = ibus_clockNodeIn_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_clockTapNode_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_4_member_clockTapNode_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_cbus_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_3_member_cbus_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_clockTapNode_clock_tap_clock = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_3_member_clockTapNode_clock_tap_reset = clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_cbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_2_member_cbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_1_member_fbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeIn_member_pbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset; // @[MixedNode.scala:551:17]
wire clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeIn_member_sbus_0_clock = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock; // @[MixedNode.scala:551:17]
wire allClockGroupsNodeIn_member_sbus_0_reset = clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset; // @[MixedNode.scala:551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_member_sbus_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_1_member_pbus_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_2_member_fbus_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_clock = clockNamePrefixer_clockNamePrefixerIn_3_member_cbus_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_reset = clockNamePrefixer_clockNamePrefixerIn_3_member_cbus_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_clock = clockNamePrefixer_clockNamePrefixerIn_4_member_clockTapNode_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_reset = clockNamePrefixer_clockNamePrefixerIn_4_member_clockTapNode_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_clock = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_0_member_sbus_0_reset = clockNamePrefixer_clockNamePrefixerOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_1_member_pbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_2_member_fbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_clock = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_3_member_cbus_0_reset = clockNamePrefixer_x1_clockNamePrefixerOut_2_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_clock = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign clockNamePrefixer_auto_clock_name_prefixer_out_4_member_clockTapNode_clock_tap_reset = clockNamePrefixer_x1_clockNamePrefixerOut_3_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset = frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset; // @[MixedNode.scala:551:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
wire frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock; // @[ClockGroupNamePrefixer.scala:32:25]
wire frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset; // @[ClockGroupNamePrefixer.scala:32:25]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierIn_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_cbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_fbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_pbus_0_reset; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_clock; // @[MixedNode.scala:542:17]
assign frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset = frequencySpecifier_frequencySpecifierOut_member_allClocks_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock = clockTapNode_auto_in_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
wire x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset = clockTapNode_auto_in_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
wire clockTapNode_nodeOut_reset; // @[MixedNode.scala:542:17]
assign clockTapIn_clock = clockTapNode_auto_out_clock; // @[ClockGroup.scala:24:9]
wire clockTapIn_reset = clockTapNode_auto_out_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_clock = clockTapNode_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_out_reset = clockTapNode_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockTapNode_nodeOut_clock = clockTapNode_nodeIn_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockTapNode_nodeOut_reset = clockTapNode_nodeIn_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire allClockGroupsNodeOut_member_sbus_0_clock; // @[MixedNode.scala:542:17]
wire allClockGroupsNodeOut_member_sbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_member_pbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_1_member_fbus_0_reset; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_cbus_0_clock; // @[MixedNode.scala:542:17]
wire x1_allClockGroupsNodeOut_2_member_cbus_0_reset; // @[MixedNode.scala:542:17]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_clock; // @[ClockGroup.scala:24:9]
assign clockTapNode_auto_in_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_reset; // @[ClockGroup.scala:24:9]
assign allClockGroupsNodeOut_member_sbus_0_clock = allClockGroupsNodeIn_member_sbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign allClockGroupsNodeOut_member_sbus_0_reset = allClockGroupsNodeIn_member_sbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_clock = x1_allClockGroupsNodeIn_member_pbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_member_pbus_0_reset = x1_allClockGroupsNodeIn_member_pbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_clock = x1_allClockGroupsNodeIn_1_member_fbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_1_member_fbus_0_reset = x1_allClockGroupsNodeIn_1_member_fbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_cbus_0_clock = x1_allClockGroupsNodeIn_2_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_2_member_cbus_0_reset = x1_allClockGroupsNodeIn_2_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_clock = x1_allClockGroupsNodeIn_3_member_clockTapNode_clock_tap_clock; // @[MixedNode.scala:542:17, :551:17]
assign x1_allClockGroupsNodeOut_3_member_clockTapNode_clock_tap_reset = x1_allClockGroupsNodeIn_3_member_clockTapNode_clock_tap_reset; // @[MixedNode.scala:542:17, :551:17]
wire domainIn_clock; // @[MixedNode.scala:551:17]
wire domainIn_reset; // @[MixedNode.scala:551:17]
wire debugNodesIn_sync_0; // @[MixedNode.scala:551:17]
wire debugNodesOut_sync_0; // @[MixedNode.scala:542:17]
assign debugNodesOut_sync_0 = debugNodesIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
wire intXingIn_sync_0; // @[MixedNode.scala:551:17]
wire intXingOut_sync_0; // @[MixedNode.scala:542:17]
assign intXingOut_sync_0 = intXingIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign uart_0_txd_0 = ioNodeIn_txd; // @[MixedNode.scala:551:17]
reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40]
wire int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24]
wire int_rtc_tick; // @[Counter.scala:117:24]
assign int_rtc_tick_wrap_wrap = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24]
assign int_rtc_tick = int_rtc_tick_wrap_wrap; // @[Counter.scala:73:24, :117:24]
wire [10:0] _int_rtc_tick_wrap_value_T = {1'h0, int_rtc_tick_c_value} + 11'h1; // @[Counter.scala:61:40, :77:24]
wire [9:0] _int_rtc_tick_wrap_value_T_1 = _int_rtc_tick_wrap_value_T[9:0]; // @[Counter.scala:77:24]
always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28]
if (_clint_domain_reset) // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40]
else // @[BusWrapper.scala:89:28]
int_rtc_tick_c_value <= int_rtc_tick_wrap_wrap ? 10'h0 : _int_rtc_tick_wrap_value_T_1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}]
always @(posedge)
IntXbar_i1_o1 ibus_int_bus ( // @[InterruptBus.scala:19:27]
.auto_anon_in_0 (ibus_auto_int_bus_anon_in_0), // @[ClockDomain.scala:14:9]
.auto_anon_out_0 (ibus_auto_int_bus_anon_out_0)
); // @[InterruptBus.scala:19:27]
SystemBus sbus ( // @[SystemBus.scala:31:26]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_ready (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_ready),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready), // @[HasTiles.scala:163:38]
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_valid (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_valid),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_opcode (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_opcode),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_param (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_param),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_size (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_size),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_source (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_source),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_sink (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_sink),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_denied (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_denied),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_data (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_data),
.auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_corrupt),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready),
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_valid (_fbus_auto_bus_xing_out_a_valid), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_ready (_fbus_auto_bus_xing_out_d_ready), // @[FrontBus.scala:23:26]
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data),
.auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_ready (_cbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_valid (_cbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_cbus_bus_xing_out_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_fixedClockNode_anon_out_2_clock (_sbus_auto_fixedClockNode_anon_out_2_clock),
.auto_fixedClockNode_anon_out_2_reset (_sbus_auto_fixedClockNode_anon_out_2_reset),
.auto_fixedClockNode_anon_out_1_clock (_sbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_sbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (ibus_auto_clock_in_clock),
.auto_fixedClockNode_anon_out_0_reset (ibus_auto_clock_in_reset),
.auto_sbus_clock_groups_in_member_sbus_0_clock (allClockGroupsNodeOut_member_sbus_0_clock), // @[MixedNode.scala:542:17]
.auto_sbus_clock_groups_in_member_sbus_0_reset (allClockGroupsNodeOut_member_sbus_0_reset) // @[MixedNode.scala:542:17]
); // @[SystemBus.scala:31:26]
PeripheryBus_pbus pbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data),
.auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready),
.auto_coupler_to_device_named_uart_0_control_xing_out_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source), // @[UART.scala:270:44]
.auto_coupler_to_device_named_uart_0_control_xing_out_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data), // @[UART.scala:270:44]
.auto_fixedClockNode_anon_out_clock (_pbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_pbus_auto_fixedClockNode_anon_out_reset),
.auto_pbus_clock_groups_in_member_pbus_0_clock (x1_allClockGroupsNodeOut_member_pbus_0_clock), // @[MixedNode.scala:542:17]
.auto_pbus_clock_groups_in_member_pbus_0_reset (x1_allClockGroupsNodeOut_member_pbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_pbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bus_xing_in_d_valid (_pbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt)
); // @[PeripheryBus.scala:37:26]
FrontBus fbus ( // @[FrontBus.scala:23:26]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready), // @[PeripheryTLSerial.scala:116:38]
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data),
.auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt),
.auto_coupler_from_debug_sb_widget_anon_in_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready),
.auto_coupler_from_debug_sb_widget_anon_in_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready), // @[Periphery.scala:88:26]
.auto_coupler_from_debug_sb_widget_anon_in_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data),
.auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt),
.auto_fixedClockNode_anon_out_clock (_fbus_auto_fixedClockNode_anon_out_clock),
.auto_fixedClockNode_anon_out_reset (_fbus_auto_fixedClockNode_anon_out_reset),
.auto_fbus_clock_groups_in_member_fbus_0_clock (x1_allClockGroupsNodeOut_1_member_fbus_0_clock), // @[MixedNode.scala:542:17]
.auto_fbus_clock_groups_in_member_fbus_0_reset (x1_allClockGroupsNodeOut_1_member_fbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_out_a_ready (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_a_valid (_fbus_auto_bus_xing_out_a_valid),
.auto_bus_xing_out_a_bits_opcode (_fbus_auto_bus_xing_out_a_bits_opcode),
.auto_bus_xing_out_a_bits_param (_fbus_auto_bus_xing_out_a_bits_param),
.auto_bus_xing_out_a_bits_size (_fbus_auto_bus_xing_out_a_bits_size),
.auto_bus_xing_out_a_bits_source (_fbus_auto_bus_xing_out_a_bits_source),
.auto_bus_xing_out_a_bits_address (_fbus_auto_bus_xing_out_a_bits_address),
.auto_bus_xing_out_a_bits_mask (_fbus_auto_bus_xing_out_a_bits_mask),
.auto_bus_xing_out_a_bits_data (_fbus_auto_bus_xing_out_a_bits_data),
.auto_bus_xing_out_a_bits_corrupt (_fbus_auto_bus_xing_out_a_bits_corrupt),
.auto_bus_xing_out_d_ready (_fbus_auto_bus_xing_out_d_ready),
.auto_bus_xing_out_d_valid (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_opcode (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_param (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_size (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_source (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_sink (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_denied (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_data (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt) // @[SystemBus.scala:31:26]
); // @[FrontBus.scala:23:26]
PeripheryBus_cbus cbus ( // @[PeripheryBus.scala:37:26]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data),
.auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready),
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_ready (_bootrom_domain_auto_bootrom_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready),
.auto_coupler_to_bootrom_fragmenter_anon_out_d_valid (_bootrom_domain_auto_bootrom_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_ready (_tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready),
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_valid (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_opcode (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_param (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_size (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_source (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_sink (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_denied (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_data (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data), // @[HasTiles.scala:163:38]
.auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_bits_corrupt (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt), // @[HasTiles.scala:163:38]
.auto_coupler_to_debug_fragmenter_anon_out_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_debug_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready),
.auto_coupler_to_debug_fragmenter_anon_out_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source), // @[Periphery.scala:88:26]
.auto_coupler_to_debug_fragmenter_anon_out_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data), // @[Periphery.scala:88:26]
.auto_coupler_to_plic_fragmenter_anon_out_a_ready (_plic_domain_auto_plic_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_plic_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready),
.auto_coupler_to_plic_fragmenter_anon_out_d_valid (_plic_domain_auto_plic_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_size (_plic_domain_auto_plic_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_source (_plic_domain_auto_plic_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_plic_fragmenter_anon_out_d_bits_data (_plic_domain_auto_plic_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_ready (_clint_domain_auto_clint_in_a_ready), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data),
.auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt),
.auto_coupler_to_clint_fragmenter_anon_out_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready),
.auto_coupler_to_clint_fragmenter_anon_out_d_valid (_clint_domain_auto_clint_in_d_valid), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_size (_clint_domain_auto_clint_in_d_bits_size), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_source (_clint_domain_auto_clint_in_d_bits_source), // @[BusWrapper.scala:89:28]
.auto_coupler_to_clint_fragmenter_anon_out_d_bits_data (_clint_domain_auto_clint_in_d_bits_data), // @[BusWrapper.scala:89:28]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready (_pbus_auto_bus_xing_in_a_ready), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data),
.auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready (_cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready),
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid (_pbus_auto_bus_xing_in_d_valid), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode (_pbus_auto_bus_xing_in_d_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param (_pbus_auto_bus_xing_in_d_bits_param), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size (_pbus_auto_bus_xing_in_d_bits_size), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source (_pbus_auto_bus_xing_in_d_bits_source), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink (_pbus_auto_bus_xing_in_d_bits_sink), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied (_pbus_auto_bus_xing_in_d_bits_denied), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data (_pbus_auto_bus_xing_in_d_bits_data), // @[PeripheryBus.scala:37:26]
.auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt (_pbus_auto_bus_xing_in_d_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_fixedClockNode_anon_out_5_clock (auto_cbus_fixedClockNode_anon_out_clock_0),
.auto_fixedClockNode_anon_out_5_reset (auto_cbus_fixedClockNode_anon_out_reset_0),
.auto_fixedClockNode_anon_out_4_clock (_cbus_auto_fixedClockNode_anon_out_4_clock),
.auto_fixedClockNode_anon_out_4_reset (_cbus_auto_fixedClockNode_anon_out_4_reset),
.auto_fixedClockNode_anon_out_3_clock (_cbus_auto_fixedClockNode_anon_out_3_clock),
.auto_fixedClockNode_anon_out_3_reset (_cbus_auto_fixedClockNode_anon_out_3_reset),
.auto_fixedClockNode_anon_out_2_clock (domainIn_clock),
.auto_fixedClockNode_anon_out_2_reset (domainIn_reset),
.auto_fixedClockNode_anon_out_1_clock (_cbus_auto_fixedClockNode_anon_out_1_clock),
.auto_fixedClockNode_anon_out_1_reset (_cbus_auto_fixedClockNode_anon_out_1_reset),
.auto_fixedClockNode_anon_out_0_clock (_cbus_auto_fixedClockNode_anon_out_0_clock),
.auto_fixedClockNode_anon_out_0_reset (_cbus_auto_fixedClockNode_anon_out_0_reset),
.auto_cbus_clock_groups_in_member_cbus_0_clock (x1_allClockGroupsNodeOut_2_member_cbus_0_clock), // @[MixedNode.scala:542:17]
.auto_cbus_clock_groups_in_member_cbus_0_reset (x1_allClockGroupsNodeOut_2_member_cbus_0_reset), // @[MixedNode.scala:542:17]
.auto_bus_xing_in_a_ready (_cbus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_opcode (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_param (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_size (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_source (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_address (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_mask (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_data (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_a_bits_corrupt (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_ready (_sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready), // @[SystemBus.scala:31:26]
.auto_bus_xing_in_d_valid (_cbus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode (_cbus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param (_cbus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size (_cbus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source (_cbus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink (_cbus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied (_cbus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data (_cbus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt (_cbus_auto_bus_xing_in_d_bits_corrupt),
.custom_boot (custom_boot)
); // @[PeripheryBus.scala:37:26]
TilePRCIDomain tile_prci_domain ( // @[HasTiles.scala:163:38]
.auto_intsink_in_sync_0 (debugNodesOut_sync_0), // @[MixedNode.scala:542:17]
.auto_element_reset_domain_sodor_tile_hartid_in (_tileHartIdNexusNode_auto_out), // @[HasTiles.scala:75:39]
.auto_int_in_clock_xing_in_1_sync_0 (_plic_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0), // @[BusWrapper.scala:89:28]
.auto_int_in_clock_xing_in_0_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1), // @[BusWrapper.scala:89:28]
.auto_tl_slave_clock_xing_in_a_ready (_tile_prci_domain_auto_tl_slave_clock_xing_in_a_ready),
.auto_tl_slave_clock_xing_in_a_valid (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_opcode (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_param (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_size (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_source (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_address (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_mask (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_data (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_a_bits_corrupt (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_d_ready (_cbus_auto_coupler_to_sodor_tile_tl_slave_clock_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_tl_slave_clock_xing_in_d_valid (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_valid),
.auto_tl_slave_clock_xing_in_d_bits_opcode (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_opcode),
.auto_tl_slave_clock_xing_in_d_bits_param (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_param),
.auto_tl_slave_clock_xing_in_d_bits_size (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_size),
.auto_tl_slave_clock_xing_in_d_bits_source (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_source),
.auto_tl_slave_clock_xing_in_d_bits_sink (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_sink),
.auto_tl_slave_clock_xing_in_d_bits_denied (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_denied),
.auto_tl_slave_clock_xing_in_d_bits_data (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_data),
.auto_tl_slave_clock_xing_in_d_bits_corrupt (_tile_prci_domain_auto_tl_slave_clock_xing_in_d_bits_corrupt),
.auto_tl_master_clock_xing_out_a_ready (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_a_ready), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_a_valid (_tile_prci_domain_auto_tl_master_clock_xing_out_a_valid),
.auto_tl_master_clock_xing_out_a_bits_opcode (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode),
.auto_tl_master_clock_xing_out_a_bits_param (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param),
.auto_tl_master_clock_xing_out_a_bits_size (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size),
.auto_tl_master_clock_xing_out_a_bits_source (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source),
.auto_tl_master_clock_xing_out_a_bits_address (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address),
.auto_tl_master_clock_xing_out_a_bits_mask (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask),
.auto_tl_master_clock_xing_out_a_bits_data (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data),
.auto_tl_master_clock_xing_out_a_bits_corrupt (_tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt),
.auto_tl_master_clock_xing_out_d_ready (_tile_prci_domain_auto_tl_master_clock_xing_out_d_ready),
.auto_tl_master_clock_xing_out_d_valid (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_valid), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_opcode (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_opcode), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_param (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_param), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_size (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_size), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_source (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_source), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_sink (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_sink), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_denied (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_denied), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_data (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_data), // @[SystemBus.scala:31:26]
.auto_tl_master_clock_xing_out_d_bits_corrupt (_sbus_auto_coupler_from_sodor_tile_tl_master_clock_xing_in_d_bits_corrupt), // @[SystemBus.scala:31:26]
.auto_tap_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_1_clock), // @[SystemBus.scala:31:26]
.auto_tap_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_1_reset) // @[SystemBus.scala:31:26]
); // @[HasTiles.scala:163:38]
IntXbar_i1_o1_1 xbar (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_2 xbar_1 (); // @[Xbar.scala:52:26]
IntXbar_i1_o1_3 xbar_2 (); // @[Xbar.scala:52:26]
BundleBridgeNexus_UInt1_1 tileHartIdNexusNode ( // @[HasTiles.scala:75:39]
.auto_out (_tileHartIdNexusNode_auto_out)
); // @[HasTiles.scala:75:39]
CLINTClockSinkDomain clint_domain ( // @[BusWrapper.scala:89:28]
.auto_clint_in_a_ready (_clint_domain_auto_clint_in_a_ready),
.auto_clint_in_a_valid (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_opcode (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_param (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_size (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_source (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_address (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_mask (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_data (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_clint_in_a_bits_corrupt (_cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_ready (_cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_clint_in_d_valid (_clint_domain_auto_clint_in_d_valid),
.auto_clint_in_d_bits_opcode (_clint_domain_auto_clint_in_d_bits_opcode),
.auto_clint_in_d_bits_size (_clint_domain_auto_clint_in_d_bits_size),
.auto_clint_in_d_bits_source (_clint_domain_auto_clint_in_d_bits_source),
.auto_clint_in_d_bits_data (_clint_domain_auto_clint_in_d_bits_data),
.auto_int_in_clock_xing_out_sync_0 (_clint_domain_auto_int_in_clock_xing_out_sync_0),
.auto_int_in_clock_xing_out_sync_1 (_clint_domain_auto_int_in_clock_xing_out_sync_1),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_0_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_0_reset), // @[PeripheryBus.scala:37:26]
.tick (int_rtc_tick), // @[Counter.scala:117:24]
.clock (_clint_domain_clock),
.reset (_clint_domain_reset)
); // @[BusWrapper.scala:89:28]
PLICClockSinkDomain plic_domain ( // @[BusWrapper.scala:89:28]
.auto_plic_int_in_0 (ibus_auto_int_bus_anon_out_0), // @[ClockDomain.scala:14:9]
.auto_plic_in_a_ready (_plic_domain_auto_plic_in_a_ready),
.auto_plic_in_a_valid (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_opcode (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_param (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_size (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_source (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_address (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_mask (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_data (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_plic_in_a_bits_corrupt (_cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_ready (_cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_plic_in_d_valid (_plic_domain_auto_plic_in_d_valid),
.auto_plic_in_d_bits_opcode (_plic_domain_auto_plic_in_d_bits_opcode),
.auto_plic_in_d_bits_size (_plic_domain_auto_plic_in_d_bits_size),
.auto_plic_in_d_bits_source (_plic_domain_auto_plic_in_d_bits_source),
.auto_plic_in_d_bits_data (_plic_domain_auto_plic_in_d_bits_data),
.auto_int_in_clock_xing_out_sync_0 (_plic_domain_auto_int_in_clock_xing_out_sync_0),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_1_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_1_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
TLDebugModule tlDM ( // @[Periphery.scala:88:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_ready (_fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_a_valid (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address),
.auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data),
.auto_dmInner_dmInner_sb2tlOpt_out_d_ready (_tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready),
.auto_dmInner_dmInner_sb2tlOpt_out_d_valid (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_opcode (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_param (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_size (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_sink (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_denied (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_data (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_sb2tlOpt_out_d_bits_corrupt (_fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_dmInner_dmInner_tl_in_a_ready (_tlDM_auto_dmInner_dmInner_tl_in_a_ready),
.auto_dmInner_dmInner_tl_in_a_valid (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_opcode (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_param (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_size (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_source (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_address (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_mask (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_data (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_a_bits_corrupt (_cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_ready (_cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_dmInner_dmInner_tl_in_d_valid (_tlDM_auto_dmInner_dmInner_tl_in_d_valid),
.auto_dmInner_dmInner_tl_in_d_bits_opcode (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode),
.auto_dmInner_dmInner_tl_in_d_bits_size (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_size),
.auto_dmInner_dmInner_tl_in_d_bits_source (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_source),
.auto_dmInner_dmInner_tl_in_d_bits_data (_tlDM_auto_dmInner_dmInner_tl_in_d_bits_data),
.auto_dmOuter_int_out_sync_0 (debugNodesIn_sync_0),
.io_debug_clock (debug_clock_0), // @[DigitalTop.scala:47:7]
.io_debug_reset (debug_reset_0), // @[DigitalTop.scala:47:7]
.io_tl_clock (domainIn_clock), // @[MixedNode.scala:551:17]
.io_tl_reset (domainIn_reset), // @[MixedNode.scala:551:17]
.io_ctrl_ndreset (debug_ndreset),
.io_ctrl_dmactive (debug_dmactive_0),
.io_ctrl_dmactiveAck (debug_dmactiveAck_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready),
.io_dmi_dmi_req_valid (_dtm_io_dmi_req_valid), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_data (_dtm_io_dmi_req_bits_data), // @[Periphery.scala:166:21]
.io_dmi_dmi_req_bits_op (_dtm_io_dmi_req_bits_op), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_ready (_dtm_io_dmi_resp_ready), // @[Periphery.scala:166:21]
.io_dmi_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid),
.io_dmi_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data),
.io_dmi_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp),
.io_dmi_dmiClock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_dmi_dmiReset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_hartIsInReset_0 (resetctrl_hartIsInReset_0_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:88:26]
DebugCustomXbar debugCustomXbarOpt (); // @[Periphery.scala:80:75]
BootROMClockSinkDomain bootrom_domain ( // @[BusWrapper.scala:89:28]
.auto_bootrom_in_a_ready (_bootrom_domain_auto_bootrom_in_a_ready),
.auto_bootrom_in_a_valid (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_opcode (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_param (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_size (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_source (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_address (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_mask (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_data (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_a_bits_corrupt (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_ready (_cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_bootrom_in_d_valid (_bootrom_domain_auto_bootrom_in_d_valid),
.auto_bootrom_in_d_bits_size (_bootrom_domain_auto_bootrom_in_d_bits_size),
.auto_bootrom_in_d_bits_source (_bootrom_domain_auto_bootrom_in_d_bits_source),
.auto_bootrom_in_d_bits_data (_bootrom_domain_auto_bootrom_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_3_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_3_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
SerialTL0ClockSinkDomain serial_tl_domain ( // @[PeripheryTLSerial.scala:116:38]
.auto_serdesser_client_out_a_ready (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_a_valid (_serial_tl_domain_auto_serdesser_client_out_a_valid),
.auto_serdesser_client_out_a_bits_opcode (_serial_tl_domain_auto_serdesser_client_out_a_bits_opcode),
.auto_serdesser_client_out_a_bits_param (_serial_tl_domain_auto_serdesser_client_out_a_bits_param),
.auto_serdesser_client_out_a_bits_size (_serial_tl_domain_auto_serdesser_client_out_a_bits_size),
.auto_serdesser_client_out_a_bits_source (_serial_tl_domain_auto_serdesser_client_out_a_bits_source),
.auto_serdesser_client_out_a_bits_address (_serial_tl_domain_auto_serdesser_client_out_a_bits_address),
.auto_serdesser_client_out_a_bits_mask (_serial_tl_domain_auto_serdesser_client_out_a_bits_mask),
.auto_serdesser_client_out_a_bits_data (_serial_tl_domain_auto_serdesser_client_out_a_bits_data),
.auto_serdesser_client_out_a_bits_corrupt (_serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt),
.auto_serdesser_client_out_d_ready (_serial_tl_domain_auto_serdesser_client_out_d_ready),
.auto_serdesser_client_out_d_valid (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_opcode (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_param (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_size (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_source (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_sink (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_denied (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_data (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data), // @[FrontBus.scala:23:26]
.auto_serdesser_client_out_d_bits_corrupt (_fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt), // @[FrontBus.scala:23:26]
.auto_clock_in_clock (_fbus_auto_fixedClockNode_anon_out_clock), // @[FrontBus.scala:23:26]
.auto_clock_in_reset (_fbus_auto_fixedClockNode_anon_out_reset), // @[FrontBus.scala:23:26]
.serial_tl_0_in_ready (serial_tl_0_in_ready_0),
.serial_tl_0_in_valid (serial_tl_0_in_valid_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_in_bits_phit (serial_tl_0_in_bits_phit_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_ready (serial_tl_0_out_ready_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_out_valid (serial_tl_0_out_valid_0),
.serial_tl_0_out_bits_phit (serial_tl_0_out_bits_phit_0),
.serial_tl_0_clock_in (serial_tl_0_clock_in_0), // @[DigitalTop.scala:47:7]
.serial_tl_0_debug_ser_busy (_serial_tl_domain_serial_tl_0_debug_ser_busy),
.serial_tl_0_debug_des_busy (_serial_tl_domain_serial_tl_0_debug_des_busy)
); // @[PeripheryTLSerial.scala:116:38]
TLUARTClockSinkDomain uartClockDomainWrapper ( // @[UART.scala:270:44]
.auto_uart_0_int_xing_out_sync_0 (intXingIn_sync_0),
.auto_uart_0_control_xing_in_a_ready (_uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready),
.auto_uart_0_control_xing_in_a_valid (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_opcode (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_param (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_size (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_source (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_address (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_mask (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_data (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_a_bits_corrupt (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_ready (_pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_uart_0_control_xing_in_d_valid (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid),
.auto_uart_0_control_xing_in_d_bits_opcode (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode),
.auto_uart_0_control_xing_in_d_bits_size (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size),
.auto_uart_0_control_xing_in_d_bits_source (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source),
.auto_uart_0_control_xing_in_d_bits_data (_uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data),
.auto_uart_0_io_out_txd (ioNodeIn_txd),
.auto_uart_0_io_out_rxd (ioNodeIn_rxd), // @[MixedNode.scala:551:17]
.auto_clock_in_clock (_pbus_auto_fixedClockNode_anon_out_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_pbus_auto_fixedClockNode_anon_out_reset) // @[PeripheryBus.scala:37:26]
); // @[UART.scala:270:44]
IntSyncSyncCrossingSink_n1x1_4 intsink ( // @[Crossing.scala:109:29]
.auto_in_sync_0 (intXingOut_sync_0), // @[MixedNode.scala:542:17]
.auto_out_0 (ibus_auto_int_bus_anon_in_0)
); // @[Crossing.scala:109:29]
ChipyardPRCICtrlClockSinkDomain chipyard_prcictrl_domain ( // @[BusWrapper.scala:89:28]
.auto_reset_setter_clock_in_member_allClocks_uncore_clock (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[DigitalTop.scala:47:7]
.auto_reset_setter_clock_in_member_allClocks_uncore_reset (auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[DigitalTop.scala:47:7]
.auto_resetSynchronizer_out_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock),
.auto_resetSynchronizer_out_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset),
.auto_xbar_anon_in_a_ready (_chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready),
.auto_xbar_anon_in_a_valid (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_opcode (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_param (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_size (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_source (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_address (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_mask (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_data (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_a_bits_corrupt (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_ready (_cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready), // @[PeripheryBus.scala:37:26]
.auto_xbar_anon_in_d_valid (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid),
.auto_xbar_anon_in_d_bits_opcode (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode),
.auto_xbar_anon_in_d_bits_size (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size),
.auto_xbar_anon_in_d_bits_source (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source),
.auto_xbar_anon_in_d_bits_data (_chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data),
.auto_clock_in_clock (_cbus_auto_fixedClockNode_anon_out_4_clock), // @[PeripheryBus.scala:37:26]
.auto_clock_in_reset (_cbus_auto_fixedClockNode_anon_out_4_reset) // @[PeripheryBus.scala:37:26]
); // @[BusWrapper.scala:89:28]
ClockGroupAggregator_allClocks aggregator ( // @[HasChipyardPRCI.scala:51:30]
.auto_in_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_clockTapNode_clock_tap_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_cbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_fbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_pbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_clock), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_in_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_out_member_allClocks_sbus_0_reset), // @[ClockGroupNamePrefixer.scala:32:25]
.auto_out_4_member_clockTapNode_clockTapNode_clock_tap_clock (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_clock),
.auto_out_4_member_clockTapNode_clockTapNode_clock_tap_reset (clockNamePrefixer_auto_clock_name_prefixer_in_4_member_clockTapNode_clockTapNode_clock_tap_reset),
.auto_out_3_member_cbus_cbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_clock),
.auto_out_3_member_cbus_cbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_3_member_cbus_cbus_0_reset),
.auto_out_2_member_fbus_fbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_clock),
.auto_out_2_member_fbus_fbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_2_member_fbus_fbus_0_reset),
.auto_out_1_member_pbus_pbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_clock),
.auto_out_1_member_pbus_pbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_1_member_pbus_pbus_0_reset),
.auto_out_0_member_sbus_sbus_0_clock (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_clock),
.auto_out_0_member_sbus_sbus_0_reset (clockNamePrefixer_auto_clock_name_prefixer_in_0_member_sbus_sbus_0_reset)
); // @[HasChipyardPRCI.scala:51:30]
ClockGroupCombiner clockGroupCombiner ( // @[ClockGroupCombiner.scala:19:15]
.auto_clock_group_combiner_in_member_allClocks_uncore_clock (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_in_member_allClocks_uncore_reset (_chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset), // @[BusWrapper.scala:89:28]
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_clock),
.auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_clockTapNode_clock_tap_reset),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_cbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_cbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_fbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_fbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_pbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_pbus_0_reset),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_clock (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_clock),
.auto_clock_group_combiner_out_member_allClocks_sbus_0_reset (frequencySpecifier_auto_frequency_specifier_in_member_allClocks_sbus_0_reset)
); // @[ClockGroupCombiner.scala:19:15]
ClockSinkDomain_1 globalNoCDomain ( // @[GlobalNoC.scala:45:40]
.auto_clock_in_clock (_sbus_auto_fixedClockNode_anon_out_2_clock), // @[SystemBus.scala:31:26]
.auto_clock_in_reset (_sbus_auto_fixedClockNode_anon_out_2_reset) // @[SystemBus.scala:31:26]
); // @[GlobalNoC.scala:45:40]
BundleBridgeNexus_NoOutput_6 reRoCCManagerIdNexusNode (); // @[Integration.scala:34:44]
DebugTransportModuleJTAG dtm ( // @[Periphery.scala:166:21]
.io_jtag_clock (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_reset (debug_systemjtag_reset_0), // @[DigitalTop.scala:47:7]
.io_dmi_req_ready (_tlDM_io_dmi_dmi_req_ready), // @[Periphery.scala:88:26]
.io_dmi_req_valid (_dtm_io_dmi_req_valid),
.io_dmi_req_bits_addr (_dtm_io_dmi_req_bits_addr),
.io_dmi_req_bits_data (_dtm_io_dmi_req_bits_data),
.io_dmi_req_bits_op (_dtm_io_dmi_req_bits_op),
.io_dmi_resp_ready (_dtm_io_dmi_resp_ready),
.io_dmi_resp_valid (_tlDM_io_dmi_dmi_resp_valid), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_data (_tlDM_io_dmi_dmi_resp_bits_data), // @[Periphery.scala:88:26]
.io_dmi_resp_bits_resp (_tlDM_io_dmi_dmi_resp_bits_resp), // @[Periphery.scala:88:26]
.io_jtag_TCK (debug_systemjtag_jtag_TCK_0), // @[DigitalTop.scala:47:7]
.io_jtag_TMS (debug_systemjtag_jtag_TMS_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDI (debug_systemjtag_jtag_TDI_0), // @[DigitalTop.scala:47:7]
.io_jtag_TDO_data (debug_systemjtag_jtag_TDO_data_0),
.io_jtag_TDO_driven (debug_systemjtag_jtag_TDO_driven),
.rf_reset (debug_systemjtag_reset_0) // @[DigitalTop.scala:47:7]
); // @[Periphery.scala:166:21]
assign auto_cbus_fixedClockNode_anon_out_clock = auto_cbus_fixedClockNode_anon_out_clock_0; // @[DigitalTop.scala:47:7]
assign auto_cbus_fixedClockNode_anon_out_reset = auto_cbus_fixedClockNode_anon_out_reset_0; // @[DigitalTop.scala:47:7]
assign debug_systemjtag_jtag_TDO_data = debug_systemjtag_jtag_TDO_data_0; // @[DigitalTop.scala:47:7]
assign debug_dmactive = debug_dmactive_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_in_ready = serial_tl_0_in_ready_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_valid = serial_tl_0_out_valid_0; // @[DigitalTop.scala:47:7]
assign serial_tl_0_out_bits_phit = serial_tl_0_out_bits_phit_0; // @[DigitalTop.scala:47:7]
assign uart_0_txd = uart_0_txd_0; // @[DigitalTop.scala:47:7]
assign clock_tap = clockTapIn_clock; // @[MixedNode.scala:551:17]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File Util.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.{Printable}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
object CompressAccelLogger {
def logInfo(format: String, args: Bits*)(implicit p: Parameters) {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
printf("cy: %d, ", loginfo_cycles)
printf(Printable.pack(format, args:_*))
}
def logCritical(format: String, args: Bits*)(implicit p: Parameters) {
val loginfo_cycles = RegInit(0.U(64.W))
loginfo_cycles := loginfo_cycles + 1.U
if (p(CompressAccelPrintfEnable)) {
printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles))
printf(midas.targetutils.SynthesizePrintf(format, args:_*))
} else {
printf("cy: %d, ", loginfo_cycles)
printf(Printable.pack(format, args:_*))
}
}
def logWaveStyle(format: String, args: Bits*)(implicit p: Parameters) {
}
}
object CompressAccelParams {
}
File ZstdCompressorCommandRouter.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
import chisel3.{Printable}
import freechips.rocketchip.tile._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.rocket.{TLBConfig}
import freechips.rocketchip.util.DecoupledHelper
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import CompressorConsts._
class ZstdBuffInfo extends Bundle {
val lit = Decoupled(new StreamInfo)
val seq = Decoupled(new StreamInfo)
}
class ZstdCompressorCommandRouterIO()(implicit val p: Parameters)
extends Bundle {
val rocc_in = Flipped(Decoupled(new RoCCCommand))
val rocc_out = Decoupled(new RoCCResponse)
val dmem_status_out = Valid(new RoCCCommand)
val sfence_out = Output(Bool())
// val no_memops_inflight = Input(Bool())
// val finished_src_info = Input(UInt(64.W))
val ALGORITHM = Output(UInt(1.W))
val src_info = Decoupled(new StreamInfo)
val dst_info = Decoupled(new DstInfo)
val buff_info = new ZstdBuffInfo
val clevel_info = Decoupled(UInt(5.W))
val SNAPPY_MAX_OFFSET_ALLOWED = Output(UInt(64.W))
val SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 = Output(UInt(5.W))
val LATENCY_INJECTION_CYCLES = Output(UInt(64.W))
val HAS_INTERMEDIATE_CACHE = Output(Bool())
val zstd_finished_cnt = Flipped(Decoupled(UInt(64.W)))
val snappy_finished_cnt = Flipped(Decoupled(UInt(64.W)))
}
class ZstdCompressorCommandRouter(implicit p: Parameters)
extends ZstdCompressorModule {
val io = IO(new ZstdCompressorCommandRouterIO)
val FUNCT_SFENCE = 0.U
val FUNCT_ZSTD_SRC_INFO = 1.U
val FUNCT_ZSTD_LIT_BUFF_INFO = 2.U
val FUNCT_ZSTD_SEQ_BUFF_INFO = 3.U
val FUNCT_ZSTD_DST_INFO = 4.U
val FUNCT_ZSTD_COMPRESSION_LEVEL = 5.U
val FUNCT_SNPY_SRC_INFO = 6.U
val FUNCT_SNPY_DST_INFO = 7.U
val FUNCT_SNPY_MAX_OFFSET_ALLOWED = 8.U
val FUNCT_SNPY_RUNTIME_HT_NUM_ENTRIES_LOG2 = 9.U
val FUNCT_LATENCY_INJECTION_INFO = 10.U
val FUNCT_CHECK_COMPLETION = 11.U
val snappy_dispatched_src_info = RegInit(0.U(64.W))
val zstd_dispatched_src_info = RegInit(0.U(64.W))
val cur_funct = io.rocc_in.bits.inst.funct
val cur_rs1 = io.rocc_in.bits.rs1
val cur_rs2 = io.rocc_in.bits.rs2
val sfence_fire = DecoupledHelper(io.rocc_in.valid,
cur_funct === FUNCT_SFENCE)
io.sfence_out := sfence_fire.fire
io.dmem_status_out.bits <> io.rocc_in.bits
io.dmem_status_out.valid <> io.rocc_in.fire
when (io.rocc_in.fire) {
CompressAccelLogger.logInfo("rocc_in_data, opcode: %d, rs1: 0x%x, rs2: 0x%x\n", cur_funct, cur_rs1, cur_rs2)
}
val ALGORITHM = RegInit(ZSTD.U(1.W))
io.ALGORITHM := ALGORITHM
val prev_algo = RegNext(ALGORITHM)
when (ALGORITHM =/= prev_algo) {
CompressAccelLogger.logInfo("ALGORITHM CHANGED FROM %d to %d\n", prev_algo, ALGORITHM)
}
val SNAPPY_MAX_OFFSET_ALLOWED = RegInit(((64 * 1024) - 64).U(64.W))
io.SNAPPY_MAX_OFFSET_ALLOWED := SNAPPY_MAX_OFFSET_ALLOWED
val max_offset_allowed_fire = DecoupledHelper(
io.rocc_in.valid,
cur_funct === FUNCT_SNPY_MAX_OFFSET_ALLOWED
)
when (max_offset_allowed_fire.fire) {
SNAPPY_MAX_OFFSET_ALLOWED := cur_rs1
}
val SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 = RegInit(14.U(5.W))
io.SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 := SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2
val runtime_ht_num_entries_fire = DecoupledHelper(
io.rocc_in.valid,
cur_funct === FUNCT_SNPY_RUNTIME_HT_NUM_ENTRIES_LOG2
)
when (runtime_ht_num_entries_fire.fire) {
SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2 := io.rocc_in.bits.rs1
}
when (io.rocc_in.fire && (cur_funct === FUNCT_ZSTD_SRC_INFO)) {
val nxt_dispatched_src_info = zstd_dispatched_src_info + 1.U
zstd_dispatched_src_info := nxt_dispatched_src_info
CompressAccelLogger.logInfo("CommandRouter, zstd dispatched src cnt: %d\n", nxt_dispatched_src_info)
}
when (io.rocc_in.fire && (cur_funct === FUNCT_SNPY_SRC_INFO)) {
val nxt_dispatched_src_info = snappy_dispatched_src_info + 1.U
snappy_dispatched_src_info := nxt_dispatched_src_info
CompressAccelLogger.logInfo("CommandRouter, snappy dispatched src cnt: %d\n", nxt_dispatched_src_info)
}
val src_info_queue = Module(new Queue(new StreamInfo, queDepth))
val src_info_fire = DecoupledHelper(io.rocc_in.valid,
src_info_queue.io.enq.ready,
(cur_funct === FUNCT_ZSTD_SRC_INFO) || (cur_funct === FUNCT_SNPY_SRC_INFO))
src_info_queue.io.enq.bits.ip := cur_rs1
src_info_queue.io.enq.bits.isize := cur_rs2
src_info_queue.io.enq.valid := src_info_fire.fire(src_info_queue.io.enq.ready)
io.src_info <> src_info_queue.io.deq
when (src_info_fire.fire) {
when (cur_funct === FUNCT_ZSTD_SRC_INFO) {
ALGORITHM := ZSTD.U
} .otherwise {
ALGORITHM := Snappy.U
}
}
when (io.src_info.fire) {
CompressAccelLogger.logInfo("CommandRouter, io.src_info.fire!\n")
CompressAccelLogger.logInfo("CommandRouter, io.src_info.ptr: 0x%x\n", io.src_info.bits.ip)
CompressAccelLogger.logInfo("CommandRouter, io.src_info.size: %d\n", io.src_info.bits.isize)
}
val lit_buff_info_queue = Module(new Queue(new StreamInfo, queDepth))
val lit_buff_info_fire = DecoupledHelper(lit_buff_info_queue.io.enq.ready,
io.rocc_in.valid,
cur_funct === FUNCT_ZSTD_LIT_BUFF_INFO)
lit_buff_info_queue.io.enq.valid := lit_buff_info_fire.fire(lit_buff_info_queue.io.enq.ready)
lit_buff_info_queue.io.enq.bits.ip := cur_rs1
lit_buff_info_queue.io.enq.bits.isize := cur_rs2
io.buff_info.lit <> lit_buff_info_queue.io.deq
when (io.buff_info.lit.fire) {
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.lit.fire!\n")
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.lit.ip: 0x%x\n", io.buff_info.lit.bits.ip)
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.lit.isize: %d\n", io.buff_info.lit.bits.isize)
}
val seq_buff_info_queue = Module(new Queue(new StreamInfo, queDepth))
val seq_buff_info_fire = DecoupledHelper(seq_buff_info_queue.io.enq.ready,
io.rocc_in.valid,
cur_funct === FUNCT_ZSTD_SEQ_BUFF_INFO)
seq_buff_info_queue.io.enq.valid := seq_buff_info_fire.fire(seq_buff_info_queue.io.enq.ready)
seq_buff_info_queue.io.enq.bits.ip := cur_rs1
seq_buff_info_queue.io.enq.bits.isize := cur_rs2
io.buff_info.seq <> seq_buff_info_queue.io.deq
when (io.buff_info.seq.fire) {
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.seq.fire!\n")
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.seq.ip: 0x%x\n", io.buff_info.seq.bits.ip)
CompressAccelLogger.logInfo("CommandRouter, io.buff_info.seq.isize: %d\n", io.buff_info.seq.bits.isize)
}
val dst_info_queue = Module(new Queue(new DstInfo, queDepth))
val dst_info_fire = DecoupledHelper(io.rocc_in.valid,
dst_info_queue.io.enq.ready,
(cur_funct === FUNCT_ZSTD_DST_INFO) || (cur_funct === FUNCT_SNPY_DST_INFO))
dst_info_queue.io.enq.bits.op := cur_rs1
dst_info_queue.io.enq.bits.cmpflag := cur_rs2
dst_info_queue.io.enq.valid := dst_info_fire.fire(dst_info_queue.io.enq.ready)
io.dst_info <> dst_info_queue.io.deq
when (io.dst_info.fire) {
CompressAccelLogger.logInfo("CommandRouter, io.dst_info.fire!\n")
CompressAccelLogger.logInfo("CommandRouter, io.dst_info.op: 0x%x\n", io.dst_info.bits.op)
CompressAccelLogger.logInfo("CommandRouter, io.dst_info.cmpflag: %d\n", io.dst_info.bits.cmpflag)
}
val clevel_info_queue = Module(new Queue(UInt(5.W), queDepth))
val clevel_info_fire = DecoupledHelper(io.rocc_in.valid,
clevel_info_queue.io.enq.ready,
cur_funct === FUNCT_ZSTD_COMPRESSION_LEVEL)
clevel_info_queue.io.enq.bits := cur_rs1
clevel_info_queue.io.enq.valid := clevel_info_fire.fire(clevel_info_queue.io.enq.ready)
io.clevel_info <> clevel_info_queue.io.deq
when (io.clevel_info.fire) {
CompressAccelLogger.logInfo("CommandRouter, io.clevel_info.fire!\n")
CompressAccelLogger.logInfo("CommandRouter, io.clevel_info: %d\n", io.clevel_info.bits)
}
val LATENCY_INJECTION_CYCLES = RegInit(0.U(64.W))
val HAS_INTERMEDIATE_CACHE = RegInit(false.B)
io.LATENCY_INJECTION_CYCLES := LATENCY_INJECTION_CYCLES
io.HAS_INTERMEDIATE_CACHE := HAS_INTERMEDIATE_CACHE
val latency_injection_info_fire = DecoupledHelper(
io.rocc_in.valid,
cur_funct === FUNCT_LATENCY_INJECTION_INFO
)
when (latency_injection_info_fire.fire) {
LATENCY_INJECTION_CYCLES := cur_rs1
HAS_INTERMEDIATE_CACHE := cur_rs2(0).asBool
}
val zstd_finished_q = Module(new Queue(UInt(64.W), queDepth))
zstd_finished_q.io.enq <> io.zstd_finished_cnt
val snappy_finished_q = Module(new Queue(UInt(64.W), queDepth))
snappy_finished_q.io.enq <> io.snappy_finished_cnt
val zstd_done = zstd_finished_q.io.deq.valid && (zstd_dispatched_src_info === zstd_finished_q.io.deq.bits)
val snappy_done = snappy_finished_q.io.deq.valid && (snappy_dispatched_src_info === snappy_finished_q.io.deq.bits)
val compression_done = zstd_done || snappy_done
val do_check_completion_fire = DecoupledHelper(
cur_funct === FUNCT_CHECK_COMPLETION,
io.rocc_in.valid,
compression_done
)
zstd_finished_q.io.deq.ready := do_check_completion_fire.fire(compression_done)
snappy_finished_q.io.deq.ready := do_check_completion_fire.fire(compression_done)
when (do_check_completion_fire.fire) {
CompressAccelLogger.logInfo("Zstd Compressor CommandRouter, do_check_completion_fire.fire\n")
CompressAccelLogger.logInfo("Zstd Compressor CommandRouter, zstd_dispatched_src_info: %d\n", zstd_dispatched_src_info)
CompressAccelLogger.logInfo("Snappy Compressor CommandRouter, Snappy_dispatched_src_info: %d\n", snappy_dispatched_src_info)
}
io.rocc_in.ready := sfence_fire.fire(io.rocc_in.valid) ||
runtime_ht_num_entries_fire.fire(io.rocc_in.valid) ||
max_offset_allowed_fire.fire(io.rocc_in.valid) ||
src_info_fire.fire(io.rocc_in.valid) ||
lit_buff_info_fire.fire(io.rocc_in.valid) ||
seq_buff_info_fire.fire(io.rocc_in.valid) ||
dst_info_fire.fire(io.rocc_in.valid) ||
clevel_info_fire.fire(io.rocc_in.valid) ||
latency_injection_info_fire.fire(io.rocc_in.valid) ||
do_check_completion_fire.fire(io.rocc_in.valid)
io.rocc_out.valid := do_check_completion_fire.fire
io.rocc_out.bits.rd := io.rocc_in.bits.inst.rd
io.rocc_out.bits.data := Mux(ALGORITHM === ZSTD.U, zstd_dispatched_src_info, snappy_dispatched_src_info)
}
| module ZstdCompressorCommandRouter( // @[ZstdCompressorCommandRouter.scala:48:7]
input clock, // @[ZstdCompressorCommandRouter.scala:48:7]
input reset, // @[ZstdCompressorCommandRouter.scala:48:7]
output io_rocc_in_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
input [6:0] io_rocc_in_bits_inst_funct, // @[ZstdCompressorCommandRouter.scala:50:14]
input [4:0] io_rocc_in_bits_inst_rs2, // @[ZstdCompressorCommandRouter.scala:50:14]
input [4:0] io_rocc_in_bits_inst_rs1, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_inst_xd, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_inst_xs1, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_inst_xs2, // @[ZstdCompressorCommandRouter.scala:50:14]
input [4:0] io_rocc_in_bits_inst_rd, // @[ZstdCompressorCommandRouter.scala:50:14]
input [6:0] io_rocc_in_bits_inst_opcode, // @[ZstdCompressorCommandRouter.scala:50:14]
input [63:0] io_rocc_in_bits_rs1, // @[ZstdCompressorCommandRouter.scala:50:14]
input [63:0] io_rocc_in_bits_rs2, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_debug, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_cease, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_wfi, // @[ZstdCompressorCommandRouter.scala:50:14]
input [31:0] io_rocc_in_bits_status_isa, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_dprv, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_dv, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_prv, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_v, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_sd, // @[ZstdCompressorCommandRouter.scala:50:14]
input [22:0] io_rocc_in_bits_status_zero2, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mpv, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_gva, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mbe, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_sbe, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_sxl, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_uxl, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_sd_rv32, // @[ZstdCompressorCommandRouter.scala:50:14]
input [7:0] io_rocc_in_bits_status_zero1, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_tsr, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_tw, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_tvm, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mxr, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_sum, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mprv, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_xs, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_fs, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_mpp, // @[ZstdCompressorCommandRouter.scala:50:14]
input [1:0] io_rocc_in_bits_status_vs, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_spp, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mpie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_ube, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_spie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_upie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_mie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_hie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_sie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_in_bits_status_uie, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_rocc_out_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_rocc_out_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [4:0] io_rocc_out_bits_rd, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_rocc_out_bits_data, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_debug, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_cease, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_wfi, // @[ZstdCompressorCommandRouter.scala:50:14]
output [31:0] io_dmem_status_out_bits_status_isa, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_dprv, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_dv, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_prv, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_v, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_sd, // @[ZstdCompressorCommandRouter.scala:50:14]
output [22:0] io_dmem_status_out_bits_status_zero2, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mpv, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_gva, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mbe, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_sbe, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_sxl, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_uxl, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_sd_rv32, // @[ZstdCompressorCommandRouter.scala:50:14]
output [7:0] io_dmem_status_out_bits_status_zero1, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_tsr, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_tw, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_tvm, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mxr, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_sum, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mprv, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_xs, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_fs, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_mpp, // @[ZstdCompressorCommandRouter.scala:50:14]
output [1:0] io_dmem_status_out_bits_status_vs, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_spp, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mpie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_ube, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_spie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_upie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_mie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_hie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_sie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dmem_status_out_bits_status_uie, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_sfence_out, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_ALGORITHM, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_src_info_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_src_info_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_src_info_bits_ip, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_src_info_bits_isize, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_dst_info_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_dst_info_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_dst_info_bits_op, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_dst_info_bits_cmpflag, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_buff_info_lit_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_buff_info_lit_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_buff_info_lit_bits_ip, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_buff_info_lit_bits_isize, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_buff_info_seq_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_buff_info_seq_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_buff_info_seq_bits_ip, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_buff_info_seq_bits_isize, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_clevel_info_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_clevel_info_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
output [4:0] io_clevel_info_bits, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_SNAPPY_MAX_OFFSET_ALLOWED, // @[ZstdCompressorCommandRouter.scala:50:14]
output [4:0] io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2, // @[ZstdCompressorCommandRouter.scala:50:14]
output [63:0] io_LATENCY_INJECTION_CYCLES, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_HAS_INTERMEDIATE_CACHE, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_zstd_finished_cnt_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_zstd_finished_cnt_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
input [63:0] io_zstd_finished_cnt_bits, // @[ZstdCompressorCommandRouter.scala:50:14]
output io_snappy_finished_cnt_ready, // @[ZstdCompressorCommandRouter.scala:50:14]
input io_snappy_finished_cnt_valid, // @[ZstdCompressorCommandRouter.scala:50:14]
input [63:0] io_snappy_finished_cnt_bits // @[ZstdCompressorCommandRouter.scala:50:14]
);
wire _snappy_finished_q_io_deq_valid; // @[ZstdCompressorCommandRouter.scala:229:33]
wire [63:0] _snappy_finished_q_io_deq_bits; // @[ZstdCompressorCommandRouter.scala:229:33]
wire _zstd_finished_q_io_deq_valid; // @[ZstdCompressorCommandRouter.scala:226:31]
wire [63:0] _zstd_finished_q_io_deq_bits; // @[ZstdCompressorCommandRouter.scala:226:31]
wire _clevel_info_queue_io_enq_ready; // @[ZstdCompressorCommandRouter.scala:194:33]
wire _dst_info_queue_io_enq_ready; // @[ZstdCompressorCommandRouter.scala:179:30]
wire _seq_buff_info_queue_io_enq_ready; // @[ZstdCompressorCommandRouter.scala:164:35]
wire _lit_buff_info_queue_io_enq_ready; // @[ZstdCompressorCommandRouter.scala:149:35]
wire _src_info_queue_io_enq_ready; // @[ZstdCompressorCommandRouter.scala:126:30]
wire io_rocc_in_valid_0 = io_rocc_in_valid; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [6:0] io_rocc_in_bits_inst_funct_0 = io_rocc_in_bits_inst_funct; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_rocc_in_bits_inst_rs2_0 = io_rocc_in_bits_inst_rs2; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_rocc_in_bits_inst_rs1_0 = io_rocc_in_bits_inst_rs1; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_inst_xd_0 = io_rocc_in_bits_inst_xd; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_inst_xs1_0 = io_rocc_in_bits_inst_xs1; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_inst_xs2_0 = io_rocc_in_bits_inst_xs2; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_rocc_in_bits_inst_rd_0 = io_rocc_in_bits_inst_rd; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [6:0] io_rocc_in_bits_inst_opcode_0 = io_rocc_in_bits_inst_opcode; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_rocc_in_bits_rs1_0 = io_rocc_in_bits_rs1; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_rocc_in_bits_rs2_0 = io_rocc_in_bits_rs2; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_debug_0 = io_rocc_in_bits_status_debug; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_cease_0 = io_rocc_in_bits_status_cease; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_wfi_0 = io_rocc_in_bits_status_wfi; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [31:0] io_rocc_in_bits_status_isa_0 = io_rocc_in_bits_status_isa; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_dprv_0 = io_rocc_in_bits_status_dprv; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_dv_0 = io_rocc_in_bits_status_dv; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_prv_0 = io_rocc_in_bits_status_prv; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_v_0 = io_rocc_in_bits_status_v; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_sd_0 = io_rocc_in_bits_status_sd; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [22:0] io_rocc_in_bits_status_zero2_0 = io_rocc_in_bits_status_zero2; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mpv_0 = io_rocc_in_bits_status_mpv; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_gva_0 = io_rocc_in_bits_status_gva; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mbe_0 = io_rocc_in_bits_status_mbe; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_sbe_0 = io_rocc_in_bits_status_sbe; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_sxl_0 = io_rocc_in_bits_status_sxl; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_uxl_0 = io_rocc_in_bits_status_uxl; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_sd_rv32_0 = io_rocc_in_bits_status_sd_rv32; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [7:0] io_rocc_in_bits_status_zero1_0 = io_rocc_in_bits_status_zero1; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_tsr_0 = io_rocc_in_bits_status_tsr; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_tw_0 = io_rocc_in_bits_status_tw; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_tvm_0 = io_rocc_in_bits_status_tvm; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mxr_0 = io_rocc_in_bits_status_mxr; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_sum_0 = io_rocc_in_bits_status_sum; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mprv_0 = io_rocc_in_bits_status_mprv; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_xs_0 = io_rocc_in_bits_status_xs; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_fs_0 = io_rocc_in_bits_status_fs; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_mpp_0 = io_rocc_in_bits_status_mpp; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_rocc_in_bits_status_vs_0 = io_rocc_in_bits_status_vs; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_spp_0 = io_rocc_in_bits_status_spp; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mpie_0 = io_rocc_in_bits_status_mpie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_ube_0 = io_rocc_in_bits_status_ube; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_spie_0 = io_rocc_in_bits_status_spie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_upie_0 = io_rocc_in_bits_status_upie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_mie_0 = io_rocc_in_bits_status_mie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_hie_0 = io_rocc_in_bits_status_hie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_sie_0 = io_rocc_in_bits_status_sie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_in_bits_status_uie_0 = io_rocc_in_bits_status_uie; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_out_ready_0 = io_rocc_out_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_src_info_ready_0 = io_src_info_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dst_info_ready_0 = io_dst_info_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_buff_info_lit_ready_0 = io_buff_info_lit_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_buff_info_seq_ready_0 = io_buff_info_seq_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_clevel_info_ready_0 = io_clevel_info_ready; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_zstd_finished_cnt_valid_0 = io_zstd_finished_cnt_valid; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_zstd_finished_cnt_bits_0 = io_zstd_finished_cnt_bits; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_snappy_finished_cnt_valid_0 = io_snappy_finished_cnt_valid; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_snappy_finished_cnt_bits_0 = io_snappy_finished_cnt_bits; // @[ZstdCompressorCommandRouter.scala:48:7]
wire _io_rocc_in_ready_T_14; // @[ZstdCompressorCommandRouter.scala:258:74]
wire [6:0] io_dmem_status_out_bits_inst_funct = io_rocc_in_bits_inst_funct_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_dmem_status_out_bits_inst_rs2 = io_rocc_in_bits_inst_rs2_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_dmem_status_out_bits_inst_rs1 = io_rocc_in_bits_inst_rs1_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_inst_xd = io_rocc_in_bits_inst_xd_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_inst_xs1 = io_rocc_in_bits_inst_xs1_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_inst_xs2 = io_rocc_in_bits_inst_xs2_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_rocc_out_bits_rd_0 = io_rocc_in_bits_inst_rd_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_dmem_status_out_bits_inst_rd = io_rocc_in_bits_inst_rd_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [6:0] io_dmem_status_out_bits_inst_opcode = io_rocc_in_bits_inst_opcode_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_dmem_status_out_bits_rs1 = io_rocc_in_bits_rs1_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_dmem_status_out_bits_rs2 = io_rocc_in_bits_rs2_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_debug_0 = io_rocc_in_bits_status_debug_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_cease_0 = io_rocc_in_bits_status_cease_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_wfi_0 = io_rocc_in_bits_status_wfi_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [31:0] io_dmem_status_out_bits_status_isa_0 = io_rocc_in_bits_status_isa_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_dprv_0 = io_rocc_in_bits_status_dprv_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_dv_0 = io_rocc_in_bits_status_dv_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_prv_0 = io_rocc_in_bits_status_prv_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_v_0 = io_rocc_in_bits_status_v_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_sd_0 = io_rocc_in_bits_status_sd_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [22:0] io_dmem_status_out_bits_status_zero2_0 = io_rocc_in_bits_status_zero2_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mpv_0 = io_rocc_in_bits_status_mpv_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_gva_0 = io_rocc_in_bits_status_gva_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mbe_0 = io_rocc_in_bits_status_mbe_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_sbe_0 = io_rocc_in_bits_status_sbe_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_sxl_0 = io_rocc_in_bits_status_sxl_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_uxl_0 = io_rocc_in_bits_status_uxl_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_sd_rv32_0 = io_rocc_in_bits_status_sd_rv32_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [7:0] io_dmem_status_out_bits_status_zero1_0 = io_rocc_in_bits_status_zero1_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_tsr_0 = io_rocc_in_bits_status_tsr_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_tw_0 = io_rocc_in_bits_status_tw_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_tvm_0 = io_rocc_in_bits_status_tvm_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mxr_0 = io_rocc_in_bits_status_mxr_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_sum_0 = io_rocc_in_bits_status_sum_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mprv_0 = io_rocc_in_bits_status_mprv_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_xs_0 = io_rocc_in_bits_status_xs_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_fs_0 = io_rocc_in_bits_status_fs_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_mpp_0 = io_rocc_in_bits_status_mpp_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [1:0] io_dmem_status_out_bits_status_vs_0 = io_rocc_in_bits_status_vs_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_spp_0 = io_rocc_in_bits_status_spp_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mpie_0 = io_rocc_in_bits_status_mpie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_ube_0 = io_rocc_in_bits_status_ube_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_spie_0 = io_rocc_in_bits_status_spie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_upie_0 = io_rocc_in_bits_status_upie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_mie_0 = io_rocc_in_bits_status_mie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_hie_0 = io_rocc_in_bits_status_hie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_sie_0 = io_rocc_in_bits_status_sie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_bits_status_uie_0 = io_rocc_in_bits_status_uie_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire _io_rocc_out_valid_T_1; // @[Misc.scala:29:18]
wire [63:0] _io_rocc_out_bits_data_T_1; // @[ZstdCompressorCommandRouter.scala:263:31]
wire _io_dmem_status_out_valid_T; // @[Decoupled.scala:51:35]
wire _io_sfence_out_T; // @[Misc.scala:29:18]
wire io_rocc_in_ready_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_rocc_out_bits_data_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_rocc_out_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dmem_status_out_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_src_info_bits_ip_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_src_info_bits_isize_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_src_info_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_dst_info_bits_op_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_dst_info_bits_cmpflag_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_dst_info_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_buff_info_lit_bits_ip_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_buff_info_lit_bits_isize_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_buff_info_lit_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_buff_info_seq_bits_ip_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_buff_info_seq_bits_isize_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_buff_info_seq_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_clevel_info_valid_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_clevel_info_bits_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_zstd_finished_cnt_ready_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_snappy_finished_cnt_ready_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_sfence_out_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_ALGORITHM_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_SNAPPY_MAX_OFFSET_ALLOWED_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [4:0] io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire [63:0] io_LATENCY_INJECTION_CYCLES_0; // @[ZstdCompressorCommandRouter.scala:48:7]
wire io_HAS_INTERMEDIATE_CACHE_0; // @[ZstdCompressorCommandRouter.scala:48:7]
reg [63:0] snappy_dispatched_src_info; // @[ZstdCompressorCommandRouter.scala:65:43]
reg [63:0] zstd_dispatched_src_info; // @[ZstdCompressorCommandRouter.scala:66:41]
wire _T = io_rocc_in_bits_inst_funct_0 == 7'h0; // @[ZstdCompressorCommandRouter.scala:48:7, :73:47]
assign _io_sfence_out_T = io_rocc_in_valid_0 & _T; // @[Misc.scala:29:18]
assign io_sfence_out_0 = _io_sfence_out_T; // @[Misc.scala:29:18]
assign _io_dmem_status_out_valid_T = io_rocc_in_ready_0 & io_rocc_in_valid_0; // @[Decoupled.scala:51:35]
assign io_dmem_status_out_valid_0 = _io_dmem_status_out_valid_T; // @[Decoupled.scala:51:35]
reg [63:0] loginfo_cycles; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38]
reg ALGORITHM; // @[ZstdCompressorCommandRouter.scala:82:26]
assign io_ALGORITHM_0 = ALGORITHM; // @[ZstdCompressorCommandRouter.scala:48:7, :82:26]
reg prev_algo; // @[ZstdCompressorCommandRouter.scala:85:26]
reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38]
reg [63:0] SNAPPY_MAX_OFFSET_ALLOWED; // @[ZstdCompressorCommandRouter.scala:90:42]
assign io_SNAPPY_MAX_OFFSET_ALLOWED_0 = SNAPPY_MAX_OFFSET_ALLOWED; // @[ZstdCompressorCommandRouter.scala:48:7, :90:42]
wire _T_11 = io_rocc_in_bits_inst_funct_0 == 7'h8; // @[ZstdCompressorCommandRouter.scala:48:7, :95:15]
reg [4:0] SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2; // @[ZstdCompressorCommandRouter.scala:102:51]
assign io_SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2_0 = SNAPPY_RUNTIME_HT_NUM_ENTRIES_LOG2; // @[ZstdCompressorCommandRouter.scala:48:7, :102:51]
wire _T_13 = io_rocc_in_bits_inst_funct_0 == 7'h9; // @[ZstdCompressorCommandRouter.scala:48:7, :107:15]
wire _T_34 = io_rocc_in_bits_inst_funct_0 == 7'h1; // @[ZstdCompressorCommandRouter.scala:48:7, :114:39]
wire _T_17 = _io_dmem_status_out_valid_T & _T_34; // @[Decoupled.scala:51:35]
wire [64:0] _nxt_dispatched_src_info_T = {1'h0, zstd_dispatched_src_info} + 65'h1; // @[ZstdCompressorCommandRouter.scala:66:41, :115:60]
wire [63:0] nxt_dispatched_src_info = _nxt_dispatched_src_info_T[63:0]; // @[ZstdCompressorCommandRouter.scala:115:60]
reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38]
wire _T_30 = io_rocc_in_bits_inst_funct_0 == 7'h6; // @[ZstdCompressorCommandRouter.scala:48:7, :120:39]
wire _T_24 = _io_dmem_status_out_valid_T & _T_30; // @[Decoupled.scala:51:35]
wire [64:0] _nxt_dispatched_src_info_T_1 = {1'h0, snappy_dispatched_src_info} + 65'h1; // @[ZstdCompressorCommandRouter.scala:65:43, :121:62]
wire [63:0] nxt_dispatched_src_info_1 = _nxt_dispatched_src_info_T_1[63:0]; // @[ZstdCompressorCommandRouter.scala:121:62]
reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38]
wire _T_31 = _T_34 | _T_30; // @[ZstdCompressorCommandRouter.scala:114:39, :120:39, :129:75]
wire _src_info_queue_io_enq_valid_T = io_rocc_in_valid_0 & _T_31; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38]
wire _T_48 = io_rocc_in_bits_inst_funct_0 == 7'h2; // @[ZstdCompressorCommandRouter.scala:48:7, :152:54]
wire _lit_buff_info_queue_io_enq_valid_T = io_rocc_in_valid_0 & _T_48; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38]
wire _T_62 = io_rocc_in_bits_inst_funct_0 == 7'h3; // @[ZstdCompressorCommandRouter.scala:48:7, :167:54]
wire _seq_buff_info_queue_io_enq_valid_T = io_rocc_in_valid_0 & _T_62; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38]
wire _T_78 = io_rocc_in_bits_inst_funct_0 == 7'h4 | io_rocc_in_bits_inst_funct_0 == 7'h7; // @[ZstdCompressorCommandRouter.scala:48:7, :182:{50,75,89}]
wire _dst_info_queue_io_enq_valid_T = io_rocc_in_valid_0 & _T_78; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38]
wire _T_92 = io_rocc_in_bits_inst_funct_0 == 7'h5; // @[ZstdCompressorCommandRouter.scala:48:7, :197:52]
wire _clevel_info_queue_io_enq_valid_T = io_rocc_in_valid_0 & _T_92; // @[Misc.scala:26:53]
reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38]
reg [63:0] LATENCY_INJECTION_CYCLES; // @[ZstdCompressorCommandRouter.scala:209:41]
assign io_LATENCY_INJECTION_CYCLES_0 = LATENCY_INJECTION_CYCLES; // @[ZstdCompressorCommandRouter.scala:48:7, :209:41]
reg HAS_INTERMEDIATE_CACHE; // @[ZstdCompressorCommandRouter.scala:210:39]
assign io_HAS_INTERMEDIATE_CACHE_0 = HAS_INTERMEDIATE_CACHE; // @[ZstdCompressorCommandRouter.scala:48:7, :210:39]
wire _T_102 = io_rocc_in_bits_inst_funct_0 == 7'hA; // @[ZstdCompressorCommandRouter.scala:48:7, :217:15]
wire _HAS_INTERMEDIATE_CACHE_T = io_rocc_in_bits_rs2_0[0]; // @[ZstdCompressorCommandRouter.scala:48:7, :222:38]
wire _zstd_done_T = zstd_dispatched_src_info == _zstd_finished_q_io_deq_bits; // @[ZstdCompressorCommandRouter.scala:66:41, :226:31, :232:77]
wire zstd_done = _zstd_finished_q_io_deq_valid & _zstd_done_T; // @[ZstdCompressorCommandRouter.scala:226:31, :232:{48,77}]
wire _snappy_done_T = snappy_dispatched_src_info == _snappy_finished_q_io_deq_bits; // @[ZstdCompressorCommandRouter.scala:65:43, :229:33, :233:83]
wire snappy_done = _snappy_finished_q_io_deq_valid & _snappy_done_T; // @[ZstdCompressorCommandRouter.scala:229:33, :233:{52,83}]
wire compression_done = zstd_done | snappy_done; // @[ZstdCompressorCommandRouter.scala:232:48, :233:52, :234:36]
wire _T_104 = io_rocc_in_bits_inst_funct_0 == 7'hB; // @[ZstdCompressorCommandRouter.scala:48:7, :236:45]
wire _T_105 = _T_104 & io_rocc_in_valid_0; // @[Misc.scala:26:53]
wire _zstd_finished_q_io_deq_ready_T; // @[Misc.scala:26:53]
assign _zstd_finished_q_io_deq_ready_T = _T_105; // @[Misc.scala:26:53]
wire _snappy_finished_q_io_deq_ready_T; // @[Misc.scala:26:53]
assign _snappy_finished_q_io_deq_ready_T = _T_105; // @[Misc.scala:26:53]
wire _io_rocc_out_valid_T; // @[Misc.scala:29:18]
assign _io_rocc_out_valid_T = _T_105; // @[Misc.scala:26:53, :29:18]
reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38]
reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33]
wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38]
wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_87( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1347 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1347; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1347; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1420 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1420; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1420; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1420; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1273 = _T_1347 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1273 & _a_set_T[0]; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1273 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1273 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1273 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}]
assign a_sizes_set = _T_1273 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1319 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1319 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1288 = _T_1420 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1288 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1288 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1288 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1391 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1391 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1373 = _T_1420 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1373 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1373 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1373 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_9( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74]
wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_16( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module MacUnit( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_postMul_e8_s24_60( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire io_fromPreMul_isInfB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:169:7]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_invalidExc_T = 1'h0; // @[MulAddRecFN.scala:272:31]
wire _io_invalidExc_T_2 = 1'h0; // @[MulAddRecFN.scala:273:32]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0; // @[MulAddRecFN.scala:169:7, :271:35]
wire notNaN_isInfProd = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire _io_invalidExc_T_5 = io_fromPreMul_isInfA_0; // @[MulAddRecFN.scala:169:7, :275:36]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1; // @[MulAddRecFN.scala:271:35, :272:57]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
| module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_296( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File SRAM.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.amba.AMBACorrupt
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
import freechips.rocketchip.resources.{DiplomaticSRAM, HasJustOneSeqMem}
import freechips.rocketchip.util.{BundleMap, SeqMemToAugmentedSeqMem}
/**
* AXI4 slave device to provide a RAM storage
*
* Setting wcorrupt=true is not enough to enable the w.user field
* You must also list AMBACorrupt in your master's requestFields
*
* @param address address range
* @param cacheable whether this ram is cacheable
* @param executable whether this ram is executable
* @param beatBytes number of bytes in each beat
* @param devName optional device name
* @param errors address ranges where all access should fail
* @param wcorrupt enable AMBACorrupt in w.user
*/
class AXI4RAM(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
beatBytes: Int = 4,
devName: Option[String] = None,
errors: Seq[AddressSet] = Nil,
wcorrupt: Boolean = true)
(implicit p: Parameters) extends DiplomaticSRAM(address, beatBytes, devName)
{
val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
Seq(AXI4SlaveParameters(
address = List(address) ++ errors,
resources = resources,
regionType = if (cacheable) RegionType.UNCACHED else RegionType.IDEMPOTENT,
executable = executable,
supportsRead = TransferSizes(1, beatBytes),
supportsWrite = TransferSizes(1, beatBytes),
interleavedId = Some(0))),
beatBytes = beatBytes,
requestKeys = if (wcorrupt) Seq(AMBACorrupt) else Seq(),
minLatency = 1)))
private val outer = this
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with HasJustOneSeqMem {
val (in, edgeIn) = node.in(0)
val laneDataBits = 8
val mem = makeSinglePortedByteWriteSeqMem(
size = BigInt(1) << mask.filter(b=>b).size,
lanes = beatBytes,
bits = laneDataBits)
val eccCode = None
val address = outer.address
val corrupt = if (edgeIn.bundle.requestFields.contains(AMBACorrupt)) Some(SyncReadMem(1 << mask.filter(b=>b).size, UInt(2.W))) else None
val r_addr = Cat((mask zip (in.ar.bits.addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)
val w_addr = Cat((mask zip (in.aw.bits.addr >> log2Ceil(beatBytes)).asBools).filter(_._1).map(_._2).reverse)
val r_sel0 = address.contains(in.ar.bits.addr)
val w_sel0 = address.contains(in.aw.bits.addr)
val w_full = RegInit(false.B)
val w_id = Reg(UInt())
val w_echo = Reg(BundleMap(in.params.echoFields))
val r_sel1 = RegNext(r_sel0)
val w_sel1 = RegNext(w_sel0)
when (in. b.fire) { w_full := false.B }
when (in.aw.fire) { w_full := true.B }
when (in.aw.fire) {
w_id := in.aw.bits.id
w_sel1 := w_sel0
w_echo :<= in.aw.bits.echo
}
val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
when (in.aw.fire && w_sel0) {
mem.write(w_addr, wdata, in.w.bits.strb.asBools)
corrupt.foreach { _.write(w_addr, in.w.bits.user(AMBACorrupt).asUInt) }
}
in. b.valid := w_full
in.aw.ready := in. w.valid && (in.b.ready || !w_full)
in. w.ready := in.aw.valid && (in.b.ready || !w_full)
in.b.bits.id := w_id
in.b.bits.resp := Mux(w_sel1, AXI4Parameters.RESP_OKAY, AXI4Parameters.RESP_DECERR)
in.b.bits.echo :<= w_echo
val r_full = RegInit(false.B)
val r_id = Reg(UInt())
val r_echo = Reg(BundleMap(in.params.echoFields))
when (in. r.fire) { r_full := false.B }
when (in.ar.fire) { r_full := true.B }
when (in.ar.fire) {
r_id := in.ar.bits.id
r_sel1 := r_sel0
r_echo :<= in.ar.bits.echo
}
val ren = in.ar.fire
val rdata = mem.readAndHold(r_addr, ren)
val rcorrupt = corrupt.map(_.readAndHold(r_addr, ren)(0)).getOrElse(false.B)
in. r.valid := r_full
in.ar.ready := in.r.ready || !r_full
in.r.bits.id := r_id
in.r.bits.resp := Mux(r_sel1, Mux(rcorrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY), AXI4Parameters.RESP_DECERR)
in.r.bits.data := Cat(rdata.reverse)
in.r.bits.echo :<= r_echo
in.r.bits.last := true.B
}
}
object AXI4RAM
{
def apply(
address: AddressSet,
cacheable: Boolean = true,
executable: Boolean = true,
beatBytes: Int = 4,
devName: Option[String] = None,
errors: Seq[AddressSet] = Nil,
wcorrupt: Boolean = true)
(implicit p: Parameters) =
{
val axi4ram = LazyModule(new AXI4RAM(
address = address,
cacheable = cacheable,
executable = executable,
beatBytes = beatBytes,
devName = devName,
errors = errors,
wcorrupt = wcorrupt))
axi4ram.node
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module AXI4RAM( // @[SRAM.scala:58:9]
input clock, // @[SRAM.scala:58:9]
input reset, // @[SRAM.scala:58:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [255:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [255:0] auto_in_r_bits_data // @[LazyModuleImp.scala:107:25]
);
wire nodeIn_ar_ready; // @[SRAM.scala:122:31]
wire nodeIn_aw_ready; // @[SRAM.scala:97:32]
wire [255:0] _mem_R0_data; // @[DescribedSRAM.scala:17:26]
reg w_full; // @[SRAM.scala:75:25]
reg [7:0] w_id; // @[SRAM.scala:76:21]
wire mem_MPORT_en = nodeIn_aw_ready & auto_in_aw_valid; // @[Decoupled.scala:51:35]
assign nodeIn_aw_ready = auto_in_w_valid & (auto_in_b_ready | ~w_full); // @[SRAM.scala:75:25, :97:{32,47,50}]
reg r_full; // @[SRAM.scala:104:25]
reg [7:0] r_id; // @[SRAM.scala:105:21]
wire ren = nodeIn_ar_ready & auto_in_ar_valid; // @[Decoupled.scala:51:35]
reg rdata_REG; // @[package.scala:100:91]
reg [7:0] rdata_r_0; // @[package.scala:88:63]
reg [7:0] rdata_r_1; // @[package.scala:88:63]
reg [7:0] rdata_r_2; // @[package.scala:88:63]
reg [7:0] rdata_r_3; // @[package.scala:88:63]
reg [7:0] rdata_r_4; // @[package.scala:88:63]
reg [7:0] rdata_r_5; // @[package.scala:88:63]
reg [7:0] rdata_r_6; // @[package.scala:88:63]
reg [7:0] rdata_r_7; // @[package.scala:88:63]
reg [7:0] rdata_r_8; // @[package.scala:88:63]
reg [7:0] rdata_r_9; // @[package.scala:88:63]
reg [7:0] rdata_r_10; // @[package.scala:88:63]
reg [7:0] rdata_r_11; // @[package.scala:88:63]
reg [7:0] rdata_r_12; // @[package.scala:88:63]
reg [7:0] rdata_r_13; // @[package.scala:88:63]
reg [7:0] rdata_r_14; // @[package.scala:88:63]
reg [7:0] rdata_r_15; // @[package.scala:88:63]
reg [7:0] rdata_r_16; // @[package.scala:88:63]
reg [7:0] rdata_r_17; // @[package.scala:88:63]
reg [7:0] rdata_r_18; // @[package.scala:88:63]
reg [7:0] rdata_r_19; // @[package.scala:88:63]
reg [7:0] rdata_r_20; // @[package.scala:88:63]
reg [7:0] rdata_r_21; // @[package.scala:88:63]
reg [7:0] rdata_r_22; // @[package.scala:88:63]
reg [7:0] rdata_r_23; // @[package.scala:88:63]
reg [7:0] rdata_r_24; // @[package.scala:88:63]
reg [7:0] rdata_r_25; // @[package.scala:88:63]
reg [7:0] rdata_r_26; // @[package.scala:88:63]
reg [7:0] rdata_r_27; // @[package.scala:88:63]
reg [7:0] rdata_r_28; // @[package.scala:88:63]
reg [7:0] rdata_r_29; // @[package.scala:88:63]
reg [7:0] rdata_r_30; // @[package.scala:88:63]
reg [7:0] rdata_r_31; // @[package.scala:88:63]
assign nodeIn_ar_ready = auto_in_r_ready | ~r_full; // @[SRAM.scala:104:25, :122:{31,34}]
always @(posedge clock) begin // @[SRAM.scala:58:9]
if (reset) begin // @[SRAM.scala:58:9]
w_full <= 1'h0; // @[SRAM.scala:75:25]
r_full <= 1'h0; // @[SRAM.scala:104:25]
end
else begin // @[SRAM.scala:58:9]
w_full <= mem_MPORT_en | ~(auto_in_b_ready & w_full) & w_full; // @[Decoupled.scala:51:35]
r_full <= ren | ~(auto_in_r_ready & r_full) & r_full; // @[Decoupled.scala:51:35]
end
if (mem_MPORT_en) // @[Decoupled.scala:51:35]
w_id <= auto_in_aw_bits_id; // @[SRAM.scala:76:21]
if (ren) // @[Decoupled.scala:51:35]
r_id <= auto_in_ar_bits_id; // @[SRAM.scala:105:21]
rdata_REG <= ren; // @[Decoupled.scala:51:35]
if (rdata_REG) begin // @[package.scala:100:91]
rdata_r_0 <= _mem_R0_data[7:0]; // @[package.scala:88:63]
rdata_r_1 <= _mem_R0_data[15:8]; // @[package.scala:88:63]
rdata_r_2 <= _mem_R0_data[23:16]; // @[package.scala:88:63]
rdata_r_3 <= _mem_R0_data[31:24]; // @[package.scala:88:63]
rdata_r_4 <= _mem_R0_data[39:32]; // @[package.scala:88:63]
rdata_r_5 <= _mem_R0_data[47:40]; // @[package.scala:88:63]
rdata_r_6 <= _mem_R0_data[55:48]; // @[package.scala:88:63]
rdata_r_7 <= _mem_R0_data[63:56]; // @[package.scala:88:63]
rdata_r_8 <= _mem_R0_data[71:64]; // @[package.scala:88:63]
rdata_r_9 <= _mem_R0_data[79:72]; // @[package.scala:88:63]
rdata_r_10 <= _mem_R0_data[87:80]; // @[package.scala:88:63]
rdata_r_11 <= _mem_R0_data[95:88]; // @[package.scala:88:63]
rdata_r_12 <= _mem_R0_data[103:96]; // @[package.scala:88:63]
rdata_r_13 <= _mem_R0_data[111:104]; // @[package.scala:88:63]
rdata_r_14 <= _mem_R0_data[119:112]; // @[package.scala:88:63]
rdata_r_15 <= _mem_R0_data[127:120]; // @[package.scala:88:63]
rdata_r_16 <= _mem_R0_data[135:128]; // @[package.scala:88:63]
rdata_r_17 <= _mem_R0_data[143:136]; // @[package.scala:88:63]
rdata_r_18 <= _mem_R0_data[151:144]; // @[package.scala:88:63]
rdata_r_19 <= _mem_R0_data[159:152]; // @[package.scala:88:63]
rdata_r_20 <= _mem_R0_data[167:160]; // @[package.scala:88:63]
rdata_r_21 <= _mem_R0_data[175:168]; // @[package.scala:88:63]
rdata_r_22 <= _mem_R0_data[183:176]; // @[package.scala:88:63]
rdata_r_23 <= _mem_R0_data[191:184]; // @[package.scala:88:63]
rdata_r_24 <= _mem_R0_data[199:192]; // @[package.scala:88:63]
rdata_r_25 <= _mem_R0_data[207:200]; // @[package.scala:88:63]
rdata_r_26 <= _mem_R0_data[215:208]; // @[package.scala:88:63]
rdata_r_27 <= _mem_R0_data[223:216]; // @[package.scala:88:63]
rdata_r_28 <= _mem_R0_data[231:224]; // @[package.scala:88:63]
rdata_r_29 <= _mem_R0_data[239:232]; // @[package.scala:88:63]
rdata_r_30 <= _mem_R0_data[247:240]; // @[package.scala:88:63]
rdata_r_31 <= _mem_R0_data[255:248]; // @[package.scala:88:63]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_44( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53]
wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38]
wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29]
wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42]
wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67]
wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
| module NoCMonitor_45( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [5:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26]
reg in_flight_8; // @[Monitor.scala:16:26]
reg in_flight_9; // @[Monitor.scala:16:26]
reg in_flight_10; // @[Monitor.scala:16:26]
reg in_flight_11; // @[Monitor.scala:16:26]
reg in_flight_12; // @[Monitor.scala:16:26]
reg in_flight_13; // @[Monitor.scala:16:26]
reg in_flight_14; // @[Monitor.scala:16:26]
reg in_flight_15; // @[Monitor.scala:16:26]
reg in_flight_16; // @[Monitor.scala:16:26]
reg in_flight_17; // @[Monitor.scala:16:26]
reg in_flight_18; // @[Monitor.scala:16:26]
reg in_flight_19; // @[Monitor.scala:16:26]
reg in_flight_20; // @[Monitor.scala:16:26]
reg in_flight_21; // @[Monitor.scala:16:26]
wire _GEN = io_in_flit_0_bits_virt_channel_id == 5'h0; // @[Monitor.scala:21:46]
wire _GEN_0 = io_in_flit_0_bits_virt_channel_id == 5'h1; // @[Monitor.scala:21:46]
wire _GEN_1 = io_in_flit_0_bits_virt_channel_id == 5'h2; // @[Monitor.scala:21:46]
wire _GEN_2 = io_in_flit_0_bits_virt_channel_id == 5'h3; // @[Monitor.scala:21:46]
wire _GEN_3 = io_in_flit_0_bits_virt_channel_id == 5'h4; // @[Monitor.scala:21:46]
wire _GEN_4 = io_in_flit_0_bits_virt_channel_id == 5'h5; // @[Monitor.scala:21:46]
wire _GEN_5 = io_in_flit_0_bits_virt_channel_id == 5'h6; // @[Monitor.scala:21:46]
wire _GEN_6 = io_in_flit_0_bits_virt_channel_id == 5'h7; // @[Monitor.scala:21:46]
wire _GEN_7 = io_in_flit_0_bits_virt_channel_id == 5'h8; // @[Monitor.scala:21:46]
wire _GEN_8 = io_in_flit_0_bits_virt_channel_id == 5'h9; // @[Monitor.scala:21:46]
wire _GEN_9 = io_in_flit_0_bits_virt_channel_id == 5'hC; // @[Monitor.scala:21:46]
wire _GEN_10 = io_in_flit_0_bits_virt_channel_id == 5'hD; // @[Monitor.scala:21:46]
wire _GEN_11 = io_in_flit_0_bits_virt_channel_id == 5'h10; // @[Monitor.scala:21:46]
wire _GEN_12 = io_in_flit_0_bits_virt_channel_id == 5'h11; // @[Monitor.scala:21:46] |
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
| module PE_257( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_1 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_12( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie7_is64_oe8_os24_1( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55]
wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41]
wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53]
wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28]
wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46]
wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32]
wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:288:41]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32]
wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22]
wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53, :288:41]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire [9:0] _sAdjustedExp_T = {io_in_sExp_0[8], io_in_sExp_0} + 10'h80; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25]
wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14]
wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}]
wire [25:0] _adjustedSig_T = io_in_sig_0[64:39]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23]
wire [38:0] _adjustedSig_T_1 = io_in_sig_0[38:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26]
wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}]
wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_15 = {25'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61]
wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17]
wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17]
wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17]
wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18]
wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15]
wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15]
wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73]
wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13]
wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftRegisterPriorityQueue.scala:
package compressacc
import chisel3._
import chisel3.util._
import chisel3.util._
// TODO : support enq & deq at the same cycle
class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle {
val output_prev = KeyValue(keyWidth, value)
val output_nxt = KeyValue(keyWidth, value)
val input_prev = Flipped(KeyValue(keyWidth, value))
val input_nxt = Flipped(KeyValue(keyWidth, value))
val cmd = Flipped(Valid(UInt(1.W)))
val insert_here = Input(Bool())
val cur_input_keyval = Flipped(KeyValue(keyWidth, value))
val cur_output_keyval = KeyValue(keyWidth, value)
}
class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module {
val io = IO(new PriorityQueueStageIO(keyWidth, value))
dontTouch(io)
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val MAX_VALUE = (1 << keyWidth) - 1
val key_reg = RegInit(MAX_VALUE.U(keyWidth.W))
val value_reg = Reg(value)
io.output_prev.key := key_reg
io.output_prev.value := value_reg
io.output_nxt.key := key_reg
io.output_nxt.value := value_reg
io.cur_output_keyval.key := key_reg
io.cur_output_keyval.value := value_reg
when (io.cmd.valid) {
switch (io.cmd.bits) {
is (CMD_DEQ) {
key_reg := io.input_nxt.key
value_reg := io.input_nxt.value
}
is (CMD_ENQ) {
when (io.insert_here) {
key_reg := io.cur_input_keyval.key
value_reg := io.cur_input_keyval.value
} .elsewhen (key_reg >= io.cur_input_keyval.key) {
key_reg := io.input_prev.key
value_reg := io.input_prev.value
} .otherwise {
// do nothing
}
}
}
}
}
object PriorityQueueStage {
def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v)
}
// TODO
// - This design is not scalable as the enqued_keyval is broadcasted to all the stages
// - Add pipeline registers later
class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle {
val cnt_bits = log2Ceil(queSize+1)
val counter = Output(UInt(cnt_bits.W))
val enq = Flipped(Decoupled(KeyValue(keyWidth, value)))
val deq = Decoupled(KeyValue(keyWidth, value))
}
class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module {
val keyWidthInternal = keyWidth + 1
val CMD_DEQ = 0.U
val CMD_ENQ = 1.U
val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value))
dontTouch(io)
val MAX_VALUE = ((1 << keyWidthInternal) - 1).U
val cnt_bits = log2Ceil(queSize+1)
// do not consider cases where we are inserting more entries then the queSize
val counter = RegInit(0.U(cnt_bits.W))
io.counter := counter
val full = (counter === queSize.U)
val empty = (counter === 0.U)
io.deq.valid := !empty
io.enq.ready := !full
when (io.enq.fire) {
counter := counter + 1.U
}
when (io.deq.fire) {
counter := counter - 1.U
}
val cmd_valid = io.enq.valid || io.deq.ready
val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ)
assert(!(io.enq.valid && io.deq.ready))
val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value)))
for (i <- 0 until (queSize - 1)) {
stages(i+1).io.input_prev <> stages(i).io.output_nxt
stages(i).io.input_nxt <> stages(i+1).io.output_prev
}
stages(queSize-1).io.input_nxt.key := MAX_VALUE
// stages(queSize-1).io.input_nxt.value :=
stages(queSize-1).io.input_nxt.value.symbol := 0.U
// stages(queSize-1).io.input_nxt.value.child(0) := 0.U
// stages(queSize-1).io.input_nxt.value.child(1) := 0.U
stages(0).io.input_prev.key := io.enq.bits.key
stages(0).io.input_prev.value <> io.enq.bits.value
for (i <- 0 until queSize) {
stages(i).io.cmd.valid := cmd_valid
stages(i).io.cmd.bits := cmd
stages(i).io.cur_input_keyval <> io.enq.bits
}
val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B)))
for (i <- 0 until queSize) {
is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key)
}
val is_large_or_equal_cat = Wire(UInt(queSize.W))
is_large_or_equal_cat := Cat(is_large_or_equal.reverse)
val insert_here_idx = PriorityEncoder(is_large_or_equal_cat)
for (i <- 0 until queSize) {
when (i.U === insert_here_idx) {
stages(i).io.insert_here := true.B
} .otherwise {
stages(i).io.insert_here := false.B
}
}
io.deq.bits <> stages(0).io.output_prev
}
| module PriorityQueueStage_33( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_166( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_187 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
| module OptimizationBarrier_PTE_1( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [9:0] io_x_reserved_for_future, // @[package.scala:268:18]
input [43:0] io_x_ppn, // @[package.scala:268:18]
input [1:0] io_x_reserved_for_software, // @[package.scala:268:18]
input io_x_d, // @[package.scala:268:18]
input io_x_a, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_x, // @[package.scala:268:18]
input io_x_w, // @[package.scala:268:18]
input io_x_r, // @[package.scala:268:18]
input io_x_v, // @[package.scala:268:18]
output [9:0] io_y_reserved_for_future, // @[package.scala:268:18]
output [43:0] io_y_ppn, // @[package.scala:268:18]
output [1:0] io_y_reserved_for_software, // @[package.scala:268:18]
output io_y_d, // @[package.scala:268:18]
output io_y_a, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_x, // @[package.scala:268:18]
output io_y_w, // @[package.scala:268:18]
output io_y_r, // @[package.scala:268:18]
output io_y_v // @[package.scala:268:18]
);
wire [9:0] io_x_reserved_for_future_0 = io_x_reserved_for_future; // @[package.scala:267:30]
wire [43:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire [1:0] io_x_reserved_for_software_0 = io_x_reserved_for_software; // @[package.scala:267:30]
wire io_x_d_0 = io_x_d; // @[package.scala:267:30]
wire io_x_a_0 = io_x_a; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_x_0 = io_x_x; // @[package.scala:267:30]
wire io_x_w_0 = io_x_w; // @[package.scala:267:30]
wire io_x_r_0 = io_x_r; // @[package.scala:267:30]
wire io_x_v_0 = io_x_v; // @[package.scala:267:30]
wire [9:0] io_y_reserved_for_future_0 = io_x_reserved_for_future_0; // @[package.scala:267:30]
wire [43:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire [1:0] io_y_reserved_for_software_0 = io_x_reserved_for_software_0; // @[package.scala:267:30]
wire io_y_d_0 = io_x_d_0; // @[package.scala:267:30]
wire io_y_a_0 = io_x_a_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_x_0 = io_x_x_0; // @[package.scala:267:30]
wire io_y_w_0 = io_x_w_0; // @[package.scala:267:30]
wire io_y_r_0 = io_x_r_0; // @[package.scala:267:30]
wire io_y_v_0 = io_x_v_0; // @[package.scala:267:30]
assign io_y_reserved_for_future = io_y_reserved_for_future_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_reserved_for_software = io_y_reserved_for_software_0; // @[package.scala:267:30]
assign io_y_d = io_y_d_0; // @[package.scala:267:30]
assign io_y_a = io_y_a_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_x = io_y_x_0; // @[package.scala:267:30]
assign io_y_w = io_y_w_0; // @[package.scala:267:30]
assign io_y_r = io_y_r_0; // @[package.scala:267:30]
assign io_y_v = io_y_v_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
| module IssueSlot_96( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_10( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52]
wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79]
wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77]
wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35]
wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35]
wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34]
wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34]
wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31]
wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31]
wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1587 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1587; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1587; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [3:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1660 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1660; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1660; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1660; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [3:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [15:0] inflight; // @[Monitor.scala:614:27]
reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [127:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [15:0] a_set; // @[Monitor.scala:626:34]
wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [127:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [15:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1513 = _T_1587 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1513 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1513 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1513 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1513 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1513 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [15:0] d_clr; // @[Monitor.scala:664:34]
wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1559 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1559 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35]
wire _T_1528 = _T_1660 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1528 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1528 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1528 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [15:0] inflight_1; // @[Monitor.scala:726:35]
wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [15:0] d_clr_1; // @[Monitor.scala:774:34]
wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1631 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1631 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire _T_1613 = _T_1660 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1613 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35]
wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1613 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1613 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113]
wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
| module RecFNToRecFN_165( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_29( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_66 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_67 = _source_ok_T_66 == 4'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1156 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1156; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1156; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1229 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1229; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1229; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1156 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1229 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1200 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1200 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1182 = _T_1229 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1182 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1182 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1182 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
| module IngressUnit_28( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_5_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_4_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_3_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_10, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_11, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_12, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_13, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_14, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_15, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_16, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_17, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_18, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_19, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_20, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_21, // @[IngressUnit.scala:24:14]
input io_out_credit_available_5_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_4_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_3_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_8, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_12, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_13, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_16, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_17, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_20, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_21, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_5_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_10, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_11, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_12, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_13, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_14, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_15, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_16, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_17, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_18, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_19, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_20, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_21, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [5:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [5:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [4:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [5:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _GEN; // @[Decoupled.scala:51:35]
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_5_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_4_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_3_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_10; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_11; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_12; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_13; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_14; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_15; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_16; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_17; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_18; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_19; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_20; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_21; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [5:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [5:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [5:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [5:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [4:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = io_in_bits_egress_id == 6'h22; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = io_in_bits_egress_id == 6'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = io_in_bits_egress_id == 6'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_12 = io_in_bits_egress_id == 6'h1E; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_13 = io_in_bits_egress_id == 6'h1A; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_14 = io_in_bits_egress_id == 6'h18; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_15 = io_in_bits_egress_id == 6'h1C; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_16 = io_in_bits_egress_id == 6'h16; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_17 = io_in_bits_egress_id == 6'h20; // @[IngressUnit.scala:30:72]
wire [3:0] _GEN_0 = {2'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_9, 1'h0} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_1 ? 4'h9 : 4'h0); // @[Mux.scala:30:73]
wire [3:0] _GEN_1 = {_GEN_0[3:2], _GEN_0[1:0] | {_route_buffer_io_enq_bits_flow_egress_node_id_T_2, 1'h0}} | {4{_route_buffer_io_enq_bits_flow_egress_node_id_T_12}} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_13 ? 4'hD : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_14 ? 4'hB : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_15 ? 4'hE : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_16 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire _GEN_2 = _route_buffer_io_enq_bits_flow_egress_node_id_T_9 | _route_buffer_io_enq_bits_flow_egress_node_id_T_17; // @[Mux.scala:30:73]
wire [1:0] _GEN_3 = {1'h0, _route_buffer_io_enq_bits_flow_egress_node_id_T_9} | {2{_route_buffer_io_enq_bits_flow_egress_node_id_T_2}}; // @[Mux.scala:30:73]
wire [4:0] _GEN_4 = {_GEN_2, _GEN_1}; // @[Mux.scala:30:73]
assign _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _GEN_4 == 5'h8; // @[Decoupled.scala:51:35]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _GEN_4 != 5'h8; // @[Decoupled.scala:51:35]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_37( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_50 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
| module MulAddRecFNToRaw_preMul_e8_s24_30( // @[MulAddRecFN.scala:71:7]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawA_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawA_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28]
wire [9:0] rawA_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawA_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [24:0] rawA_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawA_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28]
wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28]
wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32]
wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49]
wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [10:0] _sExpAlignedProd_T = 11'h12B; // @[MulAddRecFN.scala:100:19]
wire [11:0] _sExpAlignedProd_T_1 = 12'h46; // @[MulAddRecFN.scala:100:32]
wire [10:0] _sExpAlignedProd_T_2 = 11'h46; // @[MulAddRecFN.scala:100:32]
wire [10:0] sExpAlignedProd = 11'h46; // @[MulAddRecFN.scala:100:32]
wire [32:0] reduced4CExtra_shift = 33'h100000000; // @[primitives.scala:76:56]
wire [3:0] _reduced4CExtra_T_4 = 4'h0; // @[primitives.scala:77:20]
wire [3:0] _reduced4CExtra_T_13 = 4'h0; // @[primitives.scala:77:20]
wire [5:0] _reduced4CExtra_T_3 = 6'h0; // @[primitives.scala:77:20, :78:22]
wire [5:0] _reduced4CExtra_T_18 = 6'h0; // @[primitives.scala:77:20, :78:22]
wire [6:0] CAlignDist = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68]
wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[MulAddRecFN.scala:112:12, :122:68]
wire [11:0] _io_toPostMul_sExpSum_T = 12'h2E; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h2E; // @[MulAddRecFN.scala:158:53]
wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h2E; // @[MulAddRecFN.scala:158:53]
wire [4:0] io_toPostMul_CDom_CAlignDist = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire [4:0] _reduced4CExtra_T_2 = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'h0; // @[MulAddRecFN.scala:71:7, :74:16, :124:28, :161:47]
wire io_toPostMul_isZeroA = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _isMinCAlign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire isMinCAlign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _CIsDominant_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35]
wire io_toPostMul_isNaNAOrB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfA = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroB = 1'h0; // @[MulAddRecFN.scala:71:7]
wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawA_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:61:35]
wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53]
wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:53:53]
wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:55:23]
wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:56:41]
wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:56:33]
wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:57:41]
wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:57:33]
wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:59:25]
wire _signProd_T_1 = 1'h0; // @[MulAddRecFN.scala:97:49]
wire _doSubMags_T_1 = 1'h0; // @[MulAddRecFN.scala:102:49]
wire _reduced4CExtra_T_6 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_7 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_10 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_11 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_15 = 1'h0; // @[primitives.scala:77:20]
wire _reduced4CExtra_T_16 = 1'h0; // @[primitives.scala:77:20]
wire reduced4CExtra = 1'h0; // @[MulAddRecFN.scala:130:11]
wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[common.scala:82:56]
wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[common.scala:82:46]
wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[MulAddRecFN.scala:146:32]
wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[MulAddRecFN.scala:148:42]
wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :142:16]
wire [23:0] io_mulAddA = 24'h0; // @[MulAddRecFN.scala:71:7, :74:16, :141:16]
wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [32:0] io_a = 33'h115800000; // @[MulAddRecFN.scala:71:7, :74:16]
wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawA_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _rawA_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_5 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_8 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_9 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_12 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_14 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [1:0] _reduced4CExtra_T_17 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32]
wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30]
wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58]
wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire doSubMags; // @[MulAddRecFN.scala:102:42]
wire CIsDominant; // @[MulAddRecFN.scala:110:23]
wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20]
wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48]
wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _doSubMags_T = ~rawC_sign; // @[rawFloatFromRecFN.scala:55:23]
assign doSubMags = _doSubMags_T; // @[MulAddRecFN.scala:102:{30,42}]
assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42]
wire [11:0] _sNatCAlignDist_T = 12'h46 - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23]
wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42]
wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42]
wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42]
wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69]
wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23]
assign CIsDominant = _CIsDominant_T; // @[MulAddRecFN.scala:110:{9,23}]
wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60]
assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34]
wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33]
wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33]
wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23]
wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53]
wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}]
wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}]
wire [77:0] mainAlignedSigC = _mainAlignedSigC_T_4; // @[MulAddRecFN.scala:120:{94,100}]
wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:53:28, :55:23, :61:32]
wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30]
wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33]
assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15]
assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20]
wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28]
wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}]
wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32]
wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32]
wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}]
wire _alignedSigC_T_4 = _alignedSigC_T_2; // @[MulAddRecFN.scala:134:{39,44}]
wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}]
wire _alignedSigC_T_7 = _alignedSigC_T_6; // @[MulAddRecFN.scala:135:{39,44}]
wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44]
wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16]
assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30]
assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30]
wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}]
wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23]
assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46]
assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58]
wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : 11'h2E; // @[rawFloatFromRecFN.scala:55:23]
assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12]
assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20]
assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20]
assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48]
assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48]
assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7]
assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File NoC.scala:
package constellation.noc
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BundleBridgeSink, InModuleBody}
import freechips.rocketchip.util.ElaborationArtefacts
import freechips.rocketchip.prci._
import constellation.router._
import constellation.channel._
import constellation.routing.{RoutingRelation, ChannelRoutingInfo}
import constellation.topology.{PhysicalTopology, UnidirectionalLine}
class NoCTerminalIO(
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle {
val ingress = MixedVec(ingressParams.map { u => Flipped(new IngressChannel(u)) })
val egress = MixedVec(egressParams.map { u => new EgressChannel(u) })
}
class NoC(nocParams: NoCParams)(implicit p: Parameters) extends LazyModule {
override def shouldBeInlined = nocParams.inlineNoC
val internalParams = InternalNoCParams(nocParams)
val allChannelParams = internalParams.channelParams
val allIngressParams = internalParams.ingressParams
val allEgressParams = internalParams.egressParams
val allRouterParams = internalParams.routerParams
val iP = p.alterPartial({ case InternalNoCKey => internalParams })
val nNodes = nocParams.topology.nNodes
val nocName = nocParams.nocName
val skipValidationChecks = nocParams.skipValidationChecks
val clockSourceNodes = Seq.tabulate(nNodes) { i => ClockSourceNode(Seq(ClockSourceParameters())) }
val router_sink_domains = Seq.tabulate(nNodes) { i =>
val router_sink_domain = LazyModule(new ClockSinkDomain(ClockSinkParameters(
name = Some(s"${nocName}_router_$i")
)))
router_sink_domain.clockNode := clockSourceNodes(i)
router_sink_domain
}
val routers = Seq.tabulate(nNodes) { i => router_sink_domains(i) {
val inParams = allChannelParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val outParams = allChannelParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val ingressParams = allIngressParams.filter(_.destId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val egressParams = allEgressParams.filter(_.srcId == i).map(
_.copy(payloadBits=allRouterParams(i).user.payloadBits)
)
val noIn = inParams.size + ingressParams.size == 0
val noOut = outParams.size + egressParams.size == 0
if (noIn || noOut) {
println(s"Constellation WARNING: $nocName router $i seems to be unused, it will not be generated")
None
} else {
Some(LazyModule(new Router(
routerParams = allRouterParams(i),
preDiplomaticInParams = inParams,
preDiplomaticIngressParams = ingressParams,
outDests = outParams.map(_.destId),
egressIds = egressParams.map(_.egressId)
)(iP)))
}
}}.flatten
val ingressNodes = allIngressParams.map { u => IngressChannelSourceNode(u.destId) }
val egressNodes = allEgressParams.map { u => EgressChannelDestNode(u) }
// Generate channels between routers diplomatically
Seq.tabulate(nNodes, nNodes) { case (i, j) => if (i != j) {
val routerI = routers.find(_.nodeId == i)
val routerJ = routers.find(_.nodeId == j)
if (routerI.isDefined && routerJ.isDefined) {
val sourceNodes: Seq[ChannelSourceNode] = routerI.get.sourceNodes.filter(_.destId == j)
val destNodes: Seq[ChannelDestNode] = routerJ.get.destNodes.filter(_.destParams.srcId == i)
require (sourceNodes.size == destNodes.size)
(sourceNodes zip destNodes).foreach { case (src, dst) =>
val channelParam = allChannelParams.find(c => c.srcId == i && c.destId == j).get
router_sink_domains(j) {
implicit val p: Parameters = iP
(dst
:= ChannelWidthWidget(routerJ.get.payloadBits, routerI.get.payloadBits)
:= channelParam.channelGen(p)(src)
)
}
}
}
}}
// Generate terminal channels diplomatically
routers.foreach { dst => router_sink_domains(dst.nodeId) {
implicit val p: Parameters = iP
dst.ingressNodes.foreach(n => {
val ingressId = n.destParams.ingressId
require(dst.payloadBits <= allIngressParams(ingressId).payloadBits)
(n
:= IngressWidthWidget(dst.payloadBits, allIngressParams(ingressId).payloadBits)
:= ingressNodes(ingressId)
)
})
dst.egressNodes.foreach(n => {
val egressId = n.egressId
require(dst.payloadBits <= allEgressParams(egressId).payloadBits)
(egressNodes(egressId)
:= EgressWidthWidget(allEgressParams(egressId).payloadBits, dst.payloadBits)
:= n
)
})
}}
val debugNodes = routers.map { r =>
val sink = BundleBridgeSink[DebugBundle]()
sink := r.debugNode
sink
}
val ctrlNodes = if (nocParams.hasCtrl) {
(0 until nNodes).map { i =>
routers.find(_.nodeId == i).map { r =>
val sink = BundleBridgeSink[RouterCtrlBundle]()
sink := r.ctrlNode.get
sink
}
}
} else {
Nil
}
println(s"Constellation: $nocName Finished parameter validation")
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
println(s"Constellation: $nocName Starting NoC RTL generation")
val io = IO(new NoCTerminalIO(allIngressParams, allEgressParams)(iP) {
val router_clocks = Vec(nNodes, Input(new ClockBundle(ClockBundleParameters())))
val router_ctrl = if (nocParams.hasCtrl) Vec(nNodes, new RouterCtrlBundle) else Nil
})
(io.ingress zip ingressNodes.map(_.out(0)._1)).foreach { case (l,r) => r <> l }
(io.egress zip egressNodes .map(_.in (0)._1)).foreach { case (l,r) => l <> r }
(io.router_clocks zip clockSourceNodes.map(_.out(0)._1)).foreach { case (l,r) => l <> r }
if (nocParams.hasCtrl) {
ctrlNodes.zipWithIndex.map { case (c,i) =>
if (c.isDefined) {
io.router_ctrl(i) <> c.get.in(0)._1
} else {
io.router_ctrl(i) <> DontCare
}
}
}
// TODO: These assume a single clock-domain across the entire noc
val debug_va_stall_ctr = RegInit(0.U(64.W))
val debug_sa_stall_ctr = RegInit(0.U(64.W))
val debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr
debug_va_stall_ctr := debug_va_stall_ctr + debugNodes.map(_.in(0)._1.va_stall.reduce(_+_)).reduce(_+_)
debug_sa_stall_ctr := debug_sa_stall_ctr + debugNodes.map(_.in(0)._1.sa_stall.reduce(_+_)).reduce(_+_)
dontTouch(debug_va_stall_ctr)
dontTouch(debug_sa_stall_ctr)
dontTouch(debug_any_stall_ctr)
def prepend(s: String) = Seq(nocName, s).mkString(".")
ElaborationArtefacts.add(prepend("noc.graphml"), graphML)
val adjList = routers.map { r =>
val outs = r.outParams.map(o => s"${o.destId}").mkString(" ")
val egresses = r.egressParams.map(e => s"e${e.egressId}").mkString(" ")
val ingresses = r.ingressParams.map(i => s"i${i.ingressId} ${r.nodeId}")
(Seq(s"${r.nodeId} $outs $egresses") ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.adjlist"), adjList)
val xys = routers.map(r => {
val n = r.nodeId
val ids = (Seq(r.nodeId.toString)
++ r.egressParams.map(e => s"e${e.egressId}")
++ r.ingressParams.map(i => s"i${i.ingressId}")
)
val plotter = nocParams.topology.plotter
val coords = (Seq(plotter.node(r.nodeId))
++ Seq.tabulate(r.egressParams.size ) { i => plotter. egress(i, r. egressParams.size, r.nodeId) }
++ Seq.tabulate(r.ingressParams.size) { i => plotter.ingress(i, r.ingressParams.size, r.nodeId) }
)
(ids zip coords).map { case (i, (x, y)) => s"$i $x $y" }.mkString("\n")
}).mkString("\n")
ElaborationArtefacts.add(prepend("noc.xy"), xys)
val edgeProps = routers.map { r =>
val outs = r.outParams.map { o =>
(Seq(s"${r.nodeId} ${o.destId}") ++ (if (o.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val egresses = r.egressParams.map { e =>
(Seq(s"${r.nodeId} e${e.egressId}") ++ (if (e.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
val ingresses = r.ingressParams.map { i =>
(Seq(s"i${i.ingressId} ${r.nodeId}") ++ (if (i.possibleFlows.size == 0) Some("unused") else None))
.mkString(" ")
}
(outs ++ egresses ++ ingresses).mkString("\n")
}.mkString("\n")
ElaborationArtefacts.add(prepend("noc.edgeprops"), edgeProps)
println(s"Constellation: $nocName Finished NoC RTL generation")
}
}
| module NoC_2( // @[NoC.scala:141:9]
input clock, // @[NoC.scala:141:9]
input reset, // @[NoC.scala:141:9]
output io_ingress_21_flit_ready, // @[NoC.scala:143:16]
input io_ingress_21_flit_valid, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_21_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_21_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_21_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_19_flit_ready, // @[NoC.scala:143:16]
input io_ingress_19_flit_valid, // @[NoC.scala:143:16]
input io_ingress_19_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_19_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_19_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_19_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_17_flit_ready, // @[NoC.scala:143:16]
input io_ingress_17_flit_valid, // @[NoC.scala:143:16]
input io_ingress_17_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_17_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_17_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_17_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_15_flit_ready, // @[NoC.scala:143:16]
input io_ingress_15_flit_valid, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_15_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_15_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_15_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_13_flit_ready, // @[NoC.scala:143:16]
input io_ingress_13_flit_valid, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_13_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_13_flit_bits_payload, // @[NoC.scala:143:16]
input [2:0] io_ingress_13_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_9_flit_ready, // @[NoC.scala:143:16]
input io_ingress_9_flit_valid, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_9_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_9_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_9_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_6_flit_ready, // @[NoC.scala:143:16]
input io_ingress_6_flit_valid, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_6_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_6_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_6_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_3_flit_ready, // @[NoC.scala:143:16]
input io_ingress_3_flit_valid, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_3_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_3_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_3_flit_bits_egress_id, // @[NoC.scala:143:16]
output io_ingress_0_flit_ready, // @[NoC.scala:143:16]
input io_ingress_0_flit_valid, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_head, // @[NoC.scala:143:16]
input io_ingress_0_flit_bits_tail, // @[NoC.scala:143:16]
input [72:0] io_ingress_0_flit_bits_payload, // @[NoC.scala:143:16]
input [4:0] io_ingress_0_flit_bits_egress_id, // @[NoC.scala:143:16]
input io_egress_22_flit_ready, // @[NoC.scala:143:16]
output io_egress_22_flit_valid, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_22_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_21_flit_ready, // @[NoC.scala:143:16]
output io_egress_21_flit_valid, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_21_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_20_flit_ready, // @[NoC.scala:143:16]
output io_egress_20_flit_valid, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_20_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_20_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_19_flit_ready, // @[NoC.scala:143:16]
output io_egress_19_flit_valid, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_19_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_18_flit_ready, // @[NoC.scala:143:16]
output io_egress_18_flit_valid, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_18_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_17_flit_ready, // @[NoC.scala:143:16]
output io_egress_17_flit_valid, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_17_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_17_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_16_flit_ready, // @[NoC.scala:143:16]
output io_egress_16_flit_valid, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_16_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_15_flit_ready, // @[NoC.scala:143:16]
output io_egress_15_flit_valid, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_15_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_14_flit_ready, // @[NoC.scala:143:16]
output io_egress_14_flit_valid, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_14_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_14_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_13_flit_ready, // @[NoC.scala:143:16]
output io_egress_13_flit_valid, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_13_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_12_flit_ready, // @[NoC.scala:143:16]
output io_egress_12_flit_valid, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_12_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_11_flit_ready, // @[NoC.scala:143:16]
output io_egress_11_flit_valid, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_11_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_11_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_10_flit_ready, // @[NoC.scala:143:16]
output io_egress_10_flit_valid, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_10_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_9_flit_ready, // @[NoC.scala:143:16]
output io_egress_9_flit_valid, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_9_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_8_flit_ready, // @[NoC.scala:143:16]
output io_egress_8_flit_valid, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_8_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_8_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_7_flit_ready, // @[NoC.scala:143:16]
output io_egress_7_flit_valid, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_7_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_7_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_6_flit_ready, // @[NoC.scala:143:16]
output io_egress_6_flit_valid, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_6_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_5_flit_ready, // @[NoC.scala:143:16]
output io_egress_5_flit_valid, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_5_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_5_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_4_flit_ready, // @[NoC.scala:143:16]
output io_egress_4_flit_valid, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_4_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_3_flit_ready, // @[NoC.scala:143:16]
output io_egress_3_flit_valid, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_3_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_3_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_2_flit_ready, // @[NoC.scala:143:16]
output io_egress_2_flit_valid, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_2_flit_bits_tail, // @[NoC.scala:143:16]
input io_egress_1_flit_ready, // @[NoC.scala:143:16]
output io_egress_1_flit_valid, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_1_flit_bits_tail, // @[NoC.scala:143:16]
output [72:0] io_egress_1_flit_bits_payload, // @[NoC.scala:143:16]
input io_egress_0_flit_ready, // @[NoC.scala:143:16]
output io_egress_0_flit_valid, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_head, // @[NoC.scala:143:16]
output io_egress_0_flit_bits_tail, // @[NoC.scala:143:16]
input io_router_clocks_0_clock, // @[NoC.scala:143:16]
input io_router_clocks_0_reset, // @[NoC.scala:143:16]
input io_router_clocks_1_clock, // @[NoC.scala:143:16]
input io_router_clocks_1_reset, // @[NoC.scala:143:16]
input io_router_clocks_2_clock, // @[NoC.scala:143:16]
input io_router_clocks_2_reset, // @[NoC.scala:143:16]
input io_router_clocks_3_clock, // @[NoC.scala:143:16]
input io_router_clocks_3_reset, // @[NoC.scala:143:16]
input io_router_clocks_4_clock, // @[NoC.scala:143:16]
input io_router_clocks_4_reset, // @[NoC.scala:143:16]
input io_router_clocks_5_clock, // @[NoC.scala:143:16]
input io_router_clocks_5_reset, // @[NoC.scala:143:16]
input io_router_clocks_6_clock, // @[NoC.scala:143:16]
input io_router_clocks_6_reset, // @[NoC.scala:143:16]
input io_router_clocks_7_clock, // @[NoC.scala:143:16]
input io_router_clocks_7_reset, // @[NoC.scala:143:16]
input io_router_clocks_8_clock, // @[NoC.scala:143:16]
input io_router_clocks_8_reset, // @[NoC.scala:143:16]
input io_router_clocks_9_clock, // @[NoC.scala:143:16]
input io_router_clocks_9_reset, // @[NoC.scala:143:16]
input io_router_clocks_10_clock, // @[NoC.scala:143:16]
input io_router_clocks_10_reset, // @[NoC.scala:143:16]
input io_router_clocks_11_clock, // @[NoC.scala:143:16]
input io_router_clocks_11_reset, // @[NoC.scala:143:16]
input io_router_clocks_12_clock, // @[NoC.scala:143:16]
input io_router_clocks_12_reset, // @[NoC.scala:143:16]
input io_router_clocks_13_clock, // @[NoC.scala:143:16]
input io_router_clocks_13_reset, // @[NoC.scala:143:16]
input io_router_clocks_14_clock, // @[NoC.scala:143:16]
input io_router_clocks_14_reset, // @[NoC.scala:143:16]
input io_router_clocks_15_clock, // @[NoC.scala:143:16]
input io_router_clocks_15_reset // @[NoC.scala:143:16]
);
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_15_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_15_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_14_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_14_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_13_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_13_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_12_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_12_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_12_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_12_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_12_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_11_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_11_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_11_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_11_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_11_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_10_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_10_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_9_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_9_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_2_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_1_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_8_auto_routers_source_nodes_out_0_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_2_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_2_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_1_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_1_vc_free; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_0_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_8_auto_routers_dest_nodes_in_0_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_7_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_7_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_7_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_6_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_6_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_6_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_5_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_5_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_5_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_4_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_4_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_4_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_3_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_3_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_3_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_2_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_2_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_2_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_debug_out_va_stall_1; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_debug_out_sa_stall_1; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_1_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_1_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_1_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_va_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_va_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_va_stall_4; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_sa_stall_0; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_sa_stall_2; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_debug_out_sa_stall_4; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_valid; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_head; // @[NoC.scala:41:40]
wire _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_tail; // @[NoC.scala:41:40]
wire [72:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_payload; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_vnet_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node; // @[NoC.scala:41:40]
wire [1:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_ingress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node; // @[NoC.scala:41:40]
wire [2:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_flow_egress_node_id; // @[NoC.scala:41:40]
wire [3:0] _router_sink_domain_auto_routers_source_nodes_out_flit_0_bits_virt_channel_id; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_auto_routers_dest_nodes_in_credit_return; // @[NoC.scala:41:40]
wire [9:0] _router_sink_domain_auto_routers_dest_nodes_in_vc_free; // @[NoC.scala:41:40]
reg [63:0] debug_va_stall_ctr; // @[NoC.scala:163:37]
reg [63:0] debug_sa_stall_ctr; // @[NoC.scala:164:37]
wire [63:0] debug_any_stall_ctr = debug_va_stall_ctr + debug_sa_stall_ctr; // @[NoC.scala:163:37, :164:37, :165:50]
always @(posedge clock) begin // @[NoC.scala:141:9]
if (reset) begin // @[NoC.scala:141:9]
debug_va_stall_ctr <= 64'h0; // @[NoC.scala:163:37]
debug_sa_stall_ctr <= 64'h0; // @[NoC.scala:164:37]
end
else begin // @[NoC.scala:141:9]
debug_va_stall_ctr <=
debug_va_stall_ctr
+ {60'h0,
_router_sink_domain_auto_routers_debug_out_va_stall_0 + _router_sink_domain_auto_routers_debug_out_va_stall_2 + _router_sink_domain_auto_routers_debug_out_va_stall_4 + _router_sink_domain_1_auto_routers_debug_out_va_stall_0 + _router_sink_domain_1_auto_routers_debug_out_va_stall_1 + _router_sink_domain_2_auto_routers_debug_out_va_stall_0 + _router_sink_domain_2_auto_routers_debug_out_va_stall_1 + _router_sink_domain_3_auto_routers_debug_out_va_stall_0 + _router_sink_domain_3_auto_routers_debug_out_va_stall_2 + _router_sink_domain_4_auto_routers_debug_out_va_stall_0 + _router_sink_domain_4_auto_routers_debug_out_va_stall_2 + _router_sink_domain_5_auto_routers_debug_out_va_stall_0 + _router_sink_domain_5_auto_routers_debug_out_va_stall_1 + _router_sink_domain_6_auto_routers_debug_out_va_stall_0 + _router_sink_domain_6_auto_routers_debug_out_va_stall_1 + _router_sink_domain_7_auto_routers_debug_out_va_stall_0 + _router_sink_domain_7_auto_routers_debug_out_va_stall_2 + _router_sink_domain_8_auto_routers_debug_out_va_stall_0 + _router_sink_domain_8_auto_routers_debug_out_va_stall_1 + _router_sink_domain_8_auto_routers_debug_out_va_stall_2 + _router_sink_domain_9_auto_routers_debug_out_va_stall_0 + _router_sink_domain_9_auto_routers_debug_out_va_stall_1 + _router_sink_domain_9_auto_routers_debug_out_va_stall_2 + _router_sink_domain_10_auto_routers_debug_out_va_stall_0 + _router_sink_domain_10_auto_routers_debug_out_va_stall_1 + _router_sink_domain_10_auto_routers_debug_out_va_stall_2 + _router_sink_domain_11_auto_routers_debug_out_va_stall_0 + _router_sink_domain_11_auto_routers_debug_out_va_stall_1 + _router_sink_domain_12_auto_routers_debug_out_va_stall_0 + _router_sink_domain_12_auto_routers_debug_out_va_stall_1 + _router_sink_domain_13_auto_routers_debug_out_va_stall_0 + _router_sink_domain_13_auto_routers_debug_out_va_stall_1 + _router_sink_domain_13_auto_routers_debug_out_va_stall_2 + _router_sink_domain_14_auto_routers_debug_out_va_stall_0 + _router_sink_domain_14_auto_routers_debug_out_va_stall_1
+ _router_sink_domain_14_auto_routers_debug_out_va_stall_2 + _router_sink_domain_15_auto_routers_debug_out_va_stall_0 + _router_sink_domain_15_auto_routers_debug_out_va_stall_1 + _router_sink_domain_15_auto_routers_debug_out_va_stall_2}; // @[NoC.scala:41:40, :163:37, :166:{46,91,104}]
debug_sa_stall_ctr <=
debug_sa_stall_ctr
+ {60'h0,
_router_sink_domain_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_auto_routers_debug_out_sa_stall_4 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_1_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_2_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_3_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_4_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_5_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_6_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_7_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_8_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_9_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_10_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_11_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_12_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_13_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_14_auto_routers_debug_out_sa_stall_1
+ _router_sink_domain_14_auto_routers_debug_out_sa_stall_2 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_0 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_1 + _router_sink_domain_15_auto_routers_debug_out_sa_stall_2}; // @[NoC.scala:41:40, :164:37, :167:{46,91,104}]
end
always @(posedge) |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_80( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_90 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File BankBinder.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
case class BankBinderNode(mask: BigInt)(implicit valName: ValName) extends TLCustomNode
{
private val bit = mask & -mask
val maxXfer = TransferSizes(1, if (bit == 0 || bit > 4096) 4096 else bit.toInt)
val ids = AddressSet.enumerateMask(mask)
def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = {
val ports = ids.size
val oStar = if (oStars == 0) 0 else (ports - oKnown) / oStars
val iStar = if (iStars == 0) 0 else (ports - iKnown) / iStars
require (ports == iKnown + iStar*iStars, s"${name} must have ${ports} inputs, but has ${iKnown} + ${iStar}*${iStars} (at ${lazyModule.line})")
require (ports == oKnown + oStar*oStars, s"${name} must have ${ports} outputs, but has ${oKnown} + ${oStar}*${oStars} (at ${lazyModule.line})")
(iStar, oStar)
}
def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] =
(p zip ids) map { case (cp, id) => cp.v1copy(clients = cp.clients.map { c => c.v1copy(
visibility = c.visibility.flatMap { a => a.intersect(AddressSet(id, ~mask))},
supportsProbe = c.supports.probe intersect maxXfer,
supportsArithmetic = c.supports.arithmetic intersect maxXfer,
supportsLogical = c.supports.logical intersect maxXfer,
supportsGet = c.supports.get intersect maxXfer,
supportsPutFull = c.supports.putFull intersect maxXfer,
supportsPutPartial = c.supports.putPartial intersect maxXfer,
supportsHint = c.supports.hint intersect maxXfer)})}
def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] =
(p zip ids) map { case (mp, id) => mp.v1copy(managers = mp.managers.flatMap { m =>
val addresses = m.address.flatMap(a => a.intersect(AddressSet(id, ~mask)))
if (addresses.nonEmpty)
Some(m.v1copy(
address = addresses,
supportsAcquireT = m.supportsAcquireT intersect maxXfer,
supportsAcquireB = m.supportsAcquireB intersect maxXfer,
supportsArithmetic = m.supportsArithmetic intersect maxXfer,
supportsLogical = m.supportsLogical intersect maxXfer,
supportsGet = m.supportsGet intersect maxXfer,
supportsPutFull = m.supportsPutFull intersect maxXfer,
supportsPutPartial = m.supportsPutPartial intersect maxXfer,
supportsHint = m.supportsHint intersect maxXfer))
else None
})}
}
/* A BankBinder is used to divide contiguous memory regions into banks, suitable for a cache */
class BankBinder(mask: BigInt)(implicit p: Parameters) extends LazyModule
{
val node = BankBinderNode(mask)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
}
}
}
object BankBinder
{
def apply(mask: BigInt)(implicit p: Parameters): TLNode = {
val binder = LazyModule(new BankBinder(mask))
binder.node
}
def apply(nBanks: Int, granularity: Int)(implicit p: Parameters): TLNode = {
if (nBanks > 0) apply(granularity * (nBanks-1))
else TLTempNode()
}
}
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Filter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, RegionType, TransferSizes}
class TLFilter(
mfilter: TLFilter.ManagerFilter = TLFilter.mIdentity,
cfilter: TLFilter.ClientFilter = TLFilter.cIdentity
)(implicit p: Parameters) extends LazyModule
{
val node = new TLAdapterNode(
clientFn = { cp => cp.v1copy(clients = cp.clients.flatMap { c =>
val out = cfilter(c)
out.map { o => // Confirm the filter only REMOVES capability
require (c.sourceId.contains(o.sourceId))
require (c.supports.probe.contains(o.supports.probe))
require (c.supports.arithmetic.contains(o.supports.arithmetic))
require (c.supports.logical.contains(o.supports.logical))
require (c.supports.get.contains(o.supports.get))
require (c.supports.putFull.contains(o.supports.putFull))
require (c.supports.putPartial.contains(o.supports.putPartial))
require (c.supports.hint.contains(o.supports.hint))
require (!c.requestFifo || o.requestFifo)
}
out
})},
managerFn = { mp =>
val managers = mp.managers.flatMap { m =>
val out = mfilter(m)
out.map { o => // Confirm the filter only REMOVES capability
o.address.foreach { a => require (m.address.map(_.contains(a)).reduce(_||_)) }
require (o.regionType <= m.regionType)
// we allow executable to be changed both ways
require (m.supportsAcquireT.contains(o.supportsAcquireT))
require (m.supportsAcquireB.contains(o.supportsAcquireB))
require (m.supportsArithmetic.contains(o.supportsArithmetic))
require (m.supportsLogical.contains(o.supportsLogical))
require (m.supportsGet.contains(o.supportsGet))
require (m.supportsPutFull.contains(o.supportsPutFull))
require (m.supportsPutPartial.contains(o.supportsPutPartial))
require (m.supportsHint.contains(o.supportsHint))
require (!o.fifoId.isDefined || m.fifoId == o.fifoId)
}
out
}
mp.v1copy(managers = managers,
endSinkId = if (managers.exists(_.supportsAcquireB)) mp.endSinkId else 0)
}
) {
override def circuitIdentity = true
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
// In case the inner interface removes Acquire, tie-off the channels
if (!edgeIn.manager.anySupportAcquireB) {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFilter
{
type ManagerFilter = TLSlaveParameters => Option[TLSlaveParameters]
type ClientFilter = TLMasterParameters => Option[TLMasterParameters]
// preserve manager visibility
def mIdentity: ManagerFilter = { m => Some(m) }
// preserve client visibility
def cIdentity: ClientFilter = { c => Some(c) }
// make only the intersected address sets visible
def mSelectIntersect(select: AddressSet): ManagerFilter = { m =>
val filtered = m.address.map(_.intersect(select)).flatten
val alignment = select.alignment /* alignment 0 means 'select' selected everything */
transferSizeHelper(m, filtered, alignment)
}
// make everything except the intersected address sets visible
def mSubtract(excepts: Seq[AddressSet]): ManagerFilter = { m =>
val filtered = excepts.foldLeft(m.address) { (a,e) => a.flatMap(_.subtract(e)) }
val alignment: BigInt = if (filtered.isEmpty) 0 else filtered.map(_.alignment).min
transferSizeHelper(m, filtered, alignment)
}
def mSubtract(except: AddressSet): ManagerFilter = { m =>
mSubtract(Seq(except))(m)
}
// adjust supported transfer sizes based on filtered intersection
private def transferSizeHelper(m: TLSlaveParameters, filtered: Seq[AddressSet], alignment: BigInt): Option[TLSlaveParameters] = {
val maxTransfer = 1 << 30
val capTransfer = if (alignment == 0 || alignment > maxTransfer) maxTransfer else alignment.toInt
val cap = TransferSizes(1, capTransfer)
if (filtered.isEmpty) { None } else {
Some(m.v1copy(
address = filtered,
supportsAcquireT = m.supportsAcquireT .intersect(cap),
supportsAcquireB = m.supportsAcquireB .intersect(cap),
supportsArithmetic = m.supportsArithmetic.intersect(cap),
supportsLogical = m.supportsLogical .intersect(cap),
supportsGet = m.supportsGet .intersect(cap),
supportsPutFull = m.supportsPutFull .intersect(cap),
supportsPutPartial = m.supportsPutPartial.intersect(cap),
supportsHint = m.supportsHint .intersect(cap)))
}
}
// hide any fully contained address sets
def mHideContained(containedBy: AddressSet): ManagerFilter = { m =>
val filtered = m.address.filterNot(containedBy.contains(_))
if (filtered.isEmpty) None else Some(m.v1copy(address = filtered))
}
// hide all cacheable managers
def mHideCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) None else Some(m)
}
// make visible only cacheable managers
def mSelectCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) Some(m) else None
}
// cacheable managers cannot be acquired from
def mMaskCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) {
Some(m.v1copy(
regionType = RegionType.UNCACHED,
supportsAcquireB = TransferSizes.none,
supportsAcquireT = TransferSizes.none,
alwaysGrantsT = false))
} else { Some(m) }
}
// only cacheable managers are visible, but cannot be acquired from
def mSelectAndMaskCacheable: ManagerFilter = { m =>
if (m.supportsAcquireB) {
Some(m.v1copy(
regionType = RegionType.UNCACHED,
supportsAcquireB = TransferSizes.none,
supportsAcquireT = TransferSizes.none,
alwaysGrantsT = false))
} else { None }
}
// hide all caching clients
def cHideCaching: ClientFilter = { c =>
if (c.supports.probe) None else Some(c)
}
// onyl caching clients are visible
def cSelectCaching: ClientFilter = { c =>
if (c.supports.probe) Some(c) else None
}
// removes resources from managers
def mResourceRemover: ManagerFilter = { m =>
Some(m.v2copy(resources=Nil))
}
// default application applies neither type of filter unless overridden
def apply(
mfilter: ManagerFilter = TLFilter.mIdentity,
cfilter: ClientFilter = TLFilter.cIdentity
)(implicit p: Parameters): TLNode =
{
val filter = LazyModule(new TLFilter(mfilter, cfilter))
filter.node
}
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File Jbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
class TLJbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) extends LazyModule
{
val node: TLJunctionNode = new TLJunctionNode(
clientFn = { seq =>
Seq.fill(node.dRatio)(seq(0).v1copy(
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
))
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
Seq.fill(node.uRatio)(seq(0).v1copy(
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
))
}) {
override def circuitIdentity = uRatio == 1 && dRatio == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
node.inoutGrouped.foreach { case (in, out) => TLXbar.circuit(policy, in, out) }
}
}
object TLJbar
{
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters) = {
val jbar = LazyModule(new TLJbar(policy))
jbar.node
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLJbarTestImp(nClients: Int, nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val jbar = LazyModule(new TLJbar)
val fuzzers = Seq.fill(nClients) {
val fuzzer = LazyModule(new TLFuzzer(txns))
jbar.node :*= TLXbar() := TLDelayer(0.1) := fuzzer.node
fuzzer
}
for (n <- 0 until nManagers) {
TLRAM(AddressSet(0x0+0x400*n, 0x3ff)) := TLFragmenter(4, 256) := TLDelayer(0.1) := jbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.map(_.module.io.finished).reduce(_ && _)
}
}
class TLJbarTest(nClients: Int, nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLJbarTestImp(nClients, nManagers, txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File ClockGroup.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.resources.FixedClockResource
case class ClockGroupingNode(groupName: String)(implicit valName: ValName)
extends MixedNexusNode(ClockGroupImp, ClockImp)(
dFn = { _ => ClockSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) })
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupingNode(groupName)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
require (node.in.size == 1)
require (in.member.size == out.size)
(in.member.data zip out) foreach { case (i, o) => o := i }
}
}
object ClockGroup
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node
}
case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))})
{
override def circuitIdentity = outputs.size == 1
}
class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupAggregateNode(groupName)
override lazy val desiredName = s"ClockGroupAggregator_$groupName"
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in.unzip
val (out, _) = node.out.unzip
val outputs = out.flatMap(_.member.data)
require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1")
require (in.head.member.size == outputs.size)
in.head.member.data.zip(outputs).foreach { case (i, o) => o := i }
}
}
object ClockGroupAggregator
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node
}
class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule
{
val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
val (out, _) = node.out.unzip
out.map { out: ClockGroupBundle =>
out.member.data.foreach { o =>
o.clock := clock; o.reset := reset }
}
}
}
object SimpleClockGroupSource
{
def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node
}
case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName)
extends NexusNode(ClockImp)(
dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) },
uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) },
inputRequiresOutput = false) {
def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix)))
}
class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule
{
val node = new FixedClockBroadcastNode(fixedClockOpt) {
override def circuitIdentity = outputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val (in, _) = node.in(0)
val (out, _) = node.out.unzip
override def desiredName = s"FixedClockBroadcast_${out.size}"
require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock")
out.foreach { _ := in }
}
}
object FixedClockBroadcast
{
def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node
}
case class PRCIClockGroupNode()(implicit valName: ValName)
extends NexusNode(ClockGroupImp)(
dFn = { _ => ClockGroupSourceParameters() },
uFn = { _ => ClockGroupSinkParameters("prci", Nil) },
outputRequiresInput = false)
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Configs.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package freechips.rocketchip.subsystem
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import sifive.blocks.inclusivecache._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util._
import sifive.blocks.inclusivecache.InclusiveCacheParameters
case class InclusiveCacheParams(
ways: Int,
sets: Int,
writeBytes: Int, // backing store update granularity
portFactor: Int, // numSubBanks = (widest TL port * portFactor) / writeBytes
memCycles: Int, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
physicalFilter: Option[PhysicalFilterParams] = None,
hintsSkipProbe: Boolean = false, // do hints probe the same client
bankedControl: Boolean = false, // bank the cache ctrl with the cache banks
ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress),
// Interior/Exterior refer to placement either inside the Scheduler or outside it
// Inner/Outer refer to buffers on the front (towards cores) or back (towards DDR) of the L2
bufInnerInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC,
bufInnerExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.flowAD,
bufOuterInterior: InclusiveCachePortParameters = InclusiveCachePortParameters.full,
bufOuterExterior: InclusiveCachePortParameters = InclusiveCachePortParameters.none)
case object InclusiveCacheKey extends Field[InclusiveCacheParams]
class WithInclusiveCache(
nWays: Int = 8,
capacityKB: Int = 512,
outerLatencyCycles: Int = 40,
subBankingFactor: Int = 4,
hintsSkipProbe: Boolean = false,
bankedControl: Boolean = false,
ctrlAddr: Option[Int] = Some(InclusiveCacheParameters.L2ControlAddress),
writeBytes: Int = 8
) extends Config((site, here, up) => {
case InclusiveCacheKey => InclusiveCacheParams(
sets = (capacityKB * 1024)/(site(CacheBlockBytes) * nWays * up(SubsystemBankedCoherenceKey, site).nBanks),
ways = nWays,
memCycles = outerLatencyCycles,
writeBytes = writeBytes,
portFactor = subBankingFactor,
hintsSkipProbe = hintsSkipProbe,
bankedControl = bankedControl,
ctrlAddr = ctrlAddr)
case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = { context =>
implicit val p = context.p
val sbus = context.tlBusWrapperLocationMap(SBUS)
val cbus = context.tlBusWrapperLocationMap.lift(CBUS).getOrElse(sbus)
val InclusiveCacheParams(
ways,
sets,
writeBytes,
portFactor,
memCycles,
physicalFilter,
hintsSkipProbe,
bankedControl,
ctrlAddr,
bufInnerInterior,
bufInnerExterior,
bufOuterInterior,
bufOuterExterior) = p(InclusiveCacheKey)
val l2Ctrl = ctrlAddr.map { addr =>
InclusiveCacheControlParameters(
address = addr,
beatBytes = cbus.beatBytes,
bankedControl = bankedControl)
}
val l2 = LazyModule(new InclusiveCache(
CacheParameters(
level = 2,
ways = ways,
sets = sets,
blockBytes = sbus.blockBytes,
beatBytes = sbus.beatBytes,
hintsSkipProbe = hintsSkipProbe),
InclusiveCacheMicroParameters(
writeBytes = writeBytes,
portFactor = portFactor,
memCycles = memCycles,
innerBuf = bufInnerInterior,
outerBuf = bufOuterInterior),
l2Ctrl))
def skipMMIO(x: TLClientParameters) = {
val dcacheMMIO =
x.requestFifo &&
x.sourceId.start % 2 == 1 && // 1 => dcache issues acquires from another master
x.nodePath.last.name == "dcache.node"
if (dcacheMMIO) None else Some(x)
}
val filter = LazyModule(new TLFilter(cfilter = skipMMIO))
val l2_inner_buffer = bufInnerExterior()
val l2_outer_buffer = bufOuterExterior()
val cork = LazyModule(new TLCacheCork)
val lastLevelNode = cork.node
l2_inner_buffer.suggestName("InclusiveCache_inner_TLBuffer")
l2_outer_buffer.suggestName("InclusiveCache_outer_TLBuffer")
l2_inner_buffer.node :*= filter.node
l2.node :*= l2_inner_buffer.node
l2_outer_buffer.node :*= l2.node
/* PhysicalFilters need to be on the TL-C side of a CacheCork to prevent Acquire.NtoB -> Grant.toT */
physicalFilter match {
case None => lastLevelNode :*= l2_outer_buffer.node
case Some(fp) => {
val physicalFilter = LazyModule(new PhysicalFilter(fp.copy(controlBeatBytes = cbus.beatBytes)))
lastLevelNode :*= physicalFilter.node :*= l2_outer_buffer.node
physicalFilter.controlNode := cbus.coupleTo("physical_filter") {
TLBuffer(1) := TLFragmenter(cbus, Some("LLCPhysicalFilter")) := _
}
}
}
l2.ctrls.foreach {
_.ctrlnode := cbus.coupleTo("l2_ctrl") { TLBuffer(1) := TLFragmenter(cbus, Some("LLCCtrl")) := _ }
}
ElaborationArtefacts.add("l2.json", l2.module.json)
(filter.node, lastLevelNode, None)
})
})
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
| module CoherenceManagerWrapper( // @[ClockDomain.scala:14:9]
input auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coherent_jbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_coherent_jbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_coherent_jbar_anon_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_coherent_jbar_anon_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_coherent_jbar_anon_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_coherent_jbar_anon_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_coherent_jbar_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_coherent_jbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_coherent_jbar_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_coherent_jbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_coherent_jbar_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_coherent_jbar_anon_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_coherent_jbar_anon_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_l2_ctrls_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_l2_ctrls_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_l2_ctrls_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [25:0] auto_l2_ctrls_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_l2_ctrls_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_l2_ctrls_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_l2_ctrls_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_l2_ctrls_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_l2_ctrls_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_l2_ctrls_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_clock, // @[LazyModuleImp.scala:107:25]
input auto_coh_clock_groups_in_member_coh_0_reset // @[LazyModuleImp.scala:107:25]
);
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_d_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_in_d_bits_denied; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_sink; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_size; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_d_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_b_bits_address; // @[Filter.scala:60:9]
wire [1:0] filter_auto_anon_in_b_bits_param; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_ready; // @[Filter.scala:60:9]
wire filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9]
wire coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire _binder_auto_in_a_ready; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_valid; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_opcode; // @[BankBinder.scala:71:28]
wire [1:0] _binder_auto_in_d_bits_param; // @[BankBinder.scala:71:28]
wire [2:0] _binder_auto_in_d_bits_size; // @[BankBinder.scala:71:28]
wire [3:0] _binder_auto_in_d_bits_source; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_sink; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_denied; // @[BankBinder.scala:71:28]
wire [63:0] _binder_auto_in_d_bits_data; // @[BankBinder.scala:71:28]
wire _binder_auto_in_d_bits_corrupt; // @[BankBinder.scala:71:28]
wire _cork_auto_out_a_valid; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_opcode; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_param; // @[Configs.scala:120:26]
wire [2:0] _cork_auto_out_a_bits_size; // @[Configs.scala:120:26]
wire [3:0] _cork_auto_out_a_bits_source; // @[Configs.scala:120:26]
wire [31:0] _cork_auto_out_a_bits_address; // @[Configs.scala:120:26]
wire [7:0] _cork_auto_out_a_bits_mask; // @[Configs.scala:120:26]
wire [63:0] _cork_auto_out_a_bits_data; // @[Configs.scala:120:26]
wire _cork_auto_out_a_bits_corrupt; // @[Configs.scala:120:26]
wire _cork_auto_out_d_ready; // @[Configs.scala:120:26]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_size; // @[Parameters.scala:56:69]
wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_address; // @[Parameters.scala:56:69]
wire [7:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_a_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_b_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_param; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_size; // @[Parameters.scala:56:69]
wire [5:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_source; // @[Parameters.scala:56:69]
wire [31:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_address; // @[Parameters.scala:56:69]
wire [63:0] _InclusiveCache_inner_TLBuffer_auto_out_c_bits_data; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_d_ready; // @[Parameters.scala:56:69]
wire _InclusiveCache_inner_TLBuffer_auto_out_e_valid; // @[Parameters.scala:56:69]
wire [2:0] _InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink; // @[Parameters.scala:56:69]
wire _l2_auto_in_a_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_b_valid; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_b_bits_param; // @[Configs.scala:93:24]
wire [31:0] _l2_auto_in_b_bits_address; // @[Configs.scala:93:24]
wire _l2_auto_in_c_ready; // @[Configs.scala:93:24]
wire _l2_auto_in_d_valid; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_opcode; // @[Configs.scala:93:24]
wire [1:0] _l2_auto_in_d_bits_param; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_size; // @[Configs.scala:93:24]
wire [5:0] _l2_auto_in_d_bits_source; // @[Configs.scala:93:24]
wire [2:0] _l2_auto_in_d_bits_sink; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_denied; // @[Configs.scala:93:24]
wire [63:0] _l2_auto_in_d_bits_data; // @[Configs.scala:93:24]
wire _l2_auto_in_d_bits_corrupt; // @[Configs.scala:93:24]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_valid_0 = auto_coherent_jbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_opcode_0 = auto_coherent_jbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_param_0 = auto_coherent_jbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_a_bits_size_0 = auto_coherent_jbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_a_bits_source_0 = auto_coherent_jbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_a_bits_address_0 = auto_coherent_jbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coherent_jbar_anon_in_a_bits_mask_0 = auto_coherent_jbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_a_bits_data_0 = auto_coherent_jbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_bits_corrupt_0 = auto_coherent_jbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_ready_0 = auto_coherent_jbar_anon_in_b_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_valid_0 = auto_coherent_jbar_anon_in_c_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_opcode_0 = auto_coherent_jbar_anon_in_c_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_param_0 = auto_coherent_jbar_anon_in_c_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_c_bits_size_0 = auto_coherent_jbar_anon_in_c_bits_size; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_c_bits_source_0 = auto_coherent_jbar_anon_in_c_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_c_bits_address_0 = auto_coherent_jbar_anon_in_c_bits_address; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_c_bits_data_0 = auto_coherent_jbar_anon_in_c_bits_data; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_bits_corrupt_0 = auto_coherent_jbar_anon_in_c_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_ready_0 = auto_coherent_jbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_e_valid_0 = auto_coherent_jbar_anon_in_e_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_e_bits_sink_0 = auto_coherent_jbar_anon_in_e_bits_sink; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_valid_0 = auto_l2_ctrls_ctrl_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_opcode_0 = auto_l2_ctrls_ctrl_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_a_bits_param_0 = auto_l2_ctrls_ctrl_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_a_bits_size_0 = auto_l2_ctrls_ctrl_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [10:0] auto_l2_ctrls_ctrl_in_a_bits_source_0 = auto_l2_ctrls_ctrl_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [25:0] auto_l2_ctrls_ctrl_in_a_bits_address_0 = auto_l2_ctrls_ctrl_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_l2_ctrls_ctrl_in_a_bits_mask_0 = auto_l2_ctrls_ctrl_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_a_bits_data_0 = auto_l2_ctrls_ctrl_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_bits_corrupt_0 = auto_l2_ctrls_ctrl_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_ready_0 = auto_l2_ctrls_ctrl_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_clock_0 = auto_coh_clock_groups_in_member_coh_0_clock; // @[ClockDomain.scala:14:9]
wire auto_coh_clock_groups_in_member_coh_0_reset_0 = auto_coh_clock_groups_in_member_coh_0_reset; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_opcode = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_b_bits_size = 3'h6; // @[ClockDomain.scala:14:9]
wire [2:0] filter_auto_anon_in_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_in_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_opcode = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_b_bits_size = 3'h6; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_opcode = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_out_b_bits_size = 3'h6; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_b_bits_opcode = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonOut_b_bits_size = 3'h6; // @[MixedNode.scala:542:17]
wire [2:0] coherent_jbar_anonIn_b_bits_opcode = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_anonIn_b_bits_size = 3'h6; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_in_0_b_bits_opcode = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_b_bits_size = 3'h6; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_out_0_b_bits_opcode = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_b_bits_size = 3'h6; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_opcode = 3'h6; // @[Xbar.scala:352:24]
wire [2:0] coherent_jbar_portsBIO_filtered_0_bits_size = 3'h6; // @[Xbar.scala:352:24]
wire [5:0] auto_coherent_jbar_anon_in_b_bits_source = 6'h21; // @[ClockDomain.scala:14:9]
wire [5:0] filter_auto_anon_in_b_bits_source = 6'h21; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_b_bits_source = 6'h21; // @[Filter.scala:60:9]
wire [5:0] filter_anonOut_b_bits_source = 6'h21; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonIn_b_bits_source = 6'h21; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_auto_anon_in_b_bits_source = 6'h21; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_out_b_bits_source = 6'h21; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_b_bits_source = 6'h21; // @[MixedNode.scala:542:17]
wire [5:0] coherent_jbar_anonIn_b_bits_source = 6'h21; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_in_0_b_bits_source = 6'h21; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__anonIn_b_bits_source_T = 6'h21; // @[Xbar.scala:156:69]
wire [5:0] coherent_jbar_out_0_b_bits_source = 6'h21; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar__requestBOI_uncommonBits_T = 6'h21; // @[Parameters.scala:52:29]
wire [5:0] coherent_jbar_requestBOI_uncommonBits = 6'h21; // @[Parameters.scala:52:56]
wire [5:0] coherent_jbar_portsBIO_filtered_0_bits_source = 6'h21; // @[Xbar.scala:352:24]
wire [7:0] auto_coherent_jbar_anon_in_b_bits_mask = 8'hFF; // @[ClockDomain.scala:14:9]
wire [7:0] filter_auto_anon_in_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_b_bits_mask = 8'hFF; // @[Filter.scala:60:9]
wire [7:0] filter_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_auto_anon_in_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_out_b_bits_mask = 8'hFF; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_b_bits_mask = 8'hFF; // @[MixedNode.scala:542:17]
wire [7:0] coherent_jbar_anonIn_b_bits_mask = 8'hFF; // @[MixedNode.scala:551:17]
wire [7:0] coherent_jbar_in_0_b_bits_mask = 8'hFF; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_out_0_b_bits_mask = 8'hFF; // @[Xbar.scala:216:19]
wire [7:0] coherent_jbar_portsBIO_filtered_0_bits_mask = 8'hFF; // @[Xbar.scala:352:24]
wire [63:0] auto_coherent_jbar_anon_in_b_bits_data = 64'h0; // @[ClockDomain.scala:14:9]
wire [63:0] filter_auto_anon_in_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_b_bits_data = 64'h0; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_data = 64'h0; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_in_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_out_b_bits_data = 64'h0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_b_bits_data = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] coherent_jbar_anonIn_b_bits_data = 64'h0; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_in_0_b_bits_data = 64'h0; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_out_0_b_bits_data = 64'h0; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_b_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire coh_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire coh_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire fixedClockNode_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire fixedClockNode_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire fixedClockNode__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire filter_auto_anon_in_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_bits_corrupt = 1'h0; // @[Filter.scala:60:9]
wire filter_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire filter_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_valid = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_valid = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_valid = 1'h0; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_b_bits_corrupt = 1'h0; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_b_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_b_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire coherent_jbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire coherent_jbar_beatsBO_opdata = 1'h0; // @[Edges.scala:97:28]
wire coherent_jbar_portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire auto_coherent_jbar_anon_in_e_ready = 1'h1; // @[ClockDomain.scala:14:9]
wire filter_auto_anon_in_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_ready = 1'h1; // @[Filter.scala:60:9]
wire filter_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire filter_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_auto_in_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_b_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_ready = 1'h1; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_b_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_b_ready = 1'h1; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_in_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_ready = 1'h1; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_ready = 1'h1; // @[MixedNode.scala:542:17]
wire coherent_jbar_anonIn_e_ready = 1'h1; // @[MixedNode.scala:551:17]
wire coherent_jbar_in_0_e_ready = 1'h1; // @[Xbar.scala:159:18]
wire coherent_jbar_out_0_e_ready = 1'h1; // @[Xbar.scala:216:19]
wire coherent_jbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire coherent_jbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire coherent_jbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire coherent_jbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire coherent_jbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire coherent_jbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire coherent_jbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire coherent_jbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire coherent_jbar__beatsBO_opdata_T = 1'h1; // @[Edges.scala:97:37]
wire coherent_jbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire coherent_jbar_portsEOI_filtered_0_ready = 1'h1; // @[Xbar.scala:352:24]
wire coherent_jbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_param = 2'h0; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_param = 2'h0; // @[MixedNode.scala:542:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_param = 2'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_opcode = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_size = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_source = 3'h0; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_opcode = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_size = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_source = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_opcode = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_size = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_source = 3'h0; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_beatsBO_0 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] coherent_jbar_beatsBO_decode = 3'h7; // @[Edges.scala:220:59]
wire [5:0] coherent_jbar__beatsBO_decode_T_2 = 6'h3F; // @[package.scala:243:46]
wire [5:0] coherent_jbar__beatsBO_decode_T_1 = 6'h0; // @[package.scala:243:76]
wire [12:0] coherent_jbar__beatsBO_decode_T = 13'hFC0; // @[package.scala:243:71]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_address = 32'h0; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_address = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_address = 32'h0; // @[MixedNode.scala:551:17]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_in_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_b_bits_mask = 8'h0; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_b_bits_mask = 8'h0; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_b_bits_mask = 8'h0; // @[MixedNode.scala:551:17]
wire [32:0] coherent_jbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] coherent_jbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire coherent_jbar_auto_anon_in_a_valid = auto_coherent_jbar_anon_in_a_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_opcode = auto_coherent_jbar_anon_in_a_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_param = auto_coherent_jbar_anon_in_a_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_a_bits_size = auto_coherent_jbar_anon_in_a_bits_size_0; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_a_bits_source = auto_coherent_jbar_anon_in_a_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_a_bits_address = auto_coherent_jbar_anon_in_a_bits_address_0; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_auto_anon_in_a_bits_mask = auto_coherent_jbar_anon_in_a_bits_mask_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_a_bits_data = auto_coherent_jbar_anon_in_a_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_a_bits_corrupt = auto_coherent_jbar_anon_in_a_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_ready = auto_coherent_jbar_anon_in_b_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_valid = auto_coherent_jbar_anon_in_c_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_opcode = auto_coherent_jbar_anon_in_c_bits_opcode_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_param = auto_coherent_jbar_anon_in_c_bits_param_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_c_bits_size = auto_coherent_jbar_anon_in_c_bits_size_0; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_c_bits_source = auto_coherent_jbar_anon_in_c_bits_source_0; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_auto_anon_in_c_bits_address = auto_coherent_jbar_anon_in_c_bits_address_0; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_c_bits_data = auto_coherent_jbar_anon_in_c_bits_data_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_c_bits_corrupt = auto_coherent_jbar_anon_in_c_bits_corrupt_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_ready = auto_coherent_jbar_anon_in_d_ready_0; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_in_e_valid = auto_coherent_jbar_anon_in_e_valid_0; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_auto_anon_in_e_bits_sink = auto_coherent_jbar_anon_in_e_bits_sink_0; // @[Jbar.scala:44:9]
wire coh_clock_groups_auto_in_member_coh_0_clock = auto_coh_clock_groups_in_member_coh_0_clock_0; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_auto_in_member_coh_0_reset = auto_coh_clock_groups_in_member_coh_0_reset_0; // @[ClockGroup.scala:53:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
wire [3:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
wire [7:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
wire [31:0] auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [5:0] auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
wire auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [1:0] auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [10:0] auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
wire coh_clock_groups_nodeIn_member_coh_0_clock = coh_clock_groups_auto_in_member_coh_0_clock; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_clock; // @[MixedNode.scala:542:17]
wire coh_clock_groups_nodeIn_member_coh_0_reset = coh_clock_groups_auto_in_member_coh_0_reset; // @[ClockGroup.scala:53:9]
wire coh_clock_groups_nodeOut_member_coh_0_reset; // @[MixedNode.scala:542:17]
wire clockGroup_auto_in_member_coh_0_clock = coh_clock_groups_auto_out_member_coh_0_clock; // @[ClockGroup.scala:24:9, :53:9]
wire clockGroup_auto_in_member_coh_0_reset = coh_clock_groups_auto_out_member_coh_0_reset; // @[ClockGroup.scala:24:9, :53:9]
assign coh_clock_groups_auto_out_member_coh_0_clock = coh_clock_groups_nodeOut_member_coh_0_clock; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_auto_out_member_coh_0_reset = coh_clock_groups_nodeOut_member_coh_0_reset; // @[ClockGroup.scala:53:9]
assign coh_clock_groups_nodeOut_member_coh_0_clock = coh_clock_groups_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign coh_clock_groups_nodeOut_member_coh_0_reset = coh_clock_groups_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire clockGroup_nodeIn_member_coh_0_clock = clockGroup_auto_in_member_coh_0_clock; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17]
wire clockGroup_nodeIn_member_coh_0_reset = clockGroup_auto_in_member_coh_0_reset; // @[ClockGroup.scala:24:9]
wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17]
wire fixedClockNode_auto_anon_in_clock = clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9, :104:9]
wire fixedClockNode_auto_anon_in_reset = clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9, :104:9]
assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9]
assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9]
assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_coh_0_clock; // @[MixedNode.scala:542:17, :551:17]
assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_coh_0_reset; // @[MixedNode.scala:542:17, :551:17]
wire fixedClockNode_anonIn_clock = fixedClockNode_auto_anon_in_clock; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_clock; // @[MixedNode.scala:542:17]
wire fixedClockNode_anonIn_reset = fixedClockNode_auto_anon_in_reset; // @[ClockGroup.scala:104:9]
wire fixedClockNode_anonOut_reset; // @[MixedNode.scala:542:17]
assign clockSinkNodeIn_clock = fixedClockNode_auto_anon_out_clock; // @[ClockGroup.scala:104:9]
assign clockSinkNodeIn_reset = fixedClockNode_auto_anon_out_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_clock = fixedClockNode_anonOut_clock; // @[ClockGroup.scala:104:9]
assign fixedClockNode_auto_anon_out_reset = fixedClockNode_anonOut_reset; // @[ClockGroup.scala:104:9]
assign fixedClockNode_anonOut_clock = fixedClockNode_anonIn_clock; // @[MixedNode.scala:542:17, :551:17]
assign fixedClockNode_anonOut_reset = fixedClockNode_anonIn_reset; // @[MixedNode.scala:542:17, :551:17]
wire filter_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_a_ready = filter_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_a_valid = filter_auto_anon_in_a_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_opcode = filter_auto_anon_in_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_param = filter_auto_anon_in_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_a_bits_size = filter_auto_anon_in_a_bits_size; // @[Filter.scala:60:9]
wire [5:0] coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_a_bits_source = filter_auto_anon_in_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_a_bits_address = filter_auto_anon_in_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [7:0] filter_anonIn_a_bits_mask = filter_auto_anon_in_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_a_bits_data = filter_auto_anon_in_a_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_a_bits_corrupt = filter_auto_anon_in_a_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_b_ready = filter_auto_anon_in_b_ready; // @[Filter.scala:60:9]
wire filter_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_b_valid = filter_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_b_bits_param = filter_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] coherent_jbar_auto_anon_out_b_bits_address = filter_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire filter_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_c_ready = filter_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_c_valid = filter_auto_anon_in_c_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_opcode = filter_auto_anon_in_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_param = filter_auto_anon_in_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_c_bits_size = filter_auto_anon_in_c_bits_size; // @[Filter.scala:60:9]
wire [5:0] coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_c_bits_source = filter_auto_anon_in_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [31:0] filter_anonIn_c_bits_address = filter_auto_anon_in_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_c_bits_data = filter_auto_anon_in_c_bits_data; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire filter_anonIn_c_bits_corrupt = filter_auto_anon_in_c_bits_corrupt; // @[Filter.scala:60:9]
wire coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire filter_anonIn_d_ready = filter_auto_anon_in_d_ready; // @[Filter.scala:60:9]
wire filter_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] filter_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_valid = filter_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [1:0] filter_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_opcode = filter_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] coherent_jbar_auto_anon_out_d_bits_param = filter_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [5:0] filter_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_size = filter_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [5:0] coherent_jbar_auto_anon_out_d_bits_source = filter_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] coherent_jbar_auto_anon_out_d_bits_sink = filter_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire [63:0] filter_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire coherent_jbar_auto_anon_out_d_bits_denied = filter_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire filter_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] coherent_jbar_auto_anon_out_d_bits_data = filter_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_d_bits_corrupt = filter_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire filter_anonIn_e_valid = filter_auto_anon_in_e_valid; // @[Filter.scala:60:9]
wire [2:0] coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire [2:0] filter_anonIn_e_bits_sink = filter_auto_anon_in_e_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_a_ready = filter_auto_anon_out_a_ready; // @[Filter.scala:60:9]
wire filter_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] filter_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_b_valid = filter_auto_anon_out_b_valid; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_b_bits_param = filter_auto_anon_out_b_bits_param; // @[Filter.scala:60:9]
wire [31:0] filter_anonOut_b_bits_address = filter_auto_anon_out_b_bits_address; // @[Filter.scala:60:9]
wire filter_anonOut_c_ready = filter_auto_anon_out_c_ready; // @[Filter.scala:60:9]
wire filter_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [5:0] filter_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] filter_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] filter_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire filter_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire filter_anonOut_d_valid = filter_auto_anon_out_d_valid; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_opcode = filter_auto_anon_out_d_bits_opcode; // @[Filter.scala:60:9]
wire [1:0] filter_anonOut_d_bits_param = filter_auto_anon_out_d_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_size = filter_auto_anon_out_d_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_anonOut_d_bits_source = filter_auto_anon_out_d_bits_source; // @[Filter.scala:60:9]
wire [2:0] filter_anonOut_d_bits_sink = filter_auto_anon_out_d_bits_sink; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_denied = filter_auto_anon_out_d_bits_denied; // @[Filter.scala:60:9]
wire [63:0] filter_anonOut_d_bits_data = filter_auto_anon_out_d_bits_data; // @[Filter.scala:60:9]
wire filter_anonOut_d_bits_corrupt = filter_auto_anon_out_d_bits_corrupt; // @[Filter.scala:60:9]
wire filter_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] filter_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] filter_auto_anon_out_a_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_a_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_a_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_a_bits_address; // @[Filter.scala:60:9]
wire [7:0] filter_auto_anon_out_a_bits_mask; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_a_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_a_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_b_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_opcode; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_param; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_c_bits_size; // @[Filter.scala:60:9]
wire [5:0] filter_auto_anon_out_c_bits_source; // @[Filter.scala:60:9]
wire [31:0] filter_auto_anon_out_c_bits_address; // @[Filter.scala:60:9]
wire [63:0] filter_auto_anon_out_c_bits_data; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_bits_corrupt; // @[Filter.scala:60:9]
wire filter_auto_anon_out_c_valid; // @[Filter.scala:60:9]
wire filter_auto_anon_out_d_ready; // @[Filter.scala:60:9]
wire [2:0] filter_auto_anon_out_e_bits_sink; // @[Filter.scala:60:9]
wire filter_auto_anon_out_e_valid; // @[Filter.scala:60:9]
assign filter_anonIn_a_ready = filter_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_a_valid = filter_anonOut_a_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_opcode = filter_anonOut_a_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_param = filter_anonOut_a_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_size = filter_anonOut_a_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_source = filter_anonOut_a_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_address = filter_anonOut_a_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_mask = filter_anonOut_a_bits_mask; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_data = filter_anonOut_a_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_a_bits_corrupt = filter_anonOut_a_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_b_ready = filter_anonOut_b_ready; // @[Filter.scala:60:9]
assign filter_anonIn_b_valid = filter_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_param = filter_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_b_bits_address = filter_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_c_ready = filter_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_c_valid = filter_anonOut_c_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_opcode = filter_anonOut_c_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_param = filter_anonOut_c_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_size = filter_anonOut_c_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_source = filter_anonOut_c_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_address = filter_anonOut_c_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_data = filter_anonOut_c_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_out_c_bits_corrupt = filter_anonOut_c_bits_corrupt; // @[Filter.scala:60:9]
assign filter_auto_anon_out_d_ready = filter_anonOut_d_ready; // @[Filter.scala:60:9]
assign filter_anonIn_d_valid = filter_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_opcode = filter_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_param = filter_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_size = filter_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_source = filter_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_sink = filter_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_denied = filter_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_data = filter_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonIn_d_bits_corrupt = filter_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_out_e_valid = filter_anonOut_e_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_out_e_bits_sink = filter_anonOut_e_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_a_ready = filter_anonIn_a_ready; // @[Filter.scala:60:9]
assign filter_anonOut_a_valid = filter_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_opcode = filter_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_param = filter_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_size = filter_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_source = filter_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_address = filter_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_mask = filter_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_data = filter_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_a_bits_corrupt = filter_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_b_ready = filter_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_b_valid = filter_anonIn_b_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_param = filter_anonIn_b_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_b_bits_address = filter_anonIn_b_bits_address; // @[Filter.scala:60:9]
assign filter_auto_anon_in_c_ready = filter_anonIn_c_ready; // @[Filter.scala:60:9]
assign filter_anonOut_c_valid = filter_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_opcode = filter_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_param = filter_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_size = filter_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_source = filter_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_address = filter_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_data = filter_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_c_bits_corrupt = filter_anonIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_d_ready = filter_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign filter_auto_anon_in_d_valid = filter_anonIn_d_valid; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_opcode = filter_anonIn_d_bits_opcode; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_param = filter_anonIn_d_bits_param; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_size = filter_anonIn_d_bits_size; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_source = filter_anonIn_d_bits_source; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_sink = filter_anonIn_d_bits_sink; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_denied = filter_anonIn_d_bits_denied; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_data = filter_anonIn_d_bits_data; // @[Filter.scala:60:9]
assign filter_auto_anon_in_d_bits_corrupt = filter_anonIn_d_bits_corrupt; // @[Filter.scala:60:9]
assign filter_anonOut_e_valid = filter_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign filter_anonOut_e_bits_sink = filter_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_valid = InclusiveCache_outer_TLBuffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param = InclusiveCache_outer_TLBuffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size = InclusiveCache_outer_TLBuffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source = InclusiveCache_outer_TLBuffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address = InclusiveCache_outer_TLBuffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask = InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data = InclusiveCache_outer_TLBuffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_valid = InclusiveCache_outer_TLBuffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode = InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param = InclusiveCache_outer_TLBuffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size = InclusiveCache_outer_TLBuffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source = InclusiveCache_outer_TLBuffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address = InclusiveCache_outer_TLBuffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data = InclusiveCache_outer_TLBuffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_ready = InclusiveCache_outer_TLBuffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire InclusiveCache_outer_TLBuffer_nodeIn_e_valid = InclusiveCache_outer_TLBuffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink = InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_ready = InclusiveCache_outer_TLBuffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_ready = InclusiveCache_outer_TLBuffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_valid = InclusiveCache_outer_TLBuffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode = InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param = InclusiveCache_outer_TLBuffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size = InclusiveCache_outer_TLBuffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source = InclusiveCache_outer_TLBuffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink = InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied = InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data = InclusiveCache_outer_TLBuffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt = InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire InclusiveCache_outer_TLBuffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] InclusiveCache_outer_TLBuffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire [2:0] InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire InclusiveCache_outer_TLBuffer_auto_out_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_a_ready = InclusiveCache_outer_TLBuffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_a_valid = InclusiveCache_outer_TLBuffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_c_ready = InclusiveCache_outer_TLBuffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_c_valid = InclusiveCache_outer_TLBuffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_address = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_d_ready = InclusiveCache_outer_TLBuffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_valid = InclusiveCache_outer_TLBuffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_out_e_valid = InclusiveCache_outer_TLBuffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_a_ready = InclusiveCache_outer_TLBuffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_valid = InclusiveCache_outer_TLBuffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_mask = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_a_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_c_ready = InclusiveCache_outer_TLBuffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_valid = InclusiveCache_outer_TLBuffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_address = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_c_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_c_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_d_ready = InclusiveCache_outer_TLBuffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_auto_in_d_valid = InclusiveCache_outer_TLBuffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_param = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_size = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_source = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_data = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt = InclusiveCache_outer_TLBuffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_valid = InclusiveCache_outer_TLBuffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign InclusiveCache_outer_TLBuffer_nodeOut_e_bits_sink = InclusiveCache_outer_TLBuffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire coherent_jbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_a_ready_0 = coherent_jbar_auto_anon_in_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_valid = coherent_jbar_auto_anon_in_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_opcode = coherent_jbar_auto_anon_in_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_param = coherent_jbar_auto_anon_in_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_a_bits_size = coherent_jbar_auto_anon_in_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_a_bits_source = coherent_jbar_auto_anon_in_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_a_bits_address = coherent_jbar_auto_anon_in_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonIn_a_bits_mask = coherent_jbar_auto_anon_in_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_a_bits_data = coherent_jbar_auto_anon_in_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_a_bits_corrupt = coherent_jbar_auto_anon_in_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_ready = coherent_jbar_auto_anon_in_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_b_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_valid_0 = coherent_jbar_auto_anon_in_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_param_0 = coherent_jbar_auto_anon_in_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_b_bits_address_0 = coherent_jbar_auto_anon_in_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_ready; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_c_ready_0 = coherent_jbar_auto_anon_in_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_valid = coherent_jbar_auto_anon_in_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_opcode = coherent_jbar_auto_anon_in_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_param = coherent_jbar_auto_anon_in_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_c_bits_size = coherent_jbar_auto_anon_in_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_c_bits_source = coherent_jbar_auto_anon_in_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonIn_c_bits_address = coherent_jbar_auto_anon_in_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_c_bits_data = coherent_jbar_auto_anon_in_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_c_bits_corrupt = coherent_jbar_auto_anon_in_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_ready = coherent_jbar_auto_anon_in_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_valid_0 = coherent_jbar_auto_anon_in_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_opcode_0 = coherent_jbar_auto_anon_in_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_param_0 = coherent_jbar_auto_anon_in_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_size_0 = coherent_jbar_auto_anon_in_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_source_0 = coherent_jbar_auto_anon_in_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_sink_0 = coherent_jbar_auto_anon_in_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_denied_0 = coherent_jbar_auto_anon_in_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_data_0 = coherent_jbar_auto_anon_in_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_coherent_jbar_anon_in_d_bits_corrupt_0 = coherent_jbar_auto_anon_in_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonIn_e_valid = coherent_jbar_auto_anon_in_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonIn_e_bits_sink = coherent_jbar_auto_anon_in_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_ready = coherent_jbar_auto_anon_out_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_valid = coherent_jbar_auto_anon_out_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_opcode = coherent_jbar_auto_anon_out_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_param = coherent_jbar_auto_anon_out_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_size = coherent_jbar_auto_anon_out_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_source = coherent_jbar_auto_anon_out_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_address = coherent_jbar_auto_anon_out_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_mask = coherent_jbar_auto_anon_out_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_data = coherent_jbar_auto_anon_out_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_a_bits_corrupt = coherent_jbar_auto_anon_out_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_b_ready = coherent_jbar_auto_anon_out_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_b_valid = coherent_jbar_auto_anon_out_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_b_bits_param = coherent_jbar_auto_anon_out_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_b_bits_address = coherent_jbar_auto_anon_out_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_ready = coherent_jbar_auto_anon_out_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_valid = coherent_jbar_auto_anon_out_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_opcode = coherent_jbar_auto_anon_out_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_param = coherent_jbar_auto_anon_out_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_size = coherent_jbar_auto_anon_out_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_source = coherent_jbar_auto_anon_out_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_address = coherent_jbar_auto_anon_out_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_data = coherent_jbar_auto_anon_out_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_c_bits_corrupt = coherent_jbar_auto_anon_out_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_d_ready = coherent_jbar_auto_anon_out_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_valid = coherent_jbar_auto_anon_out_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_opcode = coherent_jbar_auto_anon_out_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_anonOut_d_bits_param = coherent_jbar_auto_anon_out_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_size = coherent_jbar_auto_anon_out_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_anonOut_d_bits_source = coherent_jbar_auto_anon_out_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_d_bits_sink = coherent_jbar_auto_anon_out_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_denied = coherent_jbar_auto_anon_out_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_anonOut_d_bits_data = coherent_jbar_auto_anon_out_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_d_bits_corrupt = coherent_jbar_auto_anon_out_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_valid = coherent_jbar_auto_anon_out_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign filter_auto_anon_in_e_bits_sink = coherent_jbar_auto_anon_out_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_ready = coherent_jbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_valid = coherent_jbar_anonOut_a_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_opcode = coherent_jbar_anonOut_a_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_param = coherent_jbar_anonOut_a_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_size = coherent_jbar_anonOut_a_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_source = coherent_jbar_anonOut_a_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_address = coherent_jbar_anonOut_a_bits_address; // @[Jbar.scala:44:9]
wire [7:0] coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_mask = coherent_jbar_anonOut_a_bits_mask; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_data = coherent_jbar_anonOut_a_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_a_bits_corrupt = coherent_jbar_anonOut_a_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_b_ready = coherent_jbar_anonOut_b_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_b_valid = coherent_jbar_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_b_bits_param = coherent_jbar_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [31:0] coherent_jbar_out_0_b_bits_address = coherent_jbar_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_ready = coherent_jbar_anonOut_c_ready; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_valid = coherent_jbar_anonOut_c_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_opcode = coherent_jbar_anonOut_c_bits_opcode; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_param = coherent_jbar_anonOut_c_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_size = coherent_jbar_anonOut_c_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_source = coherent_jbar_anonOut_c_bits_source; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_address = coherent_jbar_anonOut_c_bits_address; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_data = coherent_jbar_anonOut_c_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_c_bits_corrupt = coherent_jbar_anonOut_c_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_d_ready = coherent_jbar_anonOut_d_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_out_0_d_valid = coherent_jbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_opcode = coherent_jbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] coherent_jbar_out_0_d_bits_param = coherent_jbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_out_0_d_bits_size = coherent_jbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [5:0] coherent_jbar_out_0_d_bits_source = coherent_jbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar__out_0_d_bits_sink_T = coherent_jbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire coherent_jbar_out_0_d_bits_denied = coherent_jbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] coherent_jbar_out_0_d_bits_data = coherent_jbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_d_bits_corrupt = coherent_jbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_auto_anon_out_e_valid = coherent_jbar_anonOut_e_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_out_e_bits_sink = coherent_jbar_anonOut_e_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_a_ready = coherent_jbar_anonIn_a_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_a_valid = coherent_jbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_opcode = coherent_jbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_param = coherent_jbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_a_bits_size = coherent_jbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__in_0_a_bits_source_T = coherent_jbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] coherent_jbar_in_0_a_bits_address = coherent_jbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] coherent_jbar_in_0_a_bits_mask = coherent_jbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_a_bits_data = coherent_jbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_a_bits_corrupt = coherent_jbar_anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_ready = coherent_jbar_anonIn_b_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_valid = coherent_jbar_anonIn_b_valid; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_param = coherent_jbar_anonIn_b_bits_param; // @[Jbar.scala:44:9]
wire [31:0] coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_b_bits_address = coherent_jbar_anonIn_b_bits_address; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_c_ready = coherent_jbar_anonIn_c_ready; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_c_valid = coherent_jbar_anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_opcode = coherent_jbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_param = coherent_jbar_anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_c_bits_size = coherent_jbar_anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar__in_0_c_bits_source_T = coherent_jbar_anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] coherent_jbar_in_0_c_bits_address = coherent_jbar_anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_in_0_c_bits_data = coherent_jbar_anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_c_bits_corrupt = coherent_jbar_anonIn_c_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_ready = coherent_jbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_valid = coherent_jbar_anonIn_d_valid; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_opcode = coherent_jbar_anonIn_d_bits_opcode; // @[Jbar.scala:44:9]
wire [1:0] coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_param = coherent_jbar_anonIn_d_bits_param; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_size = coherent_jbar_anonIn_d_bits_size; // @[Jbar.scala:44:9]
wire [5:0] coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_auto_anon_in_d_bits_source = coherent_jbar_anonIn_d_bits_source; // @[Jbar.scala:44:9]
wire [2:0] coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_sink = coherent_jbar_anonIn_d_bits_sink; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_denied = coherent_jbar_anonIn_d_bits_denied; // @[Jbar.scala:44:9]
wire [63:0] coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_data = coherent_jbar_anonIn_d_bits_data; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign coherent_jbar_auto_anon_in_d_bits_corrupt = coherent_jbar_anonIn_d_bits_corrupt; // @[Jbar.scala:44:9]
wire coherent_jbar_in_0_e_valid = coherent_jbar_anonIn_e_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_in_0_e_bits_sink = coherent_jbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_a_ready = coherent_jbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsAOI_filtered_0_valid_T_1 = coherent_jbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_opcode = coherent_jbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_param = coherent_jbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsAOI_filtered_0_bits_size = coherent_jbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] coherent_jbar_portsAOI_filtered_0_bits_source = coherent_jbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestAIO_T = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsAOI_filtered_0_bits_address = coherent_jbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] coherent_jbar_portsAOI_filtered_0_bits_mask = coherent_jbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsAOI_filtered_0_bits_data = coherent_jbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsAOI_filtered_0_bits_corrupt = coherent_jbar_in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_ready = coherent_jbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_valid = coherent_jbar_in_0_b_valid; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_param = coherent_jbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_b_bits_address = coherent_jbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
wire coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_c_ready = coherent_jbar_in_0_c_ready; // @[Xbar.scala:159:18]
wire coherent_jbar__portsCOI_filtered_0_valid_T_1 = coherent_jbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_opcode = coherent_jbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_param = coherent_jbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [2:0] coherent_jbar_portsCOI_filtered_0_bits_size = coherent_jbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [5:0] coherent_jbar_portsCOI_filtered_0_bits_source = coherent_jbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] coherent_jbar__requestCIO_T = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] coherent_jbar_portsCOI_filtered_0_bits_address = coherent_jbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] coherent_jbar_portsCOI_filtered_0_bits_data = coherent_jbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsCOI_filtered_0_bits_corrupt = coherent_jbar_in_0_c_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_ready = coherent_jbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_valid = coherent_jbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_opcode = coherent_jbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_param = coherent_jbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_size = coherent_jbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [5:0] coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign coherent_jbar__anonIn_d_bits_source_T = coherent_jbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [2:0] coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_sink = coherent_jbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_denied = coherent_jbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_data = coherent_jbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign coherent_jbar_anonIn_d_bits_corrupt = coherent_jbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire coherent_jbar__portsEOI_filtered_0_valid_T_1 = coherent_jbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] coherent_jbar__requestEIO_uncommonBits_T = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_portsEOI_filtered_0_bits_sink = coherent_jbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_a_bits_source = coherent_jbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign coherent_jbar_in_0_c_bits_source = coherent_jbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign coherent_jbar_anonIn_d_bits_source = coherent_jbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign coherent_jbar_portsAOI_filtered_0_ready = coherent_jbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_a_valid = coherent_jbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_opcode = coherent_jbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_param = coherent_jbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_size = coherent_jbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_source = coherent_jbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_address = coherent_jbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_mask = coherent_jbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_data = coherent_jbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_a_bits_corrupt = coherent_jbar_out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_b_ready = coherent_jbar_out_0_b_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsBIO_filtered_0_valid_T_1 = coherent_jbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsBIO_filtered_0_bits_param = coherent_jbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsBIO_filtered_0_bits_address = coherent_jbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_ready = coherent_jbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_c_valid = coherent_jbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_opcode = coherent_jbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_param = coherent_jbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_size = coherent_jbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_source = coherent_jbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_address = coherent_jbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_data = coherent_jbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_c_bits_corrupt = coherent_jbar_out_0_c_bits_corrupt; // @[Xbar.scala:216:19]
assign coherent_jbar_anonOut_d_ready = coherent_jbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire coherent_jbar__portsDIO_filtered_0_valid_T_1 = coherent_jbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign coherent_jbar_portsDIO_filtered_0_bits_opcode = coherent_jbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_param = coherent_jbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_size = coherent_jbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [5:0] coherent_jbar__requestDOI_uncommonBits_T = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign coherent_jbar_portsDIO_filtered_0_bits_source = coherent_jbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_sink = coherent_jbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_denied = coherent_jbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_data = coherent_jbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsDIO_filtered_0_bits_corrupt = coherent_jbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
wire coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign coherent_jbar_anonOut_e_valid = coherent_jbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign coherent_jbar__anonOut_e_bits_sink_T = coherent_jbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign coherent_jbar_out_0_d_bits_sink = coherent_jbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign coherent_jbar_anonOut_e_bits_sink = coherent_jbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] coherent_jbar__requestAIO_T_1 = {1'h0, coherent_jbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] coherent_jbar__requestCIO_T_1 = {1'h0, coherent_jbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire [5:0] coherent_jbar_requestDOI_uncommonBits = coherent_jbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [2:0] coherent_jbar_requestEIO_uncommonBits = coherent_jbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [12:0] coherent_jbar__beatsAI_decode_T = 13'h3F << coherent_jbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsAI_decode_T_1 = coherent_jbar__beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsAI_decode_T_2 = ~coherent_jbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsAI_decode = coherent_jbar__beatsAI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar__beatsAI_opdata_T = coherent_jbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire coherent_jbar_beatsAI_opdata = ~coherent_jbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] coherent_jbar_beatsAI_0 = coherent_jbar_beatsAI_opdata ? coherent_jbar_beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsCI_decode_T = 13'h3F << coherent_jbar_in_0_c_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsCI_decode_T_1 = coherent_jbar__beatsCI_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsCI_decode_T_2 = ~coherent_jbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsCI_decode = coherent_jbar__beatsCI_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsCI_opdata = coherent_jbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [2:0] coherent_jbar_beatsCI_0 = coherent_jbar_beatsCI_opdata ? coherent_jbar_beatsCI_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [12:0] coherent_jbar__beatsDO_decode_T = 13'h3F << coherent_jbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [5:0] coherent_jbar__beatsDO_decode_T_1 = coherent_jbar__beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] coherent_jbar__beatsDO_decode_T_2 = ~coherent_jbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] coherent_jbar_beatsDO_decode = coherent_jbar__beatsDO_decode_T_2[5:3]; // @[package.scala:243:46]
wire coherent_jbar_beatsDO_opdata = coherent_jbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [2:0] coherent_jbar_beatsDO_0 = coherent_jbar_beatsDO_opdata ? coherent_jbar_beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign coherent_jbar_in_0_a_ready = coherent_jbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_a_valid = coherent_jbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_opcode = coherent_jbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_param = coherent_jbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_size = coherent_jbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_source = coherent_jbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_address = coherent_jbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_mask = coherent_jbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_data = coherent_jbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_a_bits_corrupt = coherent_jbar_portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsAOI_filtered_0_valid = coherent_jbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_b_ready = coherent_jbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_b_valid = coherent_jbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_param = coherent_jbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_b_bits_address = coherent_jbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsBIO_filtered_0_valid = coherent_jbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_in_0_c_ready = coherent_jbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_out_0_c_valid = coherent_jbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_opcode = coherent_jbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_param = coherent_jbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_size = coherent_jbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_source = coherent_jbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_address = coherent_jbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_data = coherent_jbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_c_bits_corrupt = coherent_jbar_portsCOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsCOI_filtered_0_valid = coherent_jbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_d_ready = coherent_jbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_in_0_d_valid = coherent_jbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_opcode = coherent_jbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_param = coherent_jbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_size = coherent_jbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_source = coherent_jbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_sink = coherent_jbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_denied = coherent_jbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_data = coherent_jbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_in_0_d_bits_corrupt = coherent_jbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign coherent_jbar_portsDIO_filtered_0_valid = coherent_jbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign coherent_jbar_out_0_e_valid = coherent_jbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_out_0_e_bits_sink = coherent_jbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign coherent_jbar_portsEOI_filtered_0_valid = coherent_jbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_ready = coupler_to_bus_named_mbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9]
wire [31:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9]
wire coupler_to_bus_named_mbus_bus_xingOut_d_valid = coupler_to_bus_named_mbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17]
wire [1:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_param = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_size = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_source = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingOut_d_bits_data = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_mbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [2:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7]
wire coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
assign coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_a_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [7:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_address = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [7:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_a_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_ready = coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_valid = coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_param = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_size = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_source = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [63:0] coupler_to_bus_named_mbus_widget_anonOut_d_bits_data = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_a_ready = coupler_to_bus_named_mbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_mbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_mbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_mbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_mbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_mbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_mbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_mbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonIn_d_valid = coupler_to_bus_named_mbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_param = coupler_to_bus_named_mbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_size = coupler_to_bus_named_mbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_source = coupler_to_bus_named_mbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_mbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_mbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_data = coupler_to_bus_named_mbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_mbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_anonOut_a_valid = coupler_to_bus_named_mbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_param = coupler_to_bus_named_mbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_size = coupler_to_bus_named_mbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_source = coupler_to_bus_named_mbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_address = coupler_to_bus_named_mbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_mbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_data = coupler_to_bus_named_mbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_anonOut_d_ready = coupler_to_bus_named_mbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_mbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_mbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_mbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_mbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_mbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_mbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_mbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_mbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_mbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingIn_a_ready = coupler_to_bus_named_mbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_mbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_mbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_mbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_mbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_mbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_mbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_mbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_valid = coupler_to_bus_named_mbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_param = coupler_to_bus_named_mbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_size = coupler_to_bus_named_mbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_source = coupler_to_bus_named_mbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_mbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_mbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_data = coupler_to_bus_named_mbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_mbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_bus_xingOut_a_valid = coupler_to_bus_named_mbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_param = coupler_to_bus_named_mbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_size = coupler_to_bus_named_mbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_source = coupler_to_bus_named_mbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_address = coupler_to_bus_named_mbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_mbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_data = coupler_to_bus_named_mbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_bus_xingOut_d_ready = coupler_to_bus_named_mbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_mbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_mbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_mbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_mbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_mbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_mbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_mbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_mbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign coupler_to_bus_named_mbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_mbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17]
InclusiveCache l2 ( // @[Configs.scala:93:24]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_ctrls_ctrl_in_a_ready (auto_l2_ctrls_ctrl_in_a_ready_0),
.auto_ctrls_ctrl_in_a_valid (auto_l2_ctrls_ctrl_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_opcode (auto_l2_ctrls_ctrl_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_param (auto_l2_ctrls_ctrl_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_size (auto_l2_ctrls_ctrl_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_source (auto_l2_ctrls_ctrl_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_address (auto_l2_ctrls_ctrl_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_mask (auto_l2_ctrls_ctrl_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_data (auto_l2_ctrls_ctrl_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_a_bits_corrupt (auto_l2_ctrls_ctrl_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_ready (auto_l2_ctrls_ctrl_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_ctrls_ctrl_in_d_valid (auto_l2_ctrls_ctrl_in_d_valid_0),
.auto_ctrls_ctrl_in_d_bits_opcode (auto_l2_ctrls_ctrl_in_d_bits_opcode_0),
.auto_ctrls_ctrl_in_d_bits_size (auto_l2_ctrls_ctrl_in_d_bits_size_0),
.auto_ctrls_ctrl_in_d_bits_source (auto_l2_ctrls_ctrl_in_d_bits_source_0),
.auto_ctrls_ctrl_in_d_bits_data (auto_l2_ctrls_ctrl_in_d_bits_data_0),
.auto_in_a_ready (_l2_auto_in_a_ready),
.auto_in_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid), // @[Parameters.scala:56:69]
.auto_in_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param), // @[Parameters.scala:56:69]
.auto_in_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size), // @[Parameters.scala:56:69]
.auto_in_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source), // @[Parameters.scala:56:69]
.auto_in_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address), // @[Parameters.scala:56:69]
.auto_in_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask), // @[Parameters.scala:56:69]
.auto_in_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data), // @[Parameters.scala:56:69]
.auto_in_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready), // @[Parameters.scala:56:69]
.auto_in_b_valid (_l2_auto_in_b_valid),
.auto_in_b_bits_param (_l2_auto_in_b_bits_param),
.auto_in_b_bits_address (_l2_auto_in_b_bits_address),
.auto_in_c_ready (_l2_auto_in_c_ready),
.auto_in_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid), // @[Parameters.scala:56:69]
.auto_in_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode), // @[Parameters.scala:56:69]
.auto_in_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param), // @[Parameters.scala:56:69]
.auto_in_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size), // @[Parameters.scala:56:69]
.auto_in_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source), // @[Parameters.scala:56:69]
.auto_in_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address), // @[Parameters.scala:56:69]
.auto_in_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data), // @[Parameters.scala:56:69]
.auto_in_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt), // @[Parameters.scala:56:69]
.auto_in_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready), // @[Parameters.scala:56:69]
.auto_in_d_valid (_l2_auto_in_d_valid),
.auto_in_d_bits_opcode (_l2_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_l2_auto_in_d_bits_param),
.auto_in_d_bits_size (_l2_auto_in_d_bits_size),
.auto_in_d_bits_source (_l2_auto_in_d_bits_source),
.auto_in_d_bits_sink (_l2_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_l2_auto_in_d_bits_denied),
.auto_in_d_bits_data (_l2_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_l2_auto_in_d_bits_corrupt),
.auto_in_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid), // @[Parameters.scala:56:69]
.auto_in_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink), // @[Parameters.scala:56:69]
.auto_out_a_ready (InclusiveCache_outer_TLBuffer_auto_in_a_ready), // @[Buffer.scala:40:9]
.auto_out_a_valid (InclusiveCache_outer_TLBuffer_auto_in_a_valid),
.auto_out_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_a_bits_opcode),
.auto_out_a_bits_param (InclusiveCache_outer_TLBuffer_auto_in_a_bits_param),
.auto_out_a_bits_size (InclusiveCache_outer_TLBuffer_auto_in_a_bits_size),
.auto_out_a_bits_source (InclusiveCache_outer_TLBuffer_auto_in_a_bits_source),
.auto_out_a_bits_address (InclusiveCache_outer_TLBuffer_auto_in_a_bits_address),
.auto_out_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_in_a_bits_mask),
.auto_out_a_bits_data (InclusiveCache_outer_TLBuffer_auto_in_a_bits_data),
.auto_out_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_a_bits_corrupt),
.auto_out_c_ready (InclusiveCache_outer_TLBuffer_auto_in_c_ready), // @[Buffer.scala:40:9]
.auto_out_c_valid (InclusiveCache_outer_TLBuffer_auto_in_c_valid),
.auto_out_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_c_bits_opcode),
.auto_out_c_bits_param (InclusiveCache_outer_TLBuffer_auto_in_c_bits_param),
.auto_out_c_bits_size (InclusiveCache_outer_TLBuffer_auto_in_c_bits_size),
.auto_out_c_bits_source (InclusiveCache_outer_TLBuffer_auto_in_c_bits_source),
.auto_out_c_bits_address (InclusiveCache_outer_TLBuffer_auto_in_c_bits_address),
.auto_out_c_bits_data (InclusiveCache_outer_TLBuffer_auto_in_c_bits_data),
.auto_out_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_c_bits_corrupt),
.auto_out_d_ready (InclusiveCache_outer_TLBuffer_auto_in_d_ready),
.auto_out_d_valid (InclusiveCache_outer_TLBuffer_auto_in_d_valid), // @[Buffer.scala:40:9]
.auto_out_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_in_d_bits_opcode), // @[Buffer.scala:40:9]
.auto_out_d_bits_param (InclusiveCache_outer_TLBuffer_auto_in_d_bits_param), // @[Buffer.scala:40:9]
.auto_out_d_bits_size (InclusiveCache_outer_TLBuffer_auto_in_d_bits_size), // @[Buffer.scala:40:9]
.auto_out_d_bits_source (InclusiveCache_outer_TLBuffer_auto_in_d_bits_source), // @[Buffer.scala:40:9]
.auto_out_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_d_bits_sink), // @[Buffer.scala:40:9]
.auto_out_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_in_d_bits_denied), // @[Buffer.scala:40:9]
.auto_out_d_bits_data (InclusiveCache_outer_TLBuffer_auto_in_d_bits_data), // @[Buffer.scala:40:9]
.auto_out_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_in_d_bits_corrupt), // @[Buffer.scala:40:9]
.auto_out_e_valid (InclusiveCache_outer_TLBuffer_auto_in_e_valid),
.auto_out_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_in_e_bits_sink)
); // @[Configs.scala:93:24]
TLBuffer_a32d64s6k3z3c InclusiveCache_inner_TLBuffer ( // @[Parameters.scala:56:69]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (filter_auto_anon_out_a_ready),
.auto_in_a_valid (filter_auto_anon_out_a_valid), // @[Filter.scala:60:9]
.auto_in_a_bits_opcode (filter_auto_anon_out_a_bits_opcode), // @[Filter.scala:60:9]
.auto_in_a_bits_param (filter_auto_anon_out_a_bits_param), // @[Filter.scala:60:9]
.auto_in_a_bits_size (filter_auto_anon_out_a_bits_size), // @[Filter.scala:60:9]
.auto_in_a_bits_source (filter_auto_anon_out_a_bits_source), // @[Filter.scala:60:9]
.auto_in_a_bits_address (filter_auto_anon_out_a_bits_address), // @[Filter.scala:60:9]
.auto_in_a_bits_mask (filter_auto_anon_out_a_bits_mask), // @[Filter.scala:60:9]
.auto_in_a_bits_data (filter_auto_anon_out_a_bits_data), // @[Filter.scala:60:9]
.auto_in_a_bits_corrupt (filter_auto_anon_out_a_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_b_ready (filter_auto_anon_out_b_ready), // @[Filter.scala:60:9]
.auto_in_b_valid (filter_auto_anon_out_b_valid),
.auto_in_b_bits_param (filter_auto_anon_out_b_bits_param),
.auto_in_b_bits_address (filter_auto_anon_out_b_bits_address),
.auto_in_c_ready (filter_auto_anon_out_c_ready),
.auto_in_c_valid (filter_auto_anon_out_c_valid), // @[Filter.scala:60:9]
.auto_in_c_bits_opcode (filter_auto_anon_out_c_bits_opcode), // @[Filter.scala:60:9]
.auto_in_c_bits_param (filter_auto_anon_out_c_bits_param), // @[Filter.scala:60:9]
.auto_in_c_bits_size (filter_auto_anon_out_c_bits_size), // @[Filter.scala:60:9]
.auto_in_c_bits_source (filter_auto_anon_out_c_bits_source), // @[Filter.scala:60:9]
.auto_in_c_bits_address (filter_auto_anon_out_c_bits_address), // @[Filter.scala:60:9]
.auto_in_c_bits_data (filter_auto_anon_out_c_bits_data), // @[Filter.scala:60:9]
.auto_in_c_bits_corrupt (filter_auto_anon_out_c_bits_corrupt), // @[Filter.scala:60:9]
.auto_in_d_ready (filter_auto_anon_out_d_ready), // @[Filter.scala:60:9]
.auto_in_d_valid (filter_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (filter_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (filter_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (filter_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (filter_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (filter_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (filter_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (filter_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (filter_auto_anon_out_d_bits_corrupt),
.auto_in_e_valid (filter_auto_anon_out_e_valid), // @[Filter.scala:60:9]
.auto_in_e_bits_sink (filter_auto_anon_out_e_bits_sink), // @[Filter.scala:60:9]
.auto_out_a_ready (_l2_auto_in_a_ready), // @[Configs.scala:93:24]
.auto_out_a_valid (_InclusiveCache_inner_TLBuffer_auto_out_a_valid),
.auto_out_a_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_param),
.auto_out_a_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_size),
.auto_out_a_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_source),
.auto_out_a_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_address),
.auto_out_a_bits_mask (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_mask),
.auto_out_a_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_a_bits_corrupt),
.auto_out_b_ready (_InclusiveCache_inner_TLBuffer_auto_out_b_ready),
.auto_out_b_valid (_l2_auto_in_b_valid), // @[Configs.scala:93:24]
.auto_out_b_bits_param (_l2_auto_in_b_bits_param), // @[Configs.scala:93:24]
.auto_out_b_bits_address (_l2_auto_in_b_bits_address), // @[Configs.scala:93:24]
.auto_out_c_ready (_l2_auto_in_c_ready), // @[Configs.scala:93:24]
.auto_out_c_valid (_InclusiveCache_inner_TLBuffer_auto_out_c_valid),
.auto_out_c_bits_opcode (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_opcode),
.auto_out_c_bits_param (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_param),
.auto_out_c_bits_size (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_size),
.auto_out_c_bits_source (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_source),
.auto_out_c_bits_address (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_address),
.auto_out_c_bits_data (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt (_InclusiveCache_inner_TLBuffer_auto_out_c_bits_corrupt),
.auto_out_d_ready (_InclusiveCache_inner_TLBuffer_auto_out_d_ready),
.auto_out_d_valid (_l2_auto_in_d_valid), // @[Configs.scala:93:24]
.auto_out_d_bits_opcode (_l2_auto_in_d_bits_opcode), // @[Configs.scala:93:24]
.auto_out_d_bits_param (_l2_auto_in_d_bits_param), // @[Configs.scala:93:24]
.auto_out_d_bits_size (_l2_auto_in_d_bits_size), // @[Configs.scala:93:24]
.auto_out_d_bits_source (_l2_auto_in_d_bits_source), // @[Configs.scala:93:24]
.auto_out_d_bits_sink (_l2_auto_in_d_bits_sink), // @[Configs.scala:93:24]
.auto_out_d_bits_denied (_l2_auto_in_d_bits_denied), // @[Configs.scala:93:24]
.auto_out_d_bits_data (_l2_auto_in_d_bits_data), // @[Configs.scala:93:24]
.auto_out_d_bits_corrupt (_l2_auto_in_d_bits_corrupt), // @[Configs.scala:93:24]
.auto_out_e_valid (_InclusiveCache_inner_TLBuffer_auto_out_e_valid),
.auto_out_e_bits_sink (_InclusiveCache_inner_TLBuffer_auto_out_e_bits_sink)
); // @[Parameters.scala:56:69]
TLCacheCork cork ( // @[Configs.scala:120:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (InclusiveCache_outer_TLBuffer_auto_out_a_ready),
.auto_in_a_valid (InclusiveCache_outer_TLBuffer_auto_out_a_valid), // @[Buffer.scala:40:9]
.auto_in_a_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_a_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_a_bits_param (InclusiveCache_outer_TLBuffer_auto_out_a_bits_param), // @[Buffer.scala:40:9]
.auto_in_a_bits_size (InclusiveCache_outer_TLBuffer_auto_out_a_bits_size), // @[Buffer.scala:40:9]
.auto_in_a_bits_source (InclusiveCache_outer_TLBuffer_auto_out_a_bits_source), // @[Buffer.scala:40:9]
.auto_in_a_bits_address (InclusiveCache_outer_TLBuffer_auto_out_a_bits_address), // @[Buffer.scala:40:9]
.auto_in_a_bits_mask (InclusiveCache_outer_TLBuffer_auto_out_a_bits_mask), // @[Buffer.scala:40:9]
.auto_in_a_bits_data (InclusiveCache_outer_TLBuffer_auto_out_a_bits_data), // @[Buffer.scala:40:9]
.auto_in_a_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_c_ready (InclusiveCache_outer_TLBuffer_auto_out_c_ready),
.auto_in_c_valid (InclusiveCache_outer_TLBuffer_auto_out_c_valid), // @[Buffer.scala:40:9]
.auto_in_c_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_c_bits_opcode), // @[Buffer.scala:40:9]
.auto_in_c_bits_param (InclusiveCache_outer_TLBuffer_auto_out_c_bits_param), // @[Buffer.scala:40:9]
.auto_in_c_bits_size (InclusiveCache_outer_TLBuffer_auto_out_c_bits_size), // @[Buffer.scala:40:9]
.auto_in_c_bits_source (InclusiveCache_outer_TLBuffer_auto_out_c_bits_source), // @[Buffer.scala:40:9]
.auto_in_c_bits_address (InclusiveCache_outer_TLBuffer_auto_out_c_bits_address), // @[Buffer.scala:40:9]
.auto_in_c_bits_data (InclusiveCache_outer_TLBuffer_auto_out_c_bits_data), // @[Buffer.scala:40:9]
.auto_in_c_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_c_bits_corrupt), // @[Buffer.scala:40:9]
.auto_in_d_ready (InclusiveCache_outer_TLBuffer_auto_out_d_ready), // @[Buffer.scala:40:9]
.auto_in_d_valid (InclusiveCache_outer_TLBuffer_auto_out_d_valid),
.auto_in_d_bits_opcode (InclusiveCache_outer_TLBuffer_auto_out_d_bits_opcode),
.auto_in_d_bits_param (InclusiveCache_outer_TLBuffer_auto_out_d_bits_param),
.auto_in_d_bits_size (InclusiveCache_outer_TLBuffer_auto_out_d_bits_size),
.auto_in_d_bits_source (InclusiveCache_outer_TLBuffer_auto_out_d_bits_source),
.auto_in_d_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_d_bits_sink),
.auto_in_d_bits_denied (InclusiveCache_outer_TLBuffer_auto_out_d_bits_denied),
.auto_in_d_bits_data (InclusiveCache_outer_TLBuffer_auto_out_d_bits_data),
.auto_in_d_bits_corrupt (InclusiveCache_outer_TLBuffer_auto_out_d_bits_corrupt),
.auto_in_e_valid (InclusiveCache_outer_TLBuffer_auto_out_e_valid), // @[Buffer.scala:40:9]
.auto_in_e_bits_sink (InclusiveCache_outer_TLBuffer_auto_out_e_bits_sink), // @[Buffer.scala:40:9]
.auto_out_a_ready (_binder_auto_in_a_ready), // @[BankBinder.scala:71:28]
.auto_out_a_valid (_cork_auto_out_a_valid),
.auto_out_a_bits_opcode (_cork_auto_out_a_bits_opcode),
.auto_out_a_bits_param (_cork_auto_out_a_bits_param),
.auto_out_a_bits_size (_cork_auto_out_a_bits_size),
.auto_out_a_bits_source (_cork_auto_out_a_bits_source),
.auto_out_a_bits_address (_cork_auto_out_a_bits_address),
.auto_out_a_bits_mask (_cork_auto_out_a_bits_mask),
.auto_out_a_bits_data (_cork_auto_out_a_bits_data),
.auto_out_a_bits_corrupt (_cork_auto_out_a_bits_corrupt),
.auto_out_d_ready (_cork_auto_out_d_ready),
.auto_out_d_valid (_binder_auto_in_d_valid), // @[BankBinder.scala:71:28]
.auto_out_d_bits_opcode (_binder_auto_in_d_bits_opcode), // @[BankBinder.scala:71:28]
.auto_out_d_bits_param (_binder_auto_in_d_bits_param), // @[BankBinder.scala:71:28]
.auto_out_d_bits_size (_binder_auto_in_d_bits_size), // @[BankBinder.scala:71:28]
.auto_out_d_bits_source (_binder_auto_in_d_bits_source), // @[BankBinder.scala:71:28]
.auto_out_d_bits_sink (_binder_auto_in_d_bits_sink), // @[BankBinder.scala:71:28]
.auto_out_d_bits_denied (_binder_auto_in_d_bits_denied), // @[BankBinder.scala:71:28]
.auto_out_d_bits_data (_binder_auto_in_d_bits_data), // @[BankBinder.scala:71:28]
.auto_out_d_bits_corrupt (_binder_auto_in_d_bits_corrupt) // @[BankBinder.scala:71:28]
); // @[Configs.scala:120:26]
BankBinder binder ( // @[BankBinder.scala:71:28]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_in_a_ready (_binder_auto_in_a_ready),
.auto_in_a_valid (_cork_auto_out_a_valid), // @[Configs.scala:120:26]
.auto_in_a_bits_opcode (_cork_auto_out_a_bits_opcode), // @[Configs.scala:120:26]
.auto_in_a_bits_param (_cork_auto_out_a_bits_param), // @[Configs.scala:120:26]
.auto_in_a_bits_size (_cork_auto_out_a_bits_size), // @[Configs.scala:120:26]
.auto_in_a_bits_source (_cork_auto_out_a_bits_source), // @[Configs.scala:120:26]
.auto_in_a_bits_address (_cork_auto_out_a_bits_address), // @[Configs.scala:120:26]
.auto_in_a_bits_mask (_cork_auto_out_a_bits_mask), // @[Configs.scala:120:26]
.auto_in_a_bits_data (_cork_auto_out_a_bits_data), // @[Configs.scala:120:26]
.auto_in_a_bits_corrupt (_cork_auto_out_a_bits_corrupt), // @[Configs.scala:120:26]
.auto_in_d_ready (_cork_auto_out_d_ready), // @[Configs.scala:120:26]
.auto_in_d_valid (_binder_auto_in_d_valid),
.auto_in_d_bits_opcode (_binder_auto_in_d_bits_opcode),
.auto_in_d_bits_param (_binder_auto_in_d_bits_param),
.auto_in_d_bits_size (_binder_auto_in_d_bits_size),
.auto_in_d_bits_source (_binder_auto_in_d_bits_source),
.auto_in_d_bits_sink (_binder_auto_in_d_bits_sink),
.auto_in_d_bits_denied (_binder_auto_in_d_bits_denied),
.auto_in_d_bits_data (_binder_auto_in_d_bits_data),
.auto_in_d_bits_corrupt (_binder_auto_in_d_bits_corrupt),
.auto_out_a_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7]
.auto_out_a_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_a_valid),
.auto_out_a_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_opcode),
.auto_out_a_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_param),
.auto_out_a_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_size),
.auto_out_a_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_source),
.auto_out_a_bits_address (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_address),
.auto_out_a_bits_mask (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_mask),
.auto_out_a_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_data),
.auto_out_a_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_a_bits_corrupt),
.auto_out_d_ready (coupler_to_bus_named_mbus_auto_widget_anon_in_d_ready),
.auto_out_d_valid (coupler_to_bus_named_mbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_opcode (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_param (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_size (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_source (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_sink (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_denied (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_data (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7]
.auto_out_d_bits_corrupt (coupler_to_bus_named_mbus_auto_widget_anon_in_d_bits_corrupt) // @[LazyModuleImp.scala:138:7]
); // @[BankBinder.scala:71:28]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_a_ready = auto_coherent_jbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_valid = auto_coherent_jbar_anon_in_b_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_param = auto_coherent_jbar_anon_in_b_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_b_bits_address = auto_coherent_jbar_anon_in_b_bits_address_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_c_ready = auto_coherent_jbar_anon_in_c_ready_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_valid = auto_coherent_jbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_opcode = auto_coherent_jbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_param = auto_coherent_jbar_anon_in_d_bits_param_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_size = auto_coherent_jbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_source = auto_coherent_jbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_sink = auto_coherent_jbar_anon_in_d_bits_sink_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_denied = auto_coherent_jbar_anon_in_d_bits_denied_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_data = auto_coherent_jbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
assign auto_coherent_jbar_anon_in_d_bits_corrupt = auto_coherent_jbar_anon_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_a_ready = auto_l2_ctrls_ctrl_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_valid = auto_l2_ctrls_ctrl_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_opcode = auto_l2_ctrls_ctrl_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_size = auto_l2_ctrls_ctrl_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_source = auto_l2_ctrls_ctrl_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_l2_ctrls_ctrl_in_d_bits_data = auto_l2_ctrls_ctrl_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module array_0( // @[DescribedSRAM.scala:17:26]
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [255:0] RW0_wdata,
output [255:0] RW0_rdata,
input [3:0] RW0_wmask
);
array_0_ext array_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File ProbePicker.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, IdRange}
/* A ProbePicker is used to unify multiple cache banks into one logical cache */
class ProbePicker(implicit p: Parameters) extends LazyModule
{
val node = TLAdapterNode(
clientFn = { p =>
// The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list
// This should be true for custers of xbar :=* BankBinder connections
def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = {
val (head, output) = pair
if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) {
(next, head +: output) // pair is not banked, push head without merging
} else {
def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0)))
require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}")
val merge = head.v1copy(
sourceId = IdRange(
head.sourceId.start min next.sourceId.start,
head.sourceId.end max next.sourceId.end),
visibility = AddressSet.unify(head.visibility ++ next.visibility))
(merge, output)
}
}
val myNil: Seq[TLMasterParameters] = Nil
val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine)
p.v1copy(clients = head +: output)
},
managerFn = { p => p })
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out <> in
// Based on address, adjust source to route to the correct bank
if (edgeIn.client.clients.size != edgeOut.client.clients.size) {
in.b.bits.source := Mux1H(
edgeOut.client.clients.map(_.sourceId contains out.b.bits.source),
edgeOut.client.clients.map { c =>
val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId)
if (banks.size == 1) {
out.b.bits.source // allow sharing the value between single-bank cases
} else {
Mux1H(
banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ || _)),
banks.map(_.sourceId.start.U))
}
}
)
}
}
}
}
object ProbePicker
{
def apply()(implicit p: Parameters): TLNode = {
val picker = LazyModule(new ProbePicker)
picker.node
}
}
| module ProbePicker( // @[ProbePicker.scala:42:9]
input clock, // @[ProbePicker.scala:42:9]
input reset, // @[ProbePicker.scala:42:9]
output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [27:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[ProbePicker.scala:42:9]
wire [27:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[ProbePicker.scala:42:9]
wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[ProbePicker.scala:42:9]
wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_sink = 1'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_out_0_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire [1:0] nodeIn_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[ProbePicker.scala:42:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [4:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [27:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [1:0] auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [27:0] auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
wire [2:0] auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
wire [4:0] auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
wire [31:0] auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
wire [7:0] auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
wire [63:0] auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
wire auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[ProbePicker.scala:42:9]
assign nodeOut_a_valid = nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_param = nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_size = nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_source = nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_mask = nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_a_bits_corrupt = nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeOut_d_ready = nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[ProbePicker.scala:42:9]
assign x1_nodeOut_a_valid = nodeIn_1_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_opcode = nodeIn_1_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_param = nodeIn_1_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_size = nodeIn_1_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_source = nodeIn_1_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_address = nodeIn_1_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_mask = nodeIn_1_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_data = nodeIn_1_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_a_bits_corrupt = nodeIn_1_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign x1_nodeOut_d_ready = nodeIn_1_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[ProbePicker.scala:42:9]
assign nodeIn_a_ready = nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_d_valid = nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_opcode = nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_size = nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_source = nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_denied = nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_data = nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_d_bits_corrupt = nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_a_ready = x1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[ProbePicker.scala:42:9]
assign nodeIn_1_d_valid = x1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_opcode = x1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_param = x1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_size = x1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_source = x1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_sink = x1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_denied = x1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_data = x1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign nodeIn_1_d_bits_corrupt = x1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
TLMonitor_31 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
TLMonitor_32 monitor_1 ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[ProbePicker.scala:42:9]
assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[ProbePicker.scala:42:9]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncQueue_16( // @[AsyncQueue.scala:226:7]
input io_enq_clock, // @[AsyncQueue.scala:227:14]
input io_enq_reset, // @[AsyncQueue.scala:227:14]
output io_enq_ready, // @[AsyncQueue.scala:227:14]
input io_enq_valid, // @[AsyncQueue.scala:227:14]
input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:227:14]
input io_deq_clock, // @[AsyncQueue.scala:227:14]
input io_deq_reset, // @[AsyncQueue.scala:227:14]
input io_deq_ready, // @[AsyncQueue.scala:227:14]
output io_deq_valid, // @[AsyncQueue.scala:227:14]
output [31:0] io_deq_bits_phit // @[AsyncQueue.scala:227:14]
);
wire [3:0] _sink_io_async_ridx; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_ridx_valid; // @[AsyncQueue.scala:229:70]
wire _sink_io_async_safe_sink_reset_n; // @[AsyncQueue.scala:229:70]
wire [31:0] _source_io_async_mem_0_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_1_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_2_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_3_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_4_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_5_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_6_phit; // @[AsyncQueue.scala:228:70]
wire [31:0] _source_io_async_mem_7_phit; // @[AsyncQueue.scala:228:70]
wire [3:0] _source_io_async_widx; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_widx_valid; // @[AsyncQueue.scala:228:70]
wire _source_io_async_safe_source_reset_n; // @[AsyncQueue.scala:228:70]
wire io_enq_clock_0 = io_enq_clock; // @[AsyncQueue.scala:226:7]
wire io_enq_reset_0 = io_enq_reset; // @[AsyncQueue.scala:226:7]
wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:226:7]
wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:226:7]
wire io_deq_clock_0 = io_deq_clock; // @[AsyncQueue.scala:226:7]
wire io_deq_reset_0 = io_deq_reset; // @[AsyncQueue.scala:226:7]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:226:7]
wire io_enq_ready_0; // @[AsyncQueue.scala:226:7]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:226:7]
AsyncQueueSource_Phit_16 source ( // @[AsyncQueue.scala:228:70]
.clock (io_enq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_enq_reset_0), // @[AsyncQueue.scala:226:7]
.io_enq_ready (io_enq_ready_0),
.io_enq_valid (io_enq_valid_0), // @[AsyncQueue.scala:226:7]
.io_enq_bits_phit (io_enq_bits_phit_0), // @[AsyncQueue.scala:226:7]
.io_async_mem_0_phit (_source_io_async_mem_0_phit),
.io_async_mem_1_phit (_source_io_async_mem_1_phit),
.io_async_mem_2_phit (_source_io_async_mem_2_phit),
.io_async_mem_3_phit (_source_io_async_mem_3_phit),
.io_async_mem_4_phit (_source_io_async_mem_4_phit),
.io_async_mem_5_phit (_source_io_async_mem_5_phit),
.io_async_mem_6_phit (_source_io_async_mem_6_phit),
.io_async_mem_7_phit (_source_io_async_mem_7_phit),
.io_async_ridx (_sink_io_async_ridx), // @[AsyncQueue.scala:229:70]
.io_async_widx (_source_io_async_widx),
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid), // @[AsyncQueue.scala:229:70]
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid),
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n),
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n) // @[AsyncQueue.scala:229:70]
); // @[AsyncQueue.scala:228:70]
AsyncQueueSink_Phit_16 sink ( // @[AsyncQueue.scala:229:70]
.clock (io_deq_clock_0), // @[AsyncQueue.scala:226:7]
.reset (io_deq_reset_0), // @[AsyncQueue.scala:226:7]
.io_deq_ready (io_deq_ready_0), // @[AsyncQueue.scala:226:7]
.io_deq_valid (io_deq_valid_0),
.io_deq_bits_phit (io_deq_bits_phit_0),
.io_async_mem_0_phit (_source_io_async_mem_0_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_1_phit (_source_io_async_mem_1_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_2_phit (_source_io_async_mem_2_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_3_phit (_source_io_async_mem_3_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_4_phit (_source_io_async_mem_4_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_5_phit (_source_io_async_mem_5_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_6_phit (_source_io_async_mem_6_phit), // @[AsyncQueue.scala:228:70]
.io_async_mem_7_phit (_source_io_async_mem_7_phit), // @[AsyncQueue.scala:228:70]
.io_async_ridx (_sink_io_async_ridx),
.io_async_widx (_source_io_async_widx), // @[AsyncQueue.scala:228:70]
.io_async_safe_ridx_valid (_sink_io_async_safe_ridx_valid),
.io_async_safe_widx_valid (_source_io_async_safe_widx_valid), // @[AsyncQueue.scala:228:70]
.io_async_safe_source_reset_n (_source_io_async_safe_source_reset_n), // @[AsyncQueue.scala:228:70]
.io_async_safe_sink_reset_n (_sink_io_async_safe_sink_reset_n)
); // @[AsyncQueue.scala:229:70]
assign io_enq_ready = io_enq_ready_0; // @[AsyncQueue.scala:226:7]
assign io_deq_valid = io_deq_valid_0; // @[AsyncQueue.scala:226:7]
assign io_deq_bits_phit = io_deq_bits_phit_0; // @[AsyncQueue.scala:226:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_preMul_e8_s24( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [32:0] io_a, // @[MulAddRecFN.scala:74:16]
input [32:0] io_b, // @[MulAddRecFN.scala:74:16]
input [32:0] io_c, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_isNaN = (&(io_a[31:30])) & io_a[29]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawB_isNaN = (&(io_b[31:30])) & io_b[29]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawC_isNaN = (&(io_c[31:30])) & io_c[29]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire signProd = io_a[32] ^ io_b[32] ^ io_op[1]; // @[rawFloatFromRecFN.scala:59:25]
wire [10:0] _sExpAlignedProd_T_1 = {2'h0, io_a[31:23]} + {2'h0, io_b[31:23]} - 11'hE5; // @[rawFloatFromRecFN.scala:51:21]
wire doSubMags = signProd ^ io_c[32] ^ io_op[0]; // @[rawFloatFromRecFN.scala:59:25]
wire [10:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[31:23]}; // @[rawFloatFromRecFN.scala:51:21]
wire isMinCAlign = ~(|(io_a[31:29])) | ~(|(io_b[31:29])) | $signed(_sNatCAlignDist_T) < 11'sh0; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire CIsDominant = (|(io_c[31:29])) & (isMinCAlign | _sNatCAlignDist_T[9:0] < 10'h19); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _sNatCAlignDist_T[9:0] < 10'h4A ? _sNatCAlignDist_T[6:0] : 7'h4A; // @[MulAddRecFN.scala:106:42, :107:42, :108:{35,50}, :112:12, :114:{16,34}, :115:33]
wire [77:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[31:29])), ~(io_c[22:0])} : {1'h0, |(io_c[31:29]), io_c[22:0]}, {53{doSubMags}}}) >>> CAlignDist); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}]
wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> CAlignDist[6:2]); // @[primitives.scala:76:56]
wire [5:0] _GEN = {|(io_c[21:18]), |(io_c[17:14]), |(io_c[13:10]), |(io_c[9:6]), |(io_c[5:2]), |(io_c[1:0])} & {reduced4CExtra_shift[14], reduced4CExtra_shift[15], reduced4CExtra_shift[16], reduced4CExtra_shift[17], reduced4CExtra_shift[18], reduced4CExtra_shift[19]}; // @[primitives.scala:76:56, :77:20, :78:22, :120:{33,54}]
assign io_mulAddA = {|(io_a[31:29]), io_a[22:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddB = {|(io_b[31:29]), io_b[22:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddC = mainAlignedSigC[50:3]; // @[MulAddRecFN.scala:71:7, :120:100, :143:30]
assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[22]) | rawB_isNaN & ~(io_b[22]) | rawC_isNaN & ~(io_c[22]); // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfA = (&(io_a[31:30])) & ~(io_a[29]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroA = ~(|(io_a[31:29])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_isInfB = (&(io_b[31:30])) & ~(io_b[29]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroB = ~(|(io_b[31:29])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_signProd = signProd; // @[MulAddRecFN.scala:71:7, :97:{30,42}]
assign io_toPostMul_isNaNC = rawC_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfC = (&(io_c[31:30])) & ~(io_c[29]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroC = ~(|(io_c[31:29])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[31:23]} : _sExpAlignedProd_T_1[9:0] - 10'h18; // @[rawFloatFromRecFN.scala:51:21]
assign io_toPostMul_doSubMags = doSubMags; // @[MulAddRecFN.scala:71:7, :102:{30,42}]
assign io_toPostMul_CIsDominant = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
assign io_toPostMul_CDom_CAlignDist = CAlignDist[4:0]; // @[MulAddRecFN.scala:71:7, :112:12, :161:47]
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[76:51]; // @[MulAddRecFN.scala:71:7, :120:100, :163:20]
assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 6'h0 : (|{mainAlignedSigC[2:0], _GEN}); // @[MulAddRecFN.scala:71:7, :102:{30,42}, :120:100, :122:68, :130:11, :133:16, :134:{32,39,44}, :135:{39,44}]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Frontend.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.bundlebridge._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.tile.{CoreBundle, BaseTile}
import freechips.rocketchip.tilelink.{TLWidthWidget, TLEdgeOut}
import freechips.rocketchip.util.{ClockGate, ShiftQueue, property}
import freechips.rocketchip.util.UIntToAugmentedUInt
class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {
val pc = UInt(vaddrBitsExtended.W)
val speculative = Bool()
}
class FrontendExceptions extends Bundle {
val pf = new Bundle {
val inst = Bool()
}
val gf = new Bundle {
val inst = Bool()
}
val ae = new Bundle {
val inst = Bool()
}
}
class FrontendResp(implicit p: Parameters) extends CoreBundle()(p) {
val btb = new BTBResp
val pc = UInt(vaddrBitsExtended.W) // ID stage PC
val data = UInt((fetchWidth * coreInstBits).W)
val mask = Bits(fetchWidth.W)
val xcpt = new FrontendExceptions
val replay = Bool()
}
class FrontendPerfEvents extends Bundle {
val acquire = Bool()
val tlbMiss = Bool()
}
class FrontendIO(implicit p: Parameters) extends CoreBundle()(p) {
val might_request = Output(Bool())
val clock_enabled = Input(Bool())
val req = Valid(new FrontendReq)
val sfence = Valid(new SFenceReq)
val resp = Flipped(Decoupled(new FrontendResp))
val gpa = Flipped(Valid(UInt(vaddrBitsExtended.W)))
val gpa_is_pte = Input(Bool())
val btb_update = Valid(new BTBUpdate)
val bht_update = Valid(new BHTUpdate)
val ras_update = Valid(new RASUpdate)
val flush_icache = Output(Bool())
val npc = Input(UInt(vaddrBitsExtended.W))
val perf = Input(new FrontendPerfEvents())
val progress = Output(Bool())
}
class Frontend(val icacheParams: ICacheParams, tileId: Int)(implicit p: Parameters) extends LazyModule {
lazy val module = new FrontendModule(this)
val icache = LazyModule(new ICache(icacheParams, tileId))
val masterNode = icache.masterNode
val slaveNode = icache.slaveNode
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(masterNode.edges.out.head.bundle.addressBits.W)))
}
class FrontendBundle(val outer: Frontend) extends CoreBundle()(outer.p) {
val cpu = Flipped(new FrontendIO())
val ptw = new TLBPTWIO()
val errors = new ICacheErrors
}
class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
with HasRocketCoreParameters
with HasL1ICacheParameters {
val io = IO(new FrontendBundle(outer))
val io_reset_vector = outer.resetVectorSinkNode.bundle
implicit val edge: TLEdgeOut = outer.masterNode.edges.out(0)
val icache = outer.icache.module
require(fetchWidth*coreInstBytes == outer.icacheParams.fetchBytes)
val fq = withReset(reset.asBool || io.cpu.req.valid) { Module(new ShiftQueue(new FrontendResp, 5, flow = true)) }
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cpu.might_request
io.cpu.clock_enabled := clock_en
assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "icache_clock_gate")
icache.clock := gated_clock
icache.io.clock_enabled := clock_en
withClock (gated_clock) { // entering gated-clock domain
val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBSets, nTLBWays, outer.icacheParams.nTLBBasePageSectors, outer.icacheParams.nTLBSuperpages)))
val s1_valid = Reg(Bool())
val s2_valid = RegInit(false.B)
val s0_fq_has_space =
!fq.io.mask(fq.io.mask.getWidth-3) ||
(!fq.io.mask(fq.io.mask.getWidth-2) && (!s1_valid || !s2_valid)) ||
(!fq.io.mask(fq.io.mask.getWidth-1) && (!s1_valid && !s2_valid))
val s0_valid = io.cpu.req.valid || s0_fq_has_space
s1_valid := s0_valid
val s1_pc = Reg(UInt(vaddrBitsExtended.W))
val s1_speculative = Reg(Bool())
val s2_pc = RegInit(t = UInt(vaddrBitsExtended.W), alignPC(io_reset_vector))
val s2_btb_resp_valid = if (usingBTB) Reg(Bool()) else false.B
val s2_btb_resp_bits = Reg(new BTBResp)
val s2_btb_taken = s2_btb_resp_valid && s2_btb_resp_bits.taken
val s2_tlb_resp = Reg(tlb.io.resp.cloneType)
val s2_xcpt = s2_tlb_resp.ae.inst || s2_tlb_resp.pf.inst || s2_tlb_resp.gf.inst
val s2_speculative = RegInit(false.B)
val s2_partial_insn_valid = RegInit(false.B)
val s2_partial_insn = Reg(UInt(coreInstBits.W))
val wrong_path = RegInit(false.B)
val s1_base_pc = ~(~s1_pc | (fetchBytes - 1).U)
val ntpc = s1_base_pc + fetchBytes.U
val predicted_npc = WireDefault(ntpc)
val predicted_taken = WireDefault(false.B)
val s2_replay = Wire(Bool())
s2_replay := (s2_valid && !fq.io.enq.fire) || RegNext(s2_replay && !s0_valid, true.B)
val npc = Mux(s2_replay, s2_pc, predicted_npc)
s1_pc := io.cpu.npc
// consider RVC fetches across blocks to be non-speculative if the first
// part was non-speculative
val s0_speculative =
if (usingCompressed) s1_speculative || s2_valid && !s2_speculative || predicted_taken
else true.B
s1_speculative := Mux(io.cpu.req.valid, io.cpu.req.bits.speculative, Mux(s2_replay, s2_speculative, s0_speculative))
val s2_redirect = WireDefault(io.cpu.req.valid)
s2_valid := false.B
when (!s2_replay) {
s2_valid := !s2_redirect
s2_pc := s1_pc
s2_speculative := s1_speculative
s2_tlb_resp := tlb.io.resp
}
val recent_progress_counter_init = 3.U
val recent_progress_counter = RegInit(recent_progress_counter_init)
val recent_progress = recent_progress_counter > 0.U
when(io.ptw.req.fire && recent_progress) { recent_progress_counter := recent_progress_counter - 1.U }
when(io.cpu.progress) { recent_progress_counter := recent_progress_counter_init }
val s2_kill_speculative_tlb_refill = s2_speculative && !recent_progress
io.ptw <> tlb.io.ptw
tlb.io.req.valid := s1_valid && !s2_replay
tlb.io.req.bits.cmd := M_XRD // Frontend only reads
tlb.io.req.bits.vaddr := s1_pc
tlb.io.req.bits.passthrough := false.B
tlb.io.req.bits.size := log2Ceil(coreInstBytes*fetchWidth).U
tlb.io.req.bits.prv := io.ptw.status.prv
tlb.io.req.bits.v := io.ptw.status.v
tlb.io.sfence := io.cpu.sfence
tlb.io.kill := !s2_valid || s2_kill_speculative_tlb_refill
icache.io.req.valid := s0_valid
icache.io.req.bits.addr := io.cpu.npc
icache.io.invalidate := io.cpu.flush_icache
icache.io.s1_paddr := tlb.io.resp.paddr
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
val s2_can_speculatively_refill = s2_tlb_resp.cacheable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill
icache.io.s2_kill := s2_speculative && !s2_can_speculatively_refill || s2_xcpt
icache.io.s2_cacheable := s2_tlb_resp.cacheable
icache.io.s2_prefetch := s2_tlb_resp.prefetchable && !io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableICachePrefetch
fq.io.enq.valid := RegNext(s1_valid) && s2_valid && (icache.io.resp.valid || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss) || (!s2_tlb_resp.miss && icache.io.s2_kill))
fq.io.enq.bits.pc := s2_pc
io.cpu.npc := alignPC(Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc))
fq.io.enq.bits.data := icache.io.resp.bits.data
fq.io.enq.bits.mask := ((1 << fetchWidth)-1).U << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
fq.io.enq.bits.replay := (icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt) || (s2_kill_speculative_tlb_refill && s2_tlb_resp.miss)
fq.io.enq.bits.btb := s2_btb_resp_bits
fq.io.enq.bits.btb.taken := s2_btb_taken
fq.io.enq.bits.xcpt := s2_tlb_resp
assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))
when (icache.io.resp.valid && icache.io.resp.bits.ae) { fq.io.enq.bits.xcpt.ae.inst := true.B }
if (usingBTB) {
val btb = Module(new BTB)
btb.io.flush := false.B
btb.io.req.valid := false.B
btb.io.req.bits.addr := s1_pc
btb.io.btb_update := io.cpu.btb_update
btb.io.bht_update := io.cpu.bht_update
btb.io.ras_update.valid := false.B
btb.io.ras_update.bits := DontCare
btb.io.bht_advance.valid := false.B
btb.io.bht_advance.bits := DontCare
when (!s2_replay) {
btb.io.req.valid := !s2_redirect
s2_btb_resp_valid := btb.io.resp.valid
s2_btb_resp_bits := btb.io.resp.bits
}
when (btb.io.resp.valid && btb.io.resp.bits.taken) {
predicted_npc := btb.io.resp.bits.target.sextTo(vaddrBitsExtended)
predicted_taken := true.B
}
val force_taken = io.ptw.customCSRs.bpmStatic
when (io.ptw.customCSRs.flushBTB) { btb.io.flush := true.B }
when (force_taken) { btb.io.bht_update.valid := false.B }
val s2_base_pc = ~(~s2_pc | (fetchBytes-1).U)
val taken_idx = Wire(UInt())
val after_idx = Wire(UInt())
val useRAS = WireDefault(false.B)
val updateBTB = WireDefault(false.B)
// If !prevTaken, ras_update / bht_update is always invalid.
taken_idx := DontCare
after_idx := DontCare
def scanInsns(idx: Int, prevValid: Bool, prevBits: UInt, prevTaken: Bool): Bool = {
def insnIsRVC(bits: UInt) = bits(1,0) =/= 3.U
val prevRVI = prevValid && !insnIsRVC(prevBits)
val valid = fq.io.enq.bits.mask(idx) && !prevRVI
val bits = fq.io.enq.bits.data(coreInstBits*(idx+1)-1, coreInstBits*idx)
val rvc = insnIsRVC(bits)
val rviBits = Cat(bits, prevBits)
val rviBranch = rviBits(6,0) === Instructions.BEQ.value.U.extract(6,0)
val rviJump = rviBits(6,0) === Instructions.JAL.value.U.extract(6,0)
val rviJALR = rviBits(6,0) === Instructions.JALR.value.U.extract(6,0)
val rviReturn = rviJALR && !rviBits(7) && BitPat("b00?01") === rviBits(19,15)
val rviCall = (rviJALR || rviJump) && rviBits(7)
val rvcBranch = bits === Instructions.C_BEQZ || bits === Instructions.C_BNEZ
val rvcJAL = (xLen == 32).B && bits === Instructions32.C_JAL
val rvcJump = bits === Instructions.C_J || rvcJAL
val rvcImm = Mux(bits(14), new RVCDecoder(bits, xLen, fLen).bImm.asSInt, new RVCDecoder(bits, xLen, fLen).jImm.asSInt)
val rvcJR = bits === Instructions.C_MV && bits(6,2) === 0.U
val rvcReturn = rvcJR && BitPat("b00?01") === bits(11,7)
val rvcJALR = bits === Instructions.C_ADD && bits(6,2) === 0.U
val rvcCall = rvcJAL || rvcJALR
val rviImm = Mux(rviBits(3), ImmGen(IMM_UJ, rviBits), ImmGen(IMM_SB, rviBits))
val predict_taken = s2_btb_resp_bits.bht.taken || force_taken
val taken =
prevRVI && (rviJump || rviJALR || rviBranch && predict_taken) ||
valid && (rvcJump || rvcJALR || rvcJR || rvcBranch && predict_taken)
val predictReturn = btb.io.ras_head.valid && (prevRVI && rviReturn || valid && rvcReturn)
val predictJump = prevRVI && rviJump || valid && rvcJump
val predictBranch = predict_taken && (prevRVI && rviBranch || valid && rvcBranch)
when (s2_valid && s2_btb_resp_valid && s2_btb_resp_bits.bridx === idx.U && valid && !rvc) {
// The BTB has predicted that the middle of an RVI instruction is
// a branch! Flush the BTB and the pipeline.
btb.io.flush := true.B
fq.io.enq.bits.replay := true.B
wrong_path := true.B
ccover(wrong_path, "BTB_NON_CFI_ON_WRONG_PATH", "BTB predicted a non-branch was taken while on the wrong path")
}
when (!prevTaken) {
taken_idx := idx.U
after_idx := (idx + 1).U
btb.io.ras_update.valid := fq.io.enq.fire && !wrong_path && (prevRVI && (rviCall || rviReturn) || valid && (rvcCall || rvcReturn))
btb.io.ras_update.bits.cfiType := Mux(Mux(prevRVI, rviReturn, rvcReturn), CFIType.ret,
Mux(Mux(prevRVI, rviCall, rvcCall), CFIType.call,
Mux(Mux(prevRVI, rviBranch, rvcBranch) && !force_taken, CFIType.branch,
CFIType.jump)))
when (!s2_btb_taken) {
when (fq.io.enq.fire && taken && !predictBranch && !predictJump && !predictReturn) {
wrong_path := true.B
}
when (s2_valid && predictReturn) {
useRAS := true.B
}
when (s2_valid && (predictBranch || predictJump)) {
val pc = s2_base_pc | (idx*coreInstBytes).U
val npc =
if (idx == 0) pc.asSInt + Mux(prevRVI, rviImm -& 2.S, rvcImm)
else Mux(prevRVI, pc - coreInstBytes.U, pc).asSInt + Mux(prevRVI, rviImm, rvcImm)
predicted_npc := npc.asUInt
}
}
when (prevRVI && rviBranch || valid && rvcBranch) {
btb.io.bht_advance.valid := fq.io.enq.fire && !wrong_path
btb.io.bht_advance.bits := s2_btb_resp_bits
}
when (!s2_btb_resp_valid && (predictBranch && s2_btb_resp_bits.bht.strongly_taken || predictJump || predictReturn)) {
updateBTB := true.B
}
}
if (idx == fetchWidth-1) {
when (fq.io.enq.fire) {
s2_partial_insn_valid := false.B
when (valid && !prevTaken && !rvc) {
s2_partial_insn_valid := true.B
s2_partial_insn := bits | 0x3.U
}
}
prevTaken || taken
} else {
scanInsns(idx + 1, valid, bits, prevTaken || taken)
}
}
when (!io.cpu.btb_update.valid) {
val fetch_bubble_likely = !fq.io.mask(1)
btb.io.btb_update.valid := fq.io.enq.fire && !wrong_path && fetch_bubble_likely && updateBTB
btb.io.btb_update.bits.prediction.entry := tileParams.btb.get.nEntries.U
btb.io.btb_update.bits.isValid := true.B
btb.io.btb_update.bits.cfiType := btb.io.ras_update.bits.cfiType
btb.io.btb_update.bits.br_pc := s2_base_pc | (taken_idx << log2Ceil(coreInstBytes))
btb.io.btb_update.bits.pc := s2_base_pc
}
btb.io.ras_update.bits.returnAddr := s2_base_pc + (after_idx << log2Ceil(coreInstBytes))
val taken = scanInsns(0, s2_partial_insn_valid, s2_partial_insn, false.B)
when (useRAS) {
predicted_npc := btb.io.ras_head.bits
}
when (fq.io.enq.fire && (s2_btb_taken || taken)) {
s2_partial_insn_valid := false.B
}
when (!s2_btb_taken) {
when (taken) {
fq.io.enq.bits.btb.bridx := taken_idx
fq.io.enq.bits.btb.taken := true.B
fq.io.enq.bits.btb.entry := tileParams.btb.get.nEntries.U
when (fq.io.enq.fire) { s2_redirect := true.B }
}
}
assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))
when (s2_redirect) { s2_partial_insn_valid := false.B }
when (io.cpu.req.valid) { wrong_path := false.B }
}
io.cpu.resp <> fq.io.deq
// supply guest physical address to commit stage
val gpa_valid = Reg(Bool())
val gpa = Reg(UInt(vaddrBitsExtended.W))
val gpa_is_pte = Reg(Bool())
when (fq.io.enq.fire && s2_tlb_resp.gf.inst) {
when (!gpa_valid) {
gpa := s2_tlb_resp.gpa
gpa_is_pte := s2_tlb_resp.gpa_is_pte
}
gpa_valid := true.B
}
when (io.cpu.req.valid) {
gpa_valid := false.B
}
io.cpu.gpa.valid := gpa_valid
io.cpu.gpa.bits := gpa
io.cpu.gpa_is_pte := gpa_is_pte
// performance events
io.cpu.perf.acquire := icache.io.perf.acquire
io.cpu.perf.tlbMiss := io.ptw.req.fire
io.errors := icache.io.errors
// gate the clock
clock_en_reg := !rocketParams.clockGate.B ||
io.cpu.might_request || // chicken bit
icache.io.keep_clock_enabled || // I$ miss or ITIM access
s1_valid || s2_valid || // some fetch in flight
!tlb.io.req.ready || // handling TLB miss
!fq.io.mask(fq.io.mask.getWidth-1) // queue not full
} // leaving gated-clock domain
def alignPC(pc: UInt) = ~(~pc | (coreInstBytes - 1).U)
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FRONTEND_$label", "Rocket;;" + desc)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(tileParams.icache.get, tileId))
tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode
connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
frontend.icache.hartIdSinkNodeOpt.foreach { _ := hartIdNexusNode }
frontend.icache.mmioAddressPrefixSinkNodeOpt.foreach { _ := mmioAddressPrefixNexusNode }
frontend.resetVectorSinkNode := resetVectorNexusNode
nPTWPorts += 1
// This should be a None in the case of not having an ITIM address, when we
// don't actually use the device that is instantiated in the frontend.
private val deviceOpt = if (tileParams.icache.get.itimAddr.isDefined) Some(frontend.icache.device) else None
}
trait HasICacheFrontendModule extends CanHavePTWModule {
val outer: HasICacheFrontend
ptwPorts += outer.frontend.module.io.ptw
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File RocketCore.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.withClock
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
import scala.collection.mutable.ArrayBuffer
case class RocketCoreParams(
xLen: Int = 64,
pgLevels: Int = 3, // sv39 default
bootFreqHz: BigInt = 0,
useVM: Boolean = true,
useUser: Boolean = false,
useSupervisor: Boolean = false,
useHypervisor: Boolean = false,
useDebug: Boolean = true,
useAtomics: Boolean = true,
useAtomicsOnlyForIO: Boolean = false,
useCompressed: Boolean = true,
useRVE: Boolean = false,
useConditionalZero: Boolean = false,
useZba: Boolean = false,
useZbb: Boolean = false,
useZbs: Boolean = false,
nLocalInterrupts: Int = 0,
useNMI: Boolean = false,
nBreakpoints: Int = 1,
useBPWatch: Boolean = false,
mcontextWidth: Int = 0,
scontextWidth: Int = 0,
nPMPs: Int = 8,
nPerfCounters: Int = 0,
haveBasicCounters: Boolean = true,
haveCFlush: Boolean = false,
misaWritable: Boolean = true,
nL2TLBEntries: Int = 0,
nL2TLBWays: Int = 1,
nPTECacheEntries: Int = 8,
mtvecInit: Option[BigInt] = Some(BigInt(0)),
mtvecWritable: Boolean = true,
fastLoadWord: Boolean = true,
fastLoadByte: Boolean = false,
branchPredictionModeCSR: Boolean = false,
clockGate: Boolean = false,
mvendorid: Int = 0, // 0 means non-commercial implementation
mimpid: Int = 0x20181004, // release date in BCD
mulDiv: Option[MulDivParams] = Some(MulDivParams()),
fpu: Option[FPUParams] = Some(FPUParams()),
debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB
haveCease: Boolean = true, // non-standard CEASE instruction
haveSimTimeout: Boolean = true, // add plusarg for simulation timeout
vector: Option[RocketCoreVectorParams] = None
) extends CoreParams {
val lgPauseCycles = 5
val haveFSDirty = false
val pmpGranularity: Int = if (useHypervisor) 4096 else 4
val fetchWidth: Int = if (useCompressed) 2 else 1
// fetchWidth doubled, but coreInstBytes halved, for RVC:
val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1)
val retireWidth: Int = 1
val instBits: Int = if (useCompressed) 16 else 32
val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop
val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace
override val useVector = vector.isDefined
override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false)
override def vLen = vector.map(_.vLen).getOrElse(0)
override def eLen = vector.map(_.eLen).getOrElse(0)
override def vfLen = vector.map(_.vfLen).getOrElse(0)
override def vfh = vector.map(_.vfh).getOrElse(false)
override def vExts = vector.map(_.vExts).getOrElse(Nil)
override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0)
override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction
override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32)
override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs
}
trait HasRocketCoreParameters extends HasCoreParameters {
lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams]
val fastLoadWord = rocketParams.fastLoadWord
val fastLoadByte = rocketParams.fastLoadByte
val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this
require(!fastLoadByte || fastLoadWord)
require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty")
}
class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters {
override def bpmCSR = {
rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0))))
}
private def haveDCache = tileParams.dcache.get.scratch.isEmpty
override def chickenCSR = {
val mask = BigInt(
tileParams.dcache.get.clockGate.toInt << 0 |
rocketParams.clockGate.toInt << 1 |
rocketParams.clockGate.toInt << 2 |
1 << 3 | // disableSpeculativeICacheRefill
haveDCache.toInt << 9 | // suppressCorruptOnGrantData
tileParams.icache.get.prefetch.toInt << 17
)
Some(CustomCSR(chickenCSRId, mask, Some(mask)))
}
def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B)
def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1))
def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid))
// mimpid encodes a release version in the form of a BCD-encoded datestamp.
def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid))
override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid
}
class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) {
val buserror = Option.when(hasBeu)(Bool())
}
trait HasRocketCoreIO extends HasRocketCoreParameters {
implicit val p: Parameters
def nTotalRoCCCSRs: Int
val io = IO(new CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val reset_vector = Input(UInt(resetVectorLen.W))
val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined))
val imem = new FrontendIO
val dmem = new HellaCacheIO
val ptw = Flipped(new DatapathPTWIO())
val fpu = Flipped(new FPUCoreIO())
val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs))
val trace = Output(new TraceBundle)
val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth)))
val cease = Output(Bool())
val wfi = Output(Bool())
val traceStall = Input(Bool())
val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None
})
}
class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
with HasRocketCoreParameters
with HasRocketCoreIO {
def nTotalRoCCCSRs = tile.roccCSRs.flatten.size
import ALU._
val clock_en_reg = RegInit(true.B)
val long_latency_stall = Reg(Bool())
val id_reg_pause = Reg(Bool())
val imem_might_request_reg = Reg(Bool())
val clock_en = WireDefault(true.B)
val gated_clock =
if (!rocketParams.clockGate) clock
else ClockGate(clock, clock_en, "rocket_clock_gate")
class RocketImpl { // entering gated-clock domain
// performance counters
def pipelineIDToWB[T <: Data](x: T): T =
RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid)
val perfEvents = new EventSets(Seq(
new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq(
("exception", () => false.B),
("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp),
("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp),
("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) || id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))),
("system", () => id_ctrl.csr =/= CSR.N),
("arith", () => id_ctrl.wxd && !(id_ctrl.jal || id_ctrl.jalr || id_ctrl.mem || id_ctrl.fp || id_ctrl.mul || id_ctrl.div || id_ctrl.csr =/= CSR.N)),
("branch", () => id_ctrl.branch),
("jal", () => id_ctrl.jal),
("jalr", () => id_ctrl.jalr))
++ (if (!usingMulDiv) Seq() else Seq(
("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV),
("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV)))
++ (if (!usingFPU) Seq() else Seq(
("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen),
("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen),
("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23),
("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3),
("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3),
("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div || io.fpu.dec.sqrt)),
("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst || io.fpu.dec.fma || io.fpu.dec.div || io.fpu.dec.sqrt))))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("load-use interlock", () => id_ex_hazard && ex_ctrl.mem || id_mem_hazard && mem_ctrl.mem || id_wb_hazard && wb_ctrl.mem),
("long-latency interlock", () => id_sboard_hazard),
("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N || id_mem_hazard && mem_ctrl.csr =/= CSR.N || id_wb_hazard && wb_ctrl.csr =/= CSR.N),
("I$ blocked", () => icache_blocked),
("D$ blocked", () => id_ctrl.mem && dcache_blocked),
("branch misprediction", () => take_pc_mem && mem_direction_misprediction),
("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked),
("flush", () => wb_reg_flush_pipe),
("replay", () => replay_wb))
++ (if (!usingMulDiv) Seq() else Seq(
("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul || ex_ctrl.div) || id_mem_hazard && (mem_ctrl.mul || mem_ctrl.div) || id_wb_hazard && wb_ctrl.div)))
++ (if (!usingFPU) Seq() else Seq(
("fp interlock", () => id_ex_hazard && ex_ctrl.fp || id_mem_hazard && mem_ctrl.fp || id_wb_hazard && wb_ctrl.fp || id_ctrl.fp && id_stall_fpu)))),
new EventSet((mask, hits) => (mask & hits).orR, Seq(
("I$ miss", () => io.imem.perf.acquire),
("D$ miss", () => io.dmem.perf.acquire),
("D$ release", () => io.dmem.perf.release),
("ITLB miss", () => io.imem.perf.tlbMiss),
("DTLB miss", () => io.dmem.perf.tlbMiss),
("L2 TLB miss", () => io.ptw.perf.l2miss)))))
val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen
val decode_table = {
(if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++:
(if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++:
(if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++:
(if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++:
(if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++:
(usingRoCC.option(new RoCCDecode)) ++:
(if (xLen == 32) new I32Decode else new I64Decode) +:
(usingVM.option(new SVMDecode)) ++:
(usingSupervisor.option(new SDecode)) ++:
(usingHypervisor.option(new HypervisorDecode)) ++:
((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++:
(usingDebug.option(new DebugDecode)) ++:
(usingNMI.option(new NMIDecode)) ++:
(usingConditionalZero.option(new ConditionalZeroDecode)) ++:
Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++:
coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++:
rocketParams.haveCease.option(new CeaseDecode) ++:
usingVector.option(new VCFGDecode) ++:
(if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++:
(if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++:
coreParams.useZbs.option(new ZbsDecode) ++:
Seq(new IDecode)
} flatMap(_.table)
val ex_ctrl = Reg(new IntCtrlSigs)
val mem_ctrl = Reg(new IntCtrlSigs)
val wb_ctrl = Reg(new IntCtrlSigs)
val ex_reg_xcpt_interrupt = Reg(Bool())
val ex_reg_valid = Reg(Bool())
val ex_reg_rvc = Reg(Bool())
val ex_reg_btb_resp = Reg(new BTBResp)
val ex_reg_xcpt = Reg(Bool())
val ex_reg_flush_pipe = Reg(Bool())
val ex_reg_load_use = Reg(Bool())
val ex_reg_cause = Reg(UInt())
val ex_reg_replay = Reg(Bool())
val ex_reg_pc = Reg(UInt())
val ex_reg_mem_size = Reg(UInt())
val ex_reg_hls = Reg(Bool())
val ex_reg_inst = Reg(Bits())
val ex_reg_raw_inst = Reg(UInt())
val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val ex_reg_set_vconfig = Reg(Bool())
val mem_reg_xcpt_interrupt = Reg(Bool())
val mem_reg_valid = Reg(Bool())
val mem_reg_rvc = Reg(Bool())
val mem_reg_btb_resp = Reg(new BTBResp)
val mem_reg_xcpt = Reg(Bool())
val mem_reg_replay = Reg(Bool())
val mem_reg_flush_pipe = Reg(Bool())
val mem_reg_cause = Reg(UInt())
val mem_reg_slow_bypass = Reg(Bool())
val mem_reg_load = Reg(Bool())
val mem_reg_store = Reg(Bool())
val mem_reg_set_vconfig = Reg(Bool())
val mem_reg_sfence = Reg(Bool())
val mem_reg_pc = Reg(UInt())
val mem_reg_inst = Reg(Bits())
val mem_reg_mem_size = Reg(UInt())
val mem_reg_hls_or_dv = Reg(Bool())
val mem_reg_raw_inst = Reg(UInt())
val mem_reg_wdata = Reg(Bits())
val mem_reg_rs2 = Reg(Bits())
val mem_br_taken = Reg(Bool())
val take_pc_mem = Wire(Bool())
val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val wb_reg_valid = Reg(Bool())
val wb_reg_xcpt = Reg(Bool())
val wb_reg_replay = Reg(Bool())
val wb_reg_flush_pipe = Reg(Bool())
val wb_reg_cause = Reg(UInt())
val wb_reg_set_vconfig = Reg(Bool())
val wb_reg_sfence = Reg(Bool())
val wb_reg_pc = Reg(UInt())
val wb_reg_mem_size = Reg(UInt())
val wb_reg_hls_or_dv = Reg(Bool())
val wb_reg_hfence_v = Reg(Bool())
val wb_reg_hfence_g = Reg(Bool())
val wb_reg_inst = Reg(Bits())
val wb_reg_raw_inst = Reg(UInt())
val wb_reg_wdata = Reg(Bits())
val wb_reg_rs2 = Reg(Bits())
val take_pc_wb = Wire(Bool())
val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool()))
val take_pc_mem_wb = take_pc_wb || take_pc_mem
val take_pc = take_pc_mem_wb
// decode stage
val ibuf = Module(new IBuf)
val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
val id_inst = id_expanded_inst.map(_.bits)
ibuf.io.imem <> io.imem.resp
ibuf.io.kill := take_pc
require(decodeWidth == 1 /* TODO */ && retireWidth == decodeWidth)
require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point")
require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor")
val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table)
val lgNXRegs = if (coreParams.useRVE) 4 else 5
val regAddrMask = (1 << lgNXRegs) - 1
def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0))
val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3)
val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2)
val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1)
val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd)
val id_load_use = Wire(Bool())
val id_reg_fence = RegInit(false.B)
val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2)
val id_raddr = IndexedSeq(id_raddr1, id_raddr2)
val rf = new RegFile(regAddrMask, xLen)
val id_rs = id_raddr.map(rf.read _)
val ctrl_killd = Wire(Bool())
val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt
val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined))
val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W)
val id_system_insn = id_ctrl.csr === CSR.I
val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U
val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr))
val id_csr_flush = id_system_insn || (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush)
val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B
id_ctrl.vec := false.B
if (usingVector) {
val v_decode = rocketParams.vector.get.decoder(p)
v_decode.io.inst := id_inst(0)
v_decode.io.vconfig := csr.io.vector.get.vconfig
when (v_decode.io.legal) {
id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill
id_ctrl.fp := v_decode.io.fp
id_ctrl.rocc := false.B
id_ctrl.branch := false.B
id_ctrl.jal := false.B
id_ctrl.jalr := false.B
id_ctrl.rxs2 := v_decode.io.read_rs2
id_ctrl.rxs1 := v_decode.io.read_rs1
id_ctrl.mem := false.B
id_ctrl.rfs1 := v_decode.io.read_frs1
id_ctrl.rfs2 := false.B
id_ctrl.rfs3 := false.B
id_ctrl.wfd := v_decode.io.write_frd
id_ctrl.mul := false.B
id_ctrl.div := false.B
id_ctrl.wxd := v_decode.io.write_rd
id_ctrl.csr := CSR.N
id_ctrl.fence_i := false.B
id_ctrl.fence := false.B
id_ctrl.amo := false.B
id_ctrl.dp := false.B
id_ctrl.vec := true.B
}
}
val id_illegal_insn = !id_ctrl.legal ||
(id_ctrl.mul || id_ctrl.div) && !csr.io.status.isa('m'-'a') ||
id_ctrl.amo && !csr.io.status.isa('a'-'a') ||
id_ctrl.fp && (csr.io.decode(0).fp_illegal || (io.fpu.illegal_rm && !id_ctrl.vec)) ||
(id_ctrl.vec) && (csr.io.decode(0).vector_illegal || csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) ||
id_ctrl.dp && !csr.io.status.isa('d'-'a') ||
ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') ||
id_raddr2_illegal && id_ctrl.rxs2 ||
id_raddr1_illegal && id_ctrl.rxs1 ||
id_waddr_illegal && id_ctrl.wxd ||
id_ctrl.rocc && csr.io.decode(0).rocc_illegal ||
id_csr_en && (csr.io.decode(0).read_illegal || !id_csr_ren && csr.io.decode(0).write_illegal) ||
!ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal)
val id_virtual_insn = id_ctrl.legal &&
((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) ||
(!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal))
// stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE)
val id_amo_aq = id_inst(0)(26)
val id_amo_rl = id_inst(0)(25)
val id_fence_pred = id_inst(0)(27,24)
val id_fence_succ = id_inst(0)(23,20)
val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_aq
val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid
when (!id_mem_busy) { id_reg_fence := false.B }
val id_rocc_busy = usingRoCC.B &&
(io.rocc.busy || ex_reg_valid && ex_ctrl.rocc ||
mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc)
val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren
val id_vec_busy = io.vector.map(v => v.backend_busy || v.trap_check_busy).getOrElse(false.B)
val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence || id_csr_rocc_write) ||
id_vec_busy && id_ctrl.fence ||
id_mem_busy && (id_ctrl.amo && id_amo_rl || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc)))
val bpu = Module(new BreakpointUnit(nBreakpoints))
bpu.io.status := csr.io.status
bpu.io.bp := csr.io.bp
bpu.io.pc := ibuf.io.pc
bpu.io.ea := mem_reg_wdata
bpu.io.mcontext := csr.io.mcontext
bpu.io.scontext := csr.io.scontext
val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0
val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1
val (id_xcpt, id_cause) = checkExceptions(List(
(csr.io.interrupt, csr.io.interrupt_cause),
(bpu.io.debug_if, CSR.debugTriggerCause.U),
(bpu.io.xcpt_if, Causes.breakpoint.U),
(id_xcpt0.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt0.ae.inst, Causes.fetch_access.U),
(id_xcpt1.pf.inst, Causes.fetch_page_fault.U),
(id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U),
(id_xcpt1.ae.inst, Causes.fetch_access.U),
(id_virtual_insn, Causes.virtual_instruction.U),
(id_illegal_insn, Causes.illegal_instruction.U)))
val idCoverCauses = List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.fetch_access, "FETCH_ACCESS"),
(Causes.illegal_instruction, "ILLEGAL_INSTRUCTION")
) ++ (if (usingVM) List(
(Causes.fetch_page_fault, "FETCH_PAGE_FAULT")
) else Nil)
coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
val dcache_bypass_data =
if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
else wb_reg_wdata
// detect bypass opportunities
val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U
val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U
val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U
val bypass_sources = IndexedSeq(
(true.B, 0.U, 0.U), // treat reading x0 as a bypass
(ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata),
(mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data))
val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr))
// execute stage
val bypass_mux = bypass_sources.map(_._3)
val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool()))
val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W)))
val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt()))
val ex_rs = for (i <- 0 until id_raddr.size)
yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst)
val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13)
val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq(
A1_RS1 -> ex_rs(0).asSInt,
A1_PC -> ex_reg_pc.asSInt,
A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S)
))
val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt
val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq(
A2_RS2 -> ex_rs(1).asSInt,
A2_IMM -> ex_imm,
A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S),
) ++ (if (coreParams.useZbs) Seq(
A2_RS2OH -> ex_op2_oh,
A2_IMMOH -> ex_op2_oh,
) else Nil))
val (ex_new_vl, ex_new_vconfig) = if (usingVector) {
val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq(
ex_reg_inst(31,30).andR -> ex_reg_inst(29,20),
!ex_reg_inst(31) -> ex_reg_inst(30,20))))
val ex_avl = Mux(ex_ctrl.rxs1,
Mux(ex_reg_inst(19,15) === 0.U,
Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax),
ex_rs(0)
),
ex_reg_inst(19,15))
val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B)
val ex_new_vconfig = Wire(new VConfig)
ex_new_vconfig.vtype := ex_new_vtype
ex_new_vconfig.vl := ex_new_vl
(Some(ex_new_vl), Some(ex_new_vconfig))
} else { (None, None) }
val alu = Module(new ALU)
alu.io.dw := ex_ctrl.alu_dw
alu.io.fn := ex_ctrl.alu_fn
alu.io.in2 := ex_op2.asUInt
alu.io.in1 := ex_op1.asUInt
// multiplier and divider
val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen))
div.io.req.valid := ex_reg_valid && ex_ctrl.div
div.io.req.bits.dw := ex_ctrl.alu_dw
div.io.req.bits.fn := ex_ctrl.alu_fn
div.io.req.bits.in1 := ex_rs(0)
div.io.req.bits.in2 := ex_rs(1)
div.io.req.bits.tag := ex_waddr
val mul = pipelinedMul.option {
val m = Module(new PipelinedMultiplier(xLen, 2))
m.io.req.valid := ex_reg_valid && ex_ctrl.mul
m.io.req.bits := div.io.req.bits
m
}
ex_reg_valid := !ctrl_killd
ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay
ex_reg_xcpt := !ctrl_killd && id_xcpt
ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt
when (!ctrl_killd) {
ex_ctrl := id_ctrl
ex_reg_rvc := ibuf.io.inst(0).bits.rvc
ex_ctrl.csr := id_csr
when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B }
when (id_fence_next) { id_reg_fence := true.B }
when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr
ex_ctrl.alu_fn := FN_ADD
ex_ctrl.alu_dw := DW_XPR
ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction
ex_ctrl.sel_alu2 := A2_ZERO
when (id_xcpt1.asUInt.orR) { // badaddr := PC+2
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_SIZE
ex_reg_rvc := true.B
}
when (bpu.io.xcpt_if || id_xcpt0.asUInt.orR) { // badaddr := PC
ex_ctrl.sel_alu1 := A1_PC
ex_ctrl.sel_alu2 := A2_ZERO
}
}
ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush
ex_reg_load_use := id_load_use
ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX)
ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12))
when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) {
ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U)
}
when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) {
ex_ctrl.mem_cmd := M_HFENCEV
}
if (tile.dcache.flushOnFenceI) {
when (id_ctrl.fence_i) {
ex_reg_mem_size := 0.U
}
}
for (i <- 0 until id_raddr.size) {
val do_bypass = id_bypass_src(i).reduce(_||_)
val bypass_src = PriorityEncoder(id_bypass_src(i))
ex_reg_rs_bypass(i) := do_bypass
ex_reg_rs_lsb(i) := bypass_src
when (id_ren(i) && !do_bypass) {
ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size)
}
}
when (id_illegal_insn || id_virtual_insn) {
val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))
ex_reg_rs_bypass(0) := false.B
ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
}
}
when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
ex_reg_cause := id_cause
ex_reg_inst := id_inst(0)
ex_reg_raw_inst := id_raw_inst(0)
ex_reg_pc := ibuf.io.pc
ex_reg_btb_resp := ibuf.io.btb_resp
ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) }
ex_reg_set_vconfig := id_set_vconfig && !id_xcpt
}
// replay inst in ex stage?
val ex_pc_valid = ex_reg_valid || ex_reg_replay || ex_reg_xcpt_interrupt
val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid
val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready ||
ex_ctrl.div && !div.io.req.ready ||
ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B)
val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use
val replay_ex = ex_reg_replay || (ex_reg_valid && (replay_ex_structural || replay_ex_load_use))
val ctrl_killx = take_pc_mem_wb || replay_ex || !ex_reg_valid
// detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || ex_reg_mem_size < 2.U
val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE || ex_ctrl.mem_cmd === M_HFENCEV || ex_ctrl.mem_cmd === M_HFENCEG)
val (ex_xcpt, ex_cause) = checkExceptions(List(
(ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause)))
val exCoverCauses = idCoverCauses
coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses)
// memory stage
val mem_pc_valid = mem_reg_valid || mem_reg_replay || mem_reg_xcpt_interrupt
val mem_br_target = mem_reg_pc.asSInt +
Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst),
Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst),
Mux(mem_reg_rvc, 2.S, 4.S)))
val mem_npc = (Mux(mem_ctrl.jalr || mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt
val mem_wrong_npc =
Mux(ex_pc_valid, mem_npc =/= ex_reg_pc,
Mux(ibuf.io.inst(0).valid || ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B))
val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence
val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt
val mem_cfi = mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal
val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal
val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken)
val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken
take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction || mem_reg_sfence)
mem_reg_valid := !ctrl_killx
mem_reg_replay := !take_pc_mem_wb && replay_ex
mem_reg_xcpt := !ctrl_killx && ex_xcpt
mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt
// on pipeline flushes, cause mem_npc to hold the sequential npc, which
// will drive the W-stage npc mux
when (mem_reg_valid && mem_reg_flush_pipe) {
mem_reg_sfence := false.B
}.elsewhen (ex_pc_valid) {
mem_ctrl := ex_ctrl
mem_reg_rvc := ex_reg_rvc
mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd)
mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd)
mem_reg_sfence := ex_sfence
mem_reg_btb_resp := ex_reg_btb_resp
mem_reg_flush_pipe := ex_reg_flush_pipe
mem_reg_slow_bypass := ex_slow_bypass
mem_reg_wphit := ex_reg_wphit
mem_reg_set_vconfig := ex_reg_set_vconfig
mem_reg_cause := ex_cause
mem_reg_inst := ex_reg_inst
mem_reg_raw_inst := ex_reg_raw_inst
mem_reg_mem_size := ex_reg_mem_size
mem_reg_hls_or_dv := io.dmem.req.bits.dv
mem_reg_pc := ex_reg_pc
// IDecode ensured they are 1H
mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out)
mem_br_taken := alu.io.cmp_out
when (ex_ctrl.rxs2 && (ex_ctrl.mem || ex_ctrl.rocc || ex_sfence)) {
val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size)
mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data
}
if (usingVector) { when (ex_reg_set_vconfig) {
mem_reg_rs2 := ex_new_vconfig.get.asUInt
} }
when (ex_ctrl.jalr && csr.io.status.debug) {
// flush I$ on D-mode JALR to effect uncached fetch without D$ flush
mem_ctrl.fence_i := true.B
mem_reg_flush_pipe := true.B
}
}
val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) || (mem_reg_store && bpu.io.xcpt_st)
val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) || (mem_reg_store && bpu.io.debug_st)
val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List(
(mem_debug_breakpoint, CSR.debugTriggerCause.U),
(mem_breakpoint, Causes.breakpoint.U)))
val (mem_xcpt, mem_cause) = checkExceptions(List(
(mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause),
(mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U),
(mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause)))
val memCoverCauses = (exCoverCauses ++ List(
(CSR.debugTriggerCause, "DEBUG_TRIGGER"),
(Causes.breakpoint, "BREAKPOINT"),
(Causes.misaligned_fetch, "MISALIGNED_FETCH")
)).distinct
coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses)
val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port
val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem
val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B)
val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B)
val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem || vec_kill_mem || vec_kill_all
val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid
div.io.kill := killm_common && RegNext(div.io.req.fire)
val ctrl_killm = killm_common || mem_xcpt || fpu_kill_mem || vec_kill_mem
// writeback stage
wb_reg_valid := !ctrl_killm
wb_reg_replay := replay_mem && !take_pc_wb
wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B)
wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe
when (mem_pc_valid) {
wb_ctrl := mem_ctrl
wb_reg_sfence := mem_reg_sfence
wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
when (mem_ctrl.rocc || mem_reg_sfence || mem_reg_set_vconfig) {
wb_reg_rs2 := mem_reg_rs2
}
wb_reg_cause := mem_cause
wb_reg_inst := mem_reg_inst
wb_reg_raw_inst := mem_reg_raw_inst
wb_reg_mem_size := mem_reg_mem_size
wb_reg_hls_or_dv := mem_reg_hls_or_dv
wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV
wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG
wb_reg_pc := mem_reg_pc
wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) }
wb_reg_set_vconfig := mem_reg_set_vconfig
}
val (wb_xcpt, wb_cause) = checkExceptions(List(
(wb_reg_xcpt, wb_reg_cause),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U),
(wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U)
))
val wbCoverCauses = List(
(Causes.misaligned_store, "MISALIGNED_STORE"),
(Causes.misaligned_load, "MISALIGNED_LOAD"),
(Causes.store_access, "STORE_ACCESS"),
(Causes.load_access, "LOAD_ACCESS")
) ++ (if(usingVM) List(
(Causes.store_page_fault, "STORE_PAGE_FAULT"),
(Causes.load_page_fault, "LOAD_PAGE_FAULT")
) else Nil) ++ (if (usingHypervisor) List(
(Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"),
(Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"),
) else Nil)
coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses)
val wb_pc_valid = wb_reg_valid || wb_reg_replay || wb_reg_xcpt
val wb_wxd = wb_reg_valid && wb_ctrl.wxd
val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc || wb_ctrl.vec
val replay_wb_common = io.dmem.s2_nack || wb_reg_replay
val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready
val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall
val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B)
val replay_wb = replay_wb_common || replay_wb_rocc || replay_wb_csr || replay_wb_vec
take_pc_wb := replay_wb || wb_xcpt || csr.io.eret || wb_reg_flush_pipe
// writeback arbitration
val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool
val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool
val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1)
val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data
val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay
class LLWB extends Bundle {
val data = UInt(xLen.W)
val tag = UInt(5.W)
}
val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec
ll_arb.io.in.foreach(_.valid := false.B)
ll_arb.io.in.foreach(_.bits := DontCare)
val ll_wdata = WireInit(ll_arb.io.out.bits.data)
val ll_waddr = WireInit(ll_arb.io.out.bits.tag)
val ll_wen = WireInit(ll_arb.io.out.fire)
ll_arb.io.out.ready := !wb_wxd
div.io.resp.ready := ll_arb.io.in(0).ready
ll_arb.io.in(0).valid := div.io.resp.valid
ll_arb.io.in(0).bits.data := div.io.resp.bits.data
ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag
if (usingRoCC) {
io.rocc.resp.ready := ll_arb.io.in(1).ready
ll_arb.io.in(1).valid := io.rocc.resp.valid
ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data
ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd
} else {
// tie off RoCC
io.rocc.resp.ready := false.B
io.rocc.mem.req.ready := false.B
}
io.vector.map { v =>
v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready)
ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp
ll_arb.io.in(2).bits.data := v.resp.bits.data
ll_arb.io.in(2).bits.tag := v.resp.bits.rd
}
// Dont care mem since not all RoCC need accessing memory
io.rocc.mem := DontCare
when (dmem_resp_replay && dmem_resp_xpu) {
ll_arb.io.out.ready := false.B
ll_waddr := dmem_resp_waddr
ll_wen := true.B
}
val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt
val wb_wen = wb_valid && wb_ctrl.wxd
val rf_wen = wb_wen || ll_wen
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
Mux(ll_wen, ll_wdata,
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata),
wb_reg_wdata))))
when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
// hook up control/status regfile
csr.io.ungated_clock := clock
csr.io.decode(0).inst := id_inst(0)
csr.io.exception := wb_xcpt
csr.io.cause := wb_cause
csr.io.retire := wb_valid
csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst)
csr.io.interrupts := io.interrupts
csr.io.hartid := io.hartid
io.fpu.fcsr_rm := csr.io.fcsr_rm
val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W))
val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B)
csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid | vector_fcsr_flags_valid
csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) | (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid))
io.fpu.time := csr.io.time(31,0)
io.fpu.hartid := io.hartid
csr.io.rocc_interrupt := io.rocc.interrupt
csr.io.pc := wb_reg_pc
val tval_dmem_addr = !wb_reg_xcpt
val tval_any_addr = tval_dmem_addr ||
wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U)
val tval_inst = wb_reg_cause === Causes.illegal_instruction.U
val tval_valid = wb_xcpt && (tval_any_addr || tval_inst)
csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v || tval_dmem_addr && wb_reg_hls_or_dv)
csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U)
val (htval, mhtinst_read_pseudo) = {
val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U
val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U)
assert(!htval_valid_imem || io.imem.gpa.valid)
val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR
val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U)
val htval = (htval_dmem | htval_imem) >> hypervisorExtraAddrBits
// read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation
val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) || (io.dmem.s2_gpa_is_pte && htval_valid_dmem)
(htval, mhtinst_read_pseudo)
}
csr.io.vector.foreach { v =>
v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid
v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig)
v.set_vs_dirty := wb_valid && wb_ctrl.vec
v.set_vstart.valid := wb_valid && wb_reg_set_vconfig
v.set_vstart.bits := 0.U
}
io.vector.foreach { v =>
when (v.wb.retire || v.wb.xcpt || wb_ctrl.vec) {
csr.io.pc := v.wb.pc
csr.io.retire := v.wb.retire
csr.io.inst(0) := v.wb.inst
when (v.wb.xcpt && !wb_reg_xcpt) {
wb_xcpt := true.B
wb_cause := v.wb.cause
csr.io.tval := v.wb.tval
}
}
v.wb.store_pending := io.dmem.store_pending
v.wb.vxrm := csr.io.vector.get.vxrm
v.wb.frm := csr.io.fcsr_rm
csr.io.vector.get.set_vxsat := v.set_vxsat
when (v.set_vconfig.valid) {
csr.io.vector.get.set_vconfig.valid := true.B
csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits
}
when (v.set_vstart.valid) {
csr.io.vector.get.set_vstart.valid := true.B
csr.io.vector.get.set_vstart.bits := v.set_vstart.bits
}
}
csr.io.htval := htval
csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo
io.ptw.ptbr := csr.io.ptbr
io.ptw.hgatp := csr.io.hgatp
io.ptw.vsatp := csr.io.vsatp
(io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs }
io.ptw.status := csr.io.status
io.ptw.hstatus := csr.io.hstatus
io.ptw.gstatus := csr.io.gstatus
io.ptw.pmp := csr.io.pmp
csr.io.rw.addr := wb_reg_inst(31,20)
csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr)
csr.io.rw.wdata := wb_reg_wdata
io.rocc.csrs <> csr.io.roccCSRs
io.trace.time := csr.io.time
io.trace.insns := csr.io.trace
if (rocketParams.debugROB.isDefined) {
val sz = rocketParams.debugROB.get.size
if (sz < 1) { // use unsynthesizable ROB
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val should_wb = WireInit((wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception)
val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard)
val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U))
io.vector.foreach { v => when (v.wb.retire) {
should_wb := v.wb.rob_should_wb
has_wb := false.B
wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7))
}}
DebugROB.pushTrace(clock, reset,
io.hartid, csr_trace_with_wdata,
should_wb, has_wb, wb_addr)
io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid)
DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata)
} else { // synthesizable ROB (no FPRs)
require(!usingVector, "Synthesizable ROB does not support vector implementations")
val csr_trace_with_wdata = WireInit(csr.io.trace(0))
csr_trace_with_wdata.wdata.get := rf_wdata
val debug_rob = Module(new HardDebugROB(sz, 32))
debug_rob.io.i_insn := csr_trace_with_wdata
debug_rob.io.should_wb := (wb_ctrl.wfd || (wb_ctrl.wxd && wb_waddr =/= 0.U)) &&
!csr.io.trace(0).exception
debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard
debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)
debug_rob.io.wb_val := ll_wen
debug_rob.io.wb_tag := rf_waddr
debug_rob.io.wb_data := rf_wdata
io.trace.insns(0) := debug_rob.io.o_insn
}
} else {
io.trace.insns := csr.io.trace
}
for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) {
iobpw.valid(0) := wphit
iobpw.action := bp.control.action
// tie off bpwatch valids
iobpw.rvalid.foreach(_ := false.B)
iobpw.wvalid.foreach(_ := false.B)
iobpw.ivalid.foreach(_ := false.B)
}
val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1),
(id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2),
(id_ctrl.wxd && id_waddr =/= 0.U, id_waddr))
val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1),
(io.fpu.dec.ren2, id_raddr2),
(io.fpu.dec.ren3, id_raddr3),
(io.fpu.dec.wen, id_waddr))
val sboard = new Scoreboard(32, true)
sboard.clear(ll_wen, ll_waddr)
def id_sboard_clear_bypass(r: UInt) = {
// ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check
if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r
else div.io.resp.fire && div.io.resp.bits.tag === r || dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r
}
val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd))
sboard.set(wb_set_sboard && wb_wen, wb_waddr)
// stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage.
val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.mul || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc || ex_ctrl.vec
val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr)
val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr)
val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex)
// stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage.
val mem_mem_cmd_bh =
if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass
else true.B
val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.mul || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc || mem_ctrl.vec
val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr)
val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr)
val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem)
id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem
val id_vconfig_hazard = id_ctrl.vec && (
(ex_reg_valid && ex_reg_set_vconfig) ||
(mem_reg_valid && mem_reg_set_vconfig) ||
(wb_reg_valid && wb_reg_set_vconfig))
// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr)
val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr)
val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb)
val id_stall_fpu = if (usingFPU) {
val fp_sboard = new Scoreboard(32)
fp_sboard.set(((wb_dcache_miss || wb_ctrl.vec) && wb_ctrl.wfd || io.fpu.sboard_set) && wb_valid, wb_waddr)
val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B)
fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) || v_ll, io.fpu.ll_resp_tag)
fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
checkHazards(fp_hazard_targets, fp_sboard.read _)
} else false.B
val dcache_blocked = {
// speculate that a blocked D$ will unblock the cycle after a Grant
val blocked = Reg(Bool())
blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked || io.dmem.req.valid || io.dmem.s2_nack)
blocked && !io.dmem.perf.grant
}
val rocc_blocked = Reg(Bool())
rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked)
val ctrl_stalld =
id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
id_vconfig_hazard ||
csr.io.singleStep && (ex_reg_valid || mem_reg_valid || wb_reg_valid) ||
id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy ||
id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy ||
id_ctrl.fp && id_stall_fpu ||
id_ctrl.mem && dcache_blocked || // reduce activity during D$ misses
id_ctrl.rocc && rocc_blocked || // reduce activity while RoCC is busy
id_ctrl.div && (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid) || // reduce odds of replay
!clock_en ||
id_do_fence ||
csr.io.csr_stall ||
id_reg_pause ||
io.traceStall
ctrl_killd := !ibuf.io.inst(0).valid || ibuf.io.inst(0).bits.replay || take_pc_mem_wb || ctrl_stalld || csr.io.interrupt
io.imem.req.valid := take_pc
io.imem.req.bits.speculative := !take_pc_wb
io.imem.req.bits.pc :=
Mux(wb_xcpt || csr.io.eret, csr.io.evec, // exception or [m|s]ret
Mux(replay_wb, wb_reg_pc, // replay
mem_npc)) // flush or branch misprediction
io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack
io.imem.might_request := {
imem_might_request_reg := ex_pc_valid || mem_pc_valid || io.ptw.customCSRs.disableICacheClockGate || io.vector.map(_.trap_check_busy).getOrElse(false.B)
imem_might_request_reg
}
io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common)
io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence
io.imem.sfence.bits.rs1 := wb_reg_mem_size(0)
io.imem.sfence.bits.rs2 := wb_reg_mem_size(1)
io.imem.sfence.bits.addr := wb_reg_wdata
io.imem.sfence.bits.asid := wb_reg_rs2
io.imem.sfence.bits.hv := wb_reg_hfence_v
io.imem.sfence.bits.hg := wb_reg_hfence_g
io.ptw.sfence := io.imem.sfence
ibuf.io.inst(0).ready := !ctrl_stalld
io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi || mem_cfi_taken)
io.imem.btb_update.bits.isValid := mem_cfi
io.imem.btb_update.bits.cfiType :=
Mux((mem_ctrl.jal || mem_ctrl.jalr) && mem_waddr(0), CFIType.call,
Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret,
Mux(mem_ctrl.jal || mem_ctrl.jalr, CFIType.jump,
CFIType.branch)))
io.imem.btb_update.bits.target := io.imem.req.bits.pc
io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc)
io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc | (coreInstBytes*fetchWidth-1).U)
io.imem.btb_update.bits.prediction := mem_reg_btb_resp
io.imem.btb_update.bits.taken := DontCare
io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb
io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc
io.imem.bht_update.bits.taken := mem_br_taken
io.imem.bht_update.bits.mispredict := mem_wrong_npc
io.imem.bht_update.bits.branch := mem_ctrl.branch
io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht
// Connect RAS in Frontend
io.imem.ras_update := DontCare
io.fpu.valid := !ctrl_killd && id_ctrl.fp
io.fpu.killx := ctrl_killx
io.fpu.killm := killm_common
io.fpu.inst := id_inst(0)
io.fpu.fromint_data := ex_rs(0)
io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu
io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data)
io.fpu.ll_resp_type := io.dmem.resp.bits.size
io.fpu.ll_resp_tag := dmem_resp_waddr
io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate
io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U)
io.vector.map { v =>
when (!(dmem_resp_valid && dmem_resp_fpu)) {
io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp
io.fpu.ll_resp_data := v.resp.bits.data
io.fpu.ll_resp_type := v.resp.bits.size
io.fpu.ll_resp_tag := v.resp.bits.rd
}
}
io.vector.foreach { v =>
v.ex.valid := ex_reg_valid && (ex_ctrl.vec || rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx
v.ex.inst := ex_reg_inst
v.ex.vconfig := csr.io.vector.get.vconfig
v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec || wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart)
v.ex.rs1 := ex_rs(0)
v.ex.rs2 := ex_rs(1)
v.ex.pc := ex_reg_pc
v.mem.frs1 := io.fpu.store_data
v.killm := killm_common
v.status := csr.io.status
}
io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem
val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp)
require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth)
io.dmem.req.bits.tag := ex_dcache_tag
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.size := ex_reg_mem_size
io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14))
io.dmem.req.bits.phys := false.B
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr)
io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv)
io.dmem.req.bits.dv := ex_reg_hls || csr.io.status.dv
io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) || (!ex_ctrl.fp && ex_waddr === 0.U)
io.dmem.req.bits.no_alloc := DontCare
io.dmem.req.bits.no_xcpt := DontCare
io.dmem.req.bits.data := DontCare
io.dmem.req.bits.mask := DontCare
io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2))
io.dmem.s1_data.mask := DontCare
io.dmem.s1_kill := killm_common || mem_ldst_xcpt || fpu_kill_mem || vec_kill_mem
io.dmem.s2_kill := false.B
// don't let D$ go to sleep if we're probably going to use it soon
io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
io.rocc.exception := wb_xcpt && csr.io.status.xs.orR
io.rocc.cmd.bits.status := csr.io.status
io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction())
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false.B }
io.cease := csr.io.status.cease && !clock_en_reg
io.wfi := csr.io.status.wfi
if (rocketParams.clockGate) {
long_latency_stall := csr.io.csr_stall || io.dmem.perf.blocked || id_reg_pause && !unpause
clock_en := clock_en_reg || ex_pc_valid || (!long_latency_stall && io.imem.resp.valid)
clock_en_reg :=
ex_pc_valid || mem_pc_valid || wb_pc_valid || // instruction in flight
io.ptw.customCSRs.disableCoreClockGate || // chicken bit
!div.io.req.ready || // mul/div in flight
usingFPU.B && !io.fpu.fcsr_rdy || // long-latency FPU in flight
io.dmem.replay_next || // long-latency load replaying
(!long_latency_stall && (ibuf.io.inst(0).valid || io.imem.resp.valid)) // instruction pending
assert(!(ex_pc_valid || mem_pc_valid || wb_pc_valid) || clock_en)
}
// evaluate performance counters
val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid))
csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen))
coreMonitorBundle.clock := clock
coreMonitorBundle.reset := reset
coreMonitorBundle.hartid := io.hartid
coreMonitorBundle.timer := csr.io.time(31,0)
coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception
coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen)
coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard
coreMonitorBundle.wrenf := false.B
coreMonitorBundle.wrdst := wb_waddr
coreMonitorBundle.wrdata := rf_wdata
coreMonitorBundle.rd0src := wb_reg_inst(19,15)
coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0)))
coreMonitorBundle.rd1src := wb_reg_inst(24,20)
coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1)))
coreMonitorBundle.inst := csr.io.trace(0).insn
coreMonitorBundle.excpt := csr.io.trace(0).exception
coreMonitorBundle.priv_mode := csr.io.trace(0).priv
if (enableCommitLog) {
val t = csr.io.trace(0)
val rd = wb_waddr
val wfd = wb_ctrl.wfd
val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard
when (t.valid && !t.exception) {
when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U)
}
.elsewhen (wxd && rd =/= 0.U && has_data) {
printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata)
}
.elsewhen (wxd && rd =/= 0.U && !has_data) {
printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd)
}
.otherwise {
printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn)
}
}
when (ll_wen && rf_waddr =/= 0.U) {
printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata)
}
}
else {
when (csr.io.trace(0).valid) {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
coreMonitorBundle.pc,
Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),
Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),
coreMonitorBundle.wrenx,
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),
coreMonitorBundle.inst, coreMonitorBundle.inst)
}
}
// CoreMonitorBundle for late latency writes
val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen))
xrfWriteBundle.clock := clock
xrfWriteBundle.reset := reset
xrfWriteBundle.hartid := io.hartid
xrfWriteBundle.timer := csr.io.time(31,0)
xrfWriteBundle.valid := false.B
xrfWriteBundle.pc := 0.U
xrfWriteBundle.wrdst := rf_waddr
xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr))
xrfWriteBundle.wrenf := false.B
xrfWriteBundle.wrdata := rf_wdata
xrfWriteBundle.rd0src := 0.U
xrfWriteBundle.rd0val := 0.U
xrfWriteBundle.rd1src := 0.U
xrfWriteBundle.rd1val := 0.U
xrfWriteBundle.inst := 0.U
xrfWriteBundle.excpt := false.B
xrfWriteBundle.priv_mode := csr.io.trace(0).priv
if (rocketParams.haveSimTimeout) PlusArg.timeout(
name = "max_core_cycles",
docstring = "Kill the emulation after INT rdtime cycles. Off if 0."
)(csr.io.time)
} // leaving gated-clock domain
val rocketImpl = withClock (gated_clock) { new RocketImpl }
def checkExceptions(x: Seq[(Bool, UInt)]) =
(WireInit(x.map(_._1).reduce(_||_)), WireInit(PriorityMux(x)))
def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = {
for ((coverCause, label) <- coverCausesLabels) {
property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}")
}
}
def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) =
targets.map(h => h._1 && cond(h._2)).reduce(_||_)
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else {
// efficient means to compress 64-bit VA into vaddrBits+1 bits
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1))
val b = vaddrBitsExtended-1
val a = (a0 >> b).asSInt
val msb = Mux(a === 0.S || a === -1.S, ea(b), !ea(b-1))
Cat(msb, ea(b-1, 0))
}
class Scoreboard(n: Int, zero: Boolean = false)
{
def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
def read(addr: UInt): Bool = r(addr)
def readBypassed(addr: UInt): Bool = _next(addr)
private val _r = RegInit(0.U(n.W))
private val r = if (zero) (_r >> 1 << 1) else _r
private var _next = r
private var ens = false.B
private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U)
private def update(en: Bool, update: UInt) = {
_next = update
ens = ens || en
when (ens) { _r := _next }
}
}
}
class RegFile(n: Int, w: Int, zero: Boolean = false) {
val rf = Mem(n, UInt(w.W))
private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0))
private val reads = ArrayBuffer[(UInt,UInt)]()
private var canRead = true
def read(addr: UInt) = {
require(canRead)
reads += addr -> Wire(UInt())
reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr))
reads.last._2
}
def write(addr: UInt, data: UInt) = {
canRead = false
when (addr =/= 0.U) {
access(addr) := data
for ((raddr, rdata) <- reads)
when (addr === raddr) { rdata := data }
}
}
}
object ImmGen {
def apply(sel: UInt, inst: UInt) = {
val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt)
val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign)
val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt)
val b11 = Mux(sel === IMM_U || sel === IMM_Z, 0.S,
Mux(sel === IMM_UJ, inst(20).asSInt,
Mux(sel === IMM_SB, inst(7).asSInt, sign)))
val b10_5 = Mux(sel === IMM_U || sel === IMM_Z, 0.U, inst(30,25))
val b4_1 = Mux(sel === IMM_U, 0.U,
Mux(sel === IMM_S || sel === IMM_SB, inst(11,8),
Mux(sel === IMM_Z, inst(19,16), inst(24,21))))
val b0 = Mux(sel === IMM_S, inst(7),
Mux(sel === IMM_I, inst(20),
Mux(sel === IMM_Z, inst(15), 0.U)))
Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File RVC.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class ExpandedInstruction extends Bundle {
val bits = UInt(32.W)
val rd = UInt(5.W)
val rs1 = UInt(5.W)
val rs2 = UInt(5.W)
val rs3 = UInt(5.W)
}
class RVCDecoder(x: UInt, xLen: Int, fLen: Int, useAddiForMv: Boolean = false) {
def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = {
val res = Wire(new ExpandedInstruction)
res.bits := bits
res.rd := rd
res.rs1 := rs1
res.rs2 := rs2
res.rs3 := rs3
res
}
def rs1p = Cat(1.U(2.W), x(9,7))
def rs2p = Cat(1.U(2.W), x(4,2))
def rs2 = x(6,2)
def rd = x(11,7)
def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W))
def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W))
def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W))
def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W))
def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W))
def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W))
def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W))
def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W))
def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W))
def addiImm = Cat(Fill(7, x(12)), x(6,2))
def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W))
def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W))
def shamt = Cat(x(12), x(6,2))
def x0 = 0.U(5.W)
def ra = 1.U(5.W)
def sp = 2.U(5.W)
def q0 = {
def addi4spn = {
val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p)
}
def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p)
def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
def flw = {
if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p)
else ld
}
def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p)
def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p)
def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
def fsw = {
if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p)
else sd
}
Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw)
}
def q1 = {
def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p)
def addiw = {
val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W))
inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def jal = {
if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p)
else addiw
}
def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p)
def addi16sp = {
val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W))
inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p)
}
def lui = {
val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W))
val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p)
Mux(rd === x0 || rd === sp, addi16sp, me)
}
def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p)
def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0)
def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0)
def arith = {
def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W))
def srai = srli | (1 << 30).U
def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W))
def rtype = {
val funct = Seq(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5)))
val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U)
val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W))
Cat(rs2p, rs1p, funct, rs1p, opc) | sub
}
inst(Seq(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p)
}
Seq(addi, jal, li, lui, arith, j, beqz, bnez)
}
def q2 = {
val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W))
def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2)
def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2)
def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2)
def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
def flwsp = {
if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2)
else ldsp
}
def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2)
def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
def fswsp = {
if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2)
else sdsp
}
def jalr = {
val mv = {
if (useAddiForMv) inst(Cat(rs2, 0.U(3.W), rd, 0x13.U(7.W)), rd, rs2, x0)
else inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2)
}
val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2)
val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W))
val reserved = Cat(jr >> 7, 0x1F.U(7.W))
val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2)
val jr_mv = Mux(rs2.orR, mv, jr_reserved)
val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W))
val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U
val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2)
val jalr_add = Mux(rs2.orR, add, jalr_ebreak)
Mux(x(12), jalr_add, jr_mv)
}
Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp)
}
def q3 = Seq.fill(8)(passthrough)
def passthrough = inst(x)
def decode = {
val s = q0 ++ q1 ++ q2 ++ q3
s(Cat(x(1,0), x(15,13)))
}
def q0_ill = {
def allz = !(x(12, 2).orR)
def fld = if (fLen >= 64) false.B else true.B
def flw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
def fsd = if (fLen >= 64) false.B else true.B
def fsw32 = if (xLen == 64 || fLen >= 32) false.B else true.B
Seq(allz, fld, false.B, flw32, true.B, fsd, false.B, fsw32)
}
def q1_ill = {
def rd0 = if (xLen == 32) false.B else rd === 0.U
def immz = !(x(12) | x(6, 2).orR)
def arith_res = x(12, 10).andR && (if (xLen == 32) true.B else x(6) === 1.U)
Seq(false.B, rd0, false.B, immz, arith_res, false.B, false.B, false.B)
}
def q2_ill = {
def fldsp = if (fLen >= 64) false.B else true.B
def rd0 = rd === 0.U
def flwsp = if (xLen == 64) rd0 else if (fLen >= 32) false.B else true.B
def jr_res = !(x(12 ,2).orR)
def fsdsp = if (fLen >= 64) false.B else true.B
def fswsp32 = if (xLen == 64) false.B else if (fLen >= 32) false.B else true.B
Seq(false.B, fldsp, rd0, flwsp, jr_res, fsdsp, false.B, fswsp32)
}
def q3_ill = Seq.fill(8)(false.B)
def ill = {
val s = q0_ill ++ q1_ill ++ q2_ill ++ q3_ill
s(Cat(x(1,0), x(15,13)))
}
}
class RVCExpander(useAddiForMv: Boolean = false)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(new ExpandedInstruction)
val rvc = Output(Bool())
val ill = Output(Bool())
})
if (usingCompressed) {
io.rvc := io.in(1,0) =/= 3.U
val decoder = new RVCDecoder(io.in, xLen, fLen, useAddiForMv)
io.out := decoder.decode
io.ill := decoder.ill
} else {
io.rvc := false.B
io.out := new RVCDecoder(io.in, xLen, fLen, useAddiForMv).passthrough
io.ill := false.B // only used for RVC
}
}
| module Frontend( // @[Frontend.scala:82:7]
input clock, // @[Frontend.scala:82:7]
input reset, // @[Frontend.scala:82:7]
input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_cpu_might_request, // @[Frontend.scala:85:14]
input io_cpu_req_valid, // @[Frontend.scala:85:14]
input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14]
input io_cpu_sfence_valid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14]
input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_asid, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hv, // @[Frontend.scala:85:14]
input io_cpu_sfence_bits_hg, // @[Frontend.scala:85:14]
input io_cpu_resp_ready, // @[Frontend.scala:85:14]
output io_cpu_resp_valid, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_cfiType, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_btb_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14]
output [38:0] io_cpu_resp_bits_btb_target, // @[Frontend.scala:85:14]
output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14]
output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_btb_bht_value, // @[Frontend.scala:85:14]
output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14]
output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14]
output [1:0] io_cpu_resp_bits_mask, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14]
output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14]
output io_cpu_gpa_valid, // @[Frontend.scala:85:14]
output [39:0] io_cpu_gpa_bits, // @[Frontend.scala:85:14]
output io_cpu_gpa_is_pte, // @[Frontend.scala:85:14]
input io_cpu_btb_update_valid, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:85:14]
input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14]
input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:85:14]
input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14]
input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14]
input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14]
input io_cpu_bht_update_valid, // @[Frontend.scala:85:14]
input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:85:14]
input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14]
input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14]
input io_cpu_flush_icache, // @[Frontend.scala:85:14]
output [39:0] io_cpu_npc, // @[Frontend.scala:85:14]
output io_cpu_perf_acquire, // @[Frontend.scala:85:14]
output io_cpu_perf_tlbMiss, // @[Frontend.scala:85:14]
input io_cpu_progress, // @[Frontend.scala:85:14]
input io_ptw_req_ready, // @[Frontend.scala:85:14]
output io_ptw_req_valid, // @[Frontend.scala:85:14]
output io_ptw_req_bits_valid, // @[Frontend.scala:85:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14]
output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14]
input io_ptw_resp_valid, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:85:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14]
input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:85:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:85:14]
input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:85:14]
input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14]
input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:85:14]
input io_ptw_status_debug, // @[Frontend.scala:85:14]
input io_ptw_status_cease, // @[Frontend.scala:85:14]
input io_ptw_status_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_status_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_dprv, // @[Frontend.scala:85:14]
input io_ptw_status_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14]
input io_ptw_status_v, // @[Frontend.scala:85:14]
input io_ptw_status_sd, // @[Frontend.scala:85:14]
input io_ptw_status_mpv, // @[Frontend.scala:85:14]
input io_ptw_status_gva, // @[Frontend.scala:85:14]
input io_ptw_status_tsr, // @[Frontend.scala:85:14]
input io_ptw_status_tw, // @[Frontend.scala:85:14]
input io_ptw_status_tvm, // @[Frontend.scala:85:14]
input io_ptw_status_mxr, // @[Frontend.scala:85:14]
input io_ptw_status_sum, // @[Frontend.scala:85:14]
input io_ptw_status_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_status_mpp, // @[Frontend.scala:85:14]
input io_ptw_status_spp, // @[Frontend.scala:85:14]
input io_ptw_status_mpie, // @[Frontend.scala:85:14]
input io_ptw_status_spie, // @[Frontend.scala:85:14]
input io_ptw_status_mie, // @[Frontend.scala:85:14]
input io_ptw_status_sie, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spvp, // @[Frontend.scala:85:14]
input io_ptw_hstatus_spv, // @[Frontend.scala:85:14]
input io_ptw_hstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_debug, // @[Frontend.scala:85:14]
input io_ptw_gstatus_cease, // @[Frontend.scala:85:14]
input io_ptw_gstatus_wfi, // @[Frontend.scala:85:14]
input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_dv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_v, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sd, // @[Frontend.scala:85:14]
input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpv, // @[Frontend.scala:85:14]
input io_ptw_gstatus_gva, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mbe, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sbe, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:85:14]
input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tsr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tw, // @[Frontend.scala:85:14]
input io_ptw_gstatus_tvm, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mxr, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sum, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mprv, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_fs, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:85:14]
input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spp, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mpie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_ube, // @[Frontend.scala:85:14]
input io_ptw_gstatus_spie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_upie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_mie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_hie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_sie, // @[Frontend.scala:85:14]
input io_ptw_gstatus_uie, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14]
input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14]
input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14]
input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_0_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_1_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_2_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_ren, // @[Frontend.scala:85:14]
input io_ptw_customCSRs_csrs_3_wen, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[Frontend.scala:85:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[Frontend.scala:85:14]
);
wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40]
wire _btb_io_resp_valid; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21]
wire [1:0] _btb_io_resp_bits_mask; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21]
wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21]
wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21]
wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21]
wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21]
wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21]
wire _tlb_io_req_ready; // @[Frontend.scala:105:19]
wire _tlb_io_resp_miss; // @[Frontend.scala:105:19]
wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19]
wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19]
wire _tlb_io_resp_ma_ld; // @[Frontend.scala:105:19]
wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19]
wire _tlb_io_resp_prefetchable; // @[Frontend.scala:105:19]
wire _fq_io_enq_ready; // @[Frontend.scala:91:64]
wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64]
wire _icache_io_resp_valid; // @[Frontend.scala:70:26]
wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26]
wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26]
wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:82:7]
wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:82:7]
wire [63:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:82:7]
wire io_cpu_might_request_0 = io_cpu_might_request; // @[Frontend.scala:82:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_req_bits_speculative_0 = io_cpu_req_bits_speculative; // @[Frontend.scala:82:7]
wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:82:7]
wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:82:7]
wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:82:7]
wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:82:7]
wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:82:7]
wire io_cpu_progress_0 = io_cpu_progress; // @[Frontend.scala:82:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:82:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:82:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:82:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:82:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:82:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:82:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:82:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:82:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:82:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[Frontend.scala:82:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:82:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:82:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:82:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:82:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:82:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:82:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:82:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:82:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:82:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:82:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:82:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:82:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[Frontend.scala:82:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[Frontend.scala:82:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_ready = 1'h1; // @[Frontend.scala:82:7]
wire io_cpu_clock_enabled = 1'h1; // @[Frontend.scala:82:7]
wire clock_en = 1'h1; // @[Frontend.scala:94:31]
wire _taken_rviImm_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_3 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_6 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_7 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_17 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_12 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_13 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_T_6 = 1'h1; // @[Frontend.scala:270:13]
wire _taken_btb_io_ras_update_bits_cfiType_T_3 = 1'h1; // @[Frontend.scala:276:85]
wire _taken_rviImm_b19_12_T_10 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b11_T_25 = 1'h1; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b19_12_T_15 = 1'h1; // @[RocketCore.scala:1343:26]
wire _taken_rviImm_b19_12_T_16 = 1'h1; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_17 = 1'h1; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_39 = 1'h1; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b4_1_T_32 = 1'h1; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_33 = 1'h1; // @[RocketCore.scala:1349:34]
wire _taken_btb_io_ras_update_bits_cfiType_T_11 = 1'h1; // @[Frontend.scala:276:85]
wire _clock_en_reg_T = 1'h1; // @[Frontend.scala:376:19]
wire _clock_en_reg_T_1 = 1'h1; // @[Frontend.scala:376:45]
wire _clock_en_reg_T_2 = 1'h1; // @[Frontend.scala:377:26]
wire _clock_en_reg_T_3 = 1'h1; // @[Frontend.scala:378:34]
wire _clock_en_reg_T_4 = 1'h1; // @[Frontend.scala:379:14]
wire _clock_en_reg_T_6 = 1'h1; // @[Frontend.scala:379:26]
wire _clock_en_reg_T_9 = 1'h1; // @[Frontend.scala:380:23]
wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_d_bits_source = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:82:7]
wire io_cpu_ras_update_valid = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[Frontend.scala:82:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[Frontend.scala:82:7]
wire taken_rvcJAL = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_14 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_1 = 1'h0; // @[RocketCore.scala:1351:17]
wire taken_rvcJAL_1 = 1'h0; // @[Frontend.scala:245:35]
wire _taken_rviImm_sign_T_6 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_6 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b19_12_T_11 = 1'h0; // @[RocketCore.scala:1343:43]
wire _taken_rviImm_b19_12_T_12 = 1'h0; // @[RocketCore.scala:1343:36]
wire _taken_rviImm_b11_T_22 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_23 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_24 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_28 = 1'h0; // @[RocketCore.scala:1346:23]
wire _taken_rviImm_b10_5_T_8 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_9 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_10 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_20 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_21 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_22 = 1'h0; // @[RocketCore.scala:1349:41]
wire _taken_rviImm_b4_1_T_23 = 1'h0; // @[RocketCore.scala:1349:34]
wire _taken_rviImm_b4_1_T_25 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_16 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_18 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_20 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_22 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_23 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_2 = 1'h0; // @[RocketCore.scala:1351:17]
wire _taken_rviImm_sign_T_9 = 1'h0; // @[RocketCore.scala:1341:24]
wire _taken_rviImm_b30_20_T_9 = 1'h0; // @[RocketCore.scala:1342:26]
wire _taken_rviImm_b11_T_33 = 1'h0; // @[RocketCore.scala:1344:23]
wire _taken_rviImm_b11_T_34 = 1'h0; // @[RocketCore.scala:1344:40]
wire _taken_rviImm_b11_T_35 = 1'h0; // @[RocketCore.scala:1344:33]
wire _taken_rviImm_b11_T_36 = 1'h0; // @[RocketCore.scala:1345:23]
wire _taken_rviImm_b10_5_T_12 = 1'h0; // @[RocketCore.scala:1347:25]
wire _taken_rviImm_b10_5_T_13 = 1'h0; // @[RocketCore.scala:1347:42]
wire _taken_rviImm_b10_5_T_14 = 1'h0; // @[RocketCore.scala:1347:35]
wire _taken_rviImm_b4_1_T_30 = 1'h0; // @[RocketCore.scala:1348:24]
wire _taken_rviImm_b4_1_T_31 = 1'h0; // @[RocketCore.scala:1349:24]
wire _taken_rviImm_b4_1_T_35 = 1'h0; // @[RocketCore.scala:1350:24]
wire _taken_rviImm_b0_T_24 = 1'h0; // @[RocketCore.scala:1351:22]
wire _taken_rviImm_b0_T_26 = 1'h0; // @[RocketCore.scala:1352:22]
wire _taken_rviImm_b0_T_28 = 1'h0; // @[RocketCore.scala:1353:22]
wire _taken_rviImm_b0_T_30 = 1'h0; // @[RocketCore.scala:1353:17]
wire _taken_rviImm_b0_T_31 = 1'h0; // @[RocketCore.scala:1352:17]
wire taken_rviImm_b0_3 = 1'h0; // @[RocketCore.scala:1351:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:82:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:82:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_ras_update_bits_cfiType = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[Frontend.scala:82:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:82:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:82:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:82:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:82:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:82:7]
wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:82:7]
wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:82:7]
wire [7:0] auto_icache_master_out_a_bits_mask = 8'hFF; // @[Frontend.scala:82:7]
wire [63:0] auto_icache_master_out_a_bits_data = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[Frontend.scala:82:7]
wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:82:7]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17]
wire [31:0] _s2_pc_T_2 = 32'h10000; // @[Frontend.scala:384:27]
wire [38:0] io_cpu_ras_update_bits_returnAddr = 39'h0; // @[Frontend.scala:82:7]
wire [31:0] _s2_pc_T = 32'hFFFEFFFF; // @[Frontend.scala:384:29]
wire [31:0] _s2_pc_T_1 = 32'hFFFEFFFF; // @[Frontend.scala:384:33]
wire [39:0] _io_cpu_npc_T_3; // @[Frontend.scala:384:27]
wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35]
wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:82:7]
wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:82:7]
wire [7:0] io_cpu_resp_bits_btb_bht_history_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bht_value_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_cfiType_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_taken_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_btb_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_btb_bridx_0; // @[Frontend.scala:82:7]
wire [38:0] io_cpu_resp_bits_btb_target_0; // @[Frontend.scala:82:7]
wire [4:0] io_cpu_resp_bits_btb_entry_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_pf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_gf_inst_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_xcpt_ae_inst_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_resp_bits_pc_0; // @[Frontend.scala:82:7]
wire [31:0] io_cpu_resp_bits_data_0; // @[Frontend.scala:82:7]
wire [1:0] io_cpu_resp_bits_mask_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_bits_replay_0; // @[Frontend.scala:82:7]
wire io_cpu_resp_valid_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_valid_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_gpa_bits_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_acquire_0; // @[Frontend.scala:82:7]
wire io_cpu_perf_tlbMiss_0; // @[Frontend.scala:82:7]
wire io_cpu_gpa_is_pte_0; // @[Frontend.scala:82:7]
wire [39:0] io_cpu_npc_0; // @[Frontend.scala:82:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:82:7]
wire io_ptw_req_bits_valid_0; // @[Frontend.scala:82:7]
wire io_ptw_req_valid_0; // @[Frontend.scala:82:7]
wire io_errors_bus_valid; // @[Frontend.scala:82:7]
wire [31:0] io_errors_bus_bits; // @[Frontend.scala:82:7]
reg s1_valid; // @[Frontend.scala:107:21]
reg s2_valid; // @[Frontend.scala:108:25]
wire _s0_fq_has_space_T = _fq_io_mask[2]; // @[Frontend.scala:91:64, :110:16]
wire _s0_fq_has_space_T_1 = ~_s0_fq_has_space_T; // @[Frontend.scala:110:{5,16}]
wire _s0_fq_has_space_T_2 = _fq_io_mask[3]; // @[Frontend.scala:91:64, :111:17]
wire _s0_fq_has_space_T_3 = ~_s0_fq_has_space_T_2; // @[Frontend.scala:111:{6,17}]
wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala:107:21, :111:45]
wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala:108:25, :111:58]
wire _s0_fq_has_space_T_6 = _s0_fq_has_space_T_4 | _s0_fq_has_space_T_5; // @[Frontend.scala:111:{45,55,58}]
wire _s0_fq_has_space_T_7 = _s0_fq_has_space_T_3 & _s0_fq_has_space_T_6; // @[Frontend.scala:111:{6,41,55}]
wire _s0_fq_has_space_T_8 = _s0_fq_has_space_T_1 | _s0_fq_has_space_T_7; // @[Frontend.scala:110:{5,40}, :111:41]
wire _s0_fq_has_space_T_9 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17]
wire _clock_en_reg_T_7 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17, :381:16]
wire _s0_fq_has_space_T_10 = ~_s0_fq_has_space_T_9; // @[Frontend.scala:112:{6,17}]
wire _s0_fq_has_space_T_11 = ~s1_valid; // @[Frontend.scala:107:21, :111:45, :112:45]
wire _s0_fq_has_space_T_12 = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :112:58]
wire _s0_fq_has_space_T_13 = _s0_fq_has_space_T_11 & _s0_fq_has_space_T_12; // @[Frontend.scala:112:{45,55,58}]
wire _s0_fq_has_space_T_14 = _s0_fq_has_space_T_10 & _s0_fq_has_space_T_13; // @[Frontend.scala:112:{6,41,55}]
wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala:110:40, :111:70, :112:41]
wire s0_valid = io_cpu_req_valid_0 | s0_fq_has_space; // @[Frontend.scala:82:7, :111:70, :113:35]
reg [39:0] s1_pc; // @[Frontend.scala:115:18]
reg s1_speculative; // @[Frontend.scala:116:27]
reg [39:0] s2_pc; // @[Frontend.scala:117:22]
reg s2_btb_resp_valid; // @[Frontend.scala:118:44]
reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29]
reg [1:0] s2_btb_resp_bits_mask; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29]
wire _taken_T_30 = s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:119:29]
reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29]
reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29]
reg s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_23 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_predict_taken_T_1 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire _taken_T_52 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29]
wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40]
reg s2_tlb_resp_miss; // @[Frontend.scala:121:24]
reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:121:24]
reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24]
reg s2_tlb_resp_ma_ld; // @[Frontend.scala:121:24]
reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24]
reg s2_tlb_resp_prefetchable; // @[Frontend.scala:121:24]
wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37]
wire s2_xcpt = _s2_xcpt_T; // @[Frontend.scala:122:{37,60}]
reg s2_speculative; // @[Frontend.scala:123:31]
reg s2_partial_insn_valid; // @[Frontend.scala:124:38]
reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28]
reg wrong_path; // @[Frontend.scala:126:27]
wire [39:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala:115:18, :128:22]
wire [39:0] _s1_base_pc_T_1 = {_s1_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:128:{22,29}]
wire [39:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala:128:{20,29}]
wire [40:0] _ntpc_T = {1'h0, s1_base_pc} + 41'h4; // @[Frontend.scala:128:20, :129:25]
wire [39:0] ntpc = _ntpc_T[39:0]; // @[Frontend.scala:129:25]
wire [39:0] predicted_npc; // @[Frontend.scala:130:34]
wire predicted_taken; // @[Frontend.scala:131:36]
wire _s2_replay_T_5; // @[Frontend.scala:134:46]
wire s2_replay; // @[Frontend.scala:133:23]
wire _fq_io_enq_valid_T_6; // @[Frontend.scala:184:52]
wire _T_37 = _fq_io_enq_ready & _fq_io_enq_valid_T_6; // @[Decoupled.scala:51:35]
wire _s2_replay_T; // @[Decoupled.scala:51:35]
assign _s2_replay_T = _T_37; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T; // @[Decoupled.scala:51:35]
assign _btb_io_btb_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_8; // @[Decoupled.scala:51:35]
assign _taken_T_8 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_9; // @[Decoupled.scala:51:35]
assign _taken_btb_io_ras_update_valid_T_9 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_37; // @[Decoupled.scala:51:35]
assign _taken_T_37 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_btb_io_bht_advance_valid_T_3; // @[Decoupled.scala:51:35]
assign _taken_btb_io_bht_advance_valid_T_3 = _T_37; // @[Decoupled.scala:51:35]
wire _taken_T_57; // @[Decoupled.scala:51:35]
assign _taken_T_57 = _T_37; // @[Decoupled.scala:51:35]
wire _s2_replay_T_1 = ~_s2_replay_T; // @[Decoupled.scala:51:35]
wire _s2_replay_T_2 = s2_valid & _s2_replay_T_1; // @[Frontend.scala:108:25, :134:{26,29}]
wire _s2_replay_T_3 = ~s0_valid; // @[Frontend.scala:113:35, :134:70]
wire _s2_replay_T_4 = s2_replay & _s2_replay_T_3; // @[Frontend.scala:133:23, :134:{67,70}]
reg s2_replay_REG; // @[Frontend.scala:134:56]
assign _s2_replay_T_5 = _s2_replay_T_2 | s2_replay_REG; // @[Frontend.scala:134:{26,46,56}]
assign s2_replay = _s2_replay_T_5; // @[Frontend.scala:133:23, :134:46]
wire [39:0] npc = s2_replay ? s2_pc : predicted_npc; // @[Frontend.scala:117:22, :130:34, :133:23, :135:16]
wire _s0_speculative_T = ~s2_speculative; // @[Frontend.scala:123:31, :141:56]
wire _s0_speculative_T_1 = s2_valid & _s0_speculative_T; // @[Frontend.scala:108:25, :141:{53,56}]
wire _s0_speculative_T_2 = s1_speculative | _s0_speculative_T_1; // @[Frontend.scala:116:27, :141:{41,53}]
wire s0_speculative = _s0_speculative_T_2 | predicted_taken; // @[Frontend.scala:131:36, :141:{41,72}]
wire _s1_speculative_T = s2_replay ? s2_speculative : s0_speculative; // @[Frontend.scala:123:31, :133:23, :141:72, :143:75]
wire _s1_speculative_T_1 = io_cpu_req_valid_0 ? io_cpu_req_bits_speculative_0 : _s1_speculative_T; // @[Frontend.scala:82:7, :143:{24,75}]
wire s2_redirect; // @[Frontend.scala:145:32]
wire _s2_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17]
reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40]
wire recent_progress = |recent_progress_counter; // @[Frontend.scala:155:40, :156:49]
assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35]
wire [2:0] _recent_progress_counter_T = {1'h0, recent_progress_counter} - 3'h1; // @[Frontend.scala:155:40, :157:97]
wire [1:0] _recent_progress_counter_T_1 = _recent_progress_counter_T[1:0]; // @[Frontend.scala:157:97]
wire _s2_kill_speculative_tlb_refill_T = ~recent_progress; // @[Frontend.scala:156:49, :160:58]
wire s2_kill_speculative_tlb_refill = s2_speculative & _s2_kill_speculative_tlb_refill_T; // @[Frontend.scala:123:31, :160:{55,58}]
wire _tlb_io_req_valid_T = ~s2_replay; // @[Frontend.scala:133:23, :147:9, :163:35]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:107:21, :163:{32,35}]
wire _tlb_io_kill_T = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :171:18]
wire _tlb_io_kill_T_1 = _tlb_io_kill_T | s2_kill_speculative_tlb_refill; // @[Frontend.scala:160:55, :171:{18,28}]
wire _icache_io_s1_kill_T = s2_redirect | _tlb_io_resp_miss; // @[Frontend.scala:105:19, :145:32, :178:36]
wire _icache_io_s1_kill_T_1 = _icache_io_s1_kill_T | s2_replay; // @[Frontend.scala:133:23, :178:{36,56}]
wire _s2_can_speculatively_refill_T = io_ptw_customCSRs_csrs_0_value_0[3]; // @[CustomCSRs.scala:46:69]
wire _s2_can_speculatively_refill_T_1 = ~_s2_can_speculatively_refill_T; // @[CustomCSRs.scala:46:69]
wire s2_can_speculatively_refill = s2_tlb_resp_cacheable & _s2_can_speculatively_refill_T_1; // @[Frontend.scala:121:24, :179:{59,62}]
wire _icache_io_s2_kill_T = ~s2_can_speculatively_refill; // @[Frontend.scala:179:59, :180:42]
wire _icache_io_s2_kill_T_1 = s2_speculative & _icache_io_s2_kill_T; // @[Frontend.scala:123:31, :180:{39,42}]
wire _icache_io_s2_kill_T_2 = _icache_io_s2_kill_T_1 | s2_xcpt; // @[Frontend.scala:122:60, :180:{39,71}]
wire _icache_io_s2_prefetch_T = io_ptw_customCSRs_csrs_0_value_0[17]; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_1 = ~_icache_io_s2_prefetch_T; // @[RocketCore.scala:115:60]
wire _icache_io_s2_prefetch_T_2 = s2_tlb_resp_prefetchable & _icache_io_s2_prefetch_T_1; // @[Frontend.scala:121:24, :182:{53,56}]
reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29]
wire _fq_io_enq_valid_T = fq_io_enq_valid_REG & s2_valid; // @[Frontend.scala:108:25, :184:{29,40}]
wire _GEN = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112]
wire _fq_io_enq_valid_T_1; // @[Frontend.scala:184:112]
assign _fq_io_enq_valid_T_1 = _GEN; // @[Frontend.scala:184:112]
wire _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:150]
assign _fq_io_enq_bits_replay_T_5 = _GEN; // @[Frontend.scala:184:112, :190:150]
wire _fq_io_enq_valid_T_2 = _icache_io_resp_valid | _fq_io_enq_valid_T_1; // @[Frontend.scala:70:26, :184:{77,112}]
wire _fq_io_enq_valid_T_3 = ~s2_tlb_resp_miss; // @[Frontend.scala:121:24, :184:137]
wire _fq_io_enq_valid_T_4 = _fq_io_enq_valid_T_3 & _icache_io_s2_kill_T_2; // @[Frontend.scala:180:71, :184:{137,155}]
wire _fq_io_enq_valid_T_5 = _fq_io_enq_valid_T_2 | _fq_io_enq_valid_T_4; // @[Frontend.scala:184:{77,133,155}]
assign _fq_io_enq_valid_T_6 = _fq_io_enq_valid_T & _fq_io_enq_valid_T_5; // @[Frontend.scala:184:{40,52,133}]
wire [39:0] _io_cpu_npc_T = io_cpu_req_valid_0 ? io_cpu_req_bits_pc_0 : npc; // @[Frontend.scala:82:7, :135:16, :186:28]
wire [39:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala:186:28, :384:29]
wire [39:0] _io_cpu_npc_T_2 = {_io_cpu_npc_T_1[39:1], 1'h1}; // @[Frontend.scala:384:{29,33}]
assign _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala:384:{27,33}]
assign io_cpu_npc_0 = _io_cpu_npc_T_3; // @[Frontend.scala:82:7, :384:27]
wire _fq_io_enq_bits_mask_T = s2_pc[1]; // @[package.scala:163:13]
wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << _fq_io_enq_bits_mask_T; // @[package.scala:163:13]
wire _fq_io_enq_bits_replay_T = ~_icache_io_resp_valid; // @[Frontend.scala:70:26, :190:80]
wire _fq_io_enq_bits_replay_T_1 = _icache_io_s2_kill_T_2 & _fq_io_enq_bits_replay_T; // @[Frontend.scala:180:71, :190:{77,80}]
wire _fq_io_enq_bits_replay_T_2 = ~s2_xcpt; // @[Frontend.scala:122:60, :190:105]
wire _fq_io_enq_bits_replay_T_3 = _fq_io_enq_bits_replay_T_1 & _fq_io_enq_bits_replay_T_2; // @[Frontend.scala:190:{77,102,105}]
wire _fq_io_enq_bits_replay_T_4 = _fq_io_enq_bits_replay_T_3; // @[Frontend.scala:190:{56,102}]
wire _fq_io_enq_bits_replay_T_6 = _fq_io_enq_bits_replay_T_4 | _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:{56,115,150}]
wire _btb_io_req_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17, :209:27]
assign predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:131:36, :198:21, :213:29]
wire _predicted_npc_T = _btb_io_resp_bits_target[38]; // @[package.scala:132:38]
wire [39:0] _predicted_npc_T_1 = {_predicted_npc_T, _btb_io_resp_bits_target}; // @[package.scala:132:{15,38}]
wire [39:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala:117:22, :222:24]
wire [39:0] _s2_base_pc_T_1 = {_s2_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:222:{24,31}]
wire [39:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala:222:{22,31}]
wire [39:0] taken_pc = s2_base_pc; // @[Frontend.scala:222:22, :287:33]
wire _taken_T_35; // @[Frontend.scala:270:13]
wire taken_idx; // @[Frontend.scala:223:25]
wire [1:0] after_idx; // @[Frontend.scala:224:25]
wire useRAS; // @[Frontend.scala:225:29]
wire updateBTB; // @[Frontend.scala:226:32]
wire _fetch_bubble_likely_T = _fq_io_mask[1]; // @[Frontend.scala:91:64, :318:44]
wire fetch_bubble_likely = ~_fetch_bubble_likely_T; // @[Frontend.scala:318:{33,44}]
wire _btb_io_btb_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :319:52]
wire _btb_io_btb_update_valid_T_2 = _btb_io_btb_update_valid_T & _btb_io_btb_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _btb_io_btb_update_valid_T_3 = _btb_io_btb_update_valid_T_2 & fetch_bubble_likely; // @[Frontend.scala:318:33, :319:{49,64}]
wire _btb_io_btb_update_valid_T_4 = _btb_io_btb_update_valid_T_3 & updateBTB; // @[Frontend.scala:226:32, :319:{64,87}]
wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala:223:25, :323:63]
wire [39:0] _btb_io_btb_update_bits_br_pc_T_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala:222:22, :323:{50,63}]
wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala:224:25, :327:66]
wire [40:0] _btb_io_ras_update_bits_returnAddr_T_1 = {1'h0, s2_base_pc} + {38'h0, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala:129:25, :222:22, :327:{53,66}]
wire [39:0] _btb_io_ras_update_bits_returnAddr_T_2 = _btb_io_ras_update_bits_returnAddr_T_1[39:0]; // @[Frontend.scala:327:53]
wire [1:0] _taken_prevRVI_T = s2_partial_insn[1:0]; // @[Frontend.scala:125:28, :233:39]
wire _taken_prevRVI_T_1 = _taken_prevRVI_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_2 = ~_taken_prevRVI_T_1; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI = s2_partial_insn_valid & _taken_prevRVI_T_2; // @[Frontend.scala:124:38, :234:{31,34}]
wire _taken_valid_T = _fq_io_enq_bits_mask_T_1[0]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_1 = ~taken_prevRVI; // @[Frontend.scala:234:31, :235:47]
wire taken_valid = _taken_valid_T & _taken_valid_T_1; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits = _icache_io_resp_bits_data[15:0]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire [1:0] _taken_prevRVI_T_3 = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc = _taken_rvc_T != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits = {taken_bits, s2_partial_insn}; // @[Frontend.scala:125:28, :236:37, :238:24]
wire [6:0] _taken_rviBranch_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch = _taken_rviBranch_T == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump = _taken_rviJump_T == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR = _taken_rviJALR_T == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_1 = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_7 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_1 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_18 = taken_rviBits[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_9 = taken_rviBits[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_1 = ~_taken_rviReturn_T; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_2 = taken_rviJALR & _taken_rviReturn_T_1; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_3 = taken_rviBits[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_4 = _taken_rviReturn_T_3 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_5 = _taken_rviReturn_T_4 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn = _taken_rviReturn_T_2 & _taken_rviReturn_T_5; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_0 = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T; // @[Frontend.scala:243:30]
assign _taken_rviCall_T = _GEN_0; // @[Frontend.scala:243:30]
wire _taken_taken_T; // @[Frontend.scala:255:29]
assign _taken_taken_T = _GEN_0; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall = _taken_rviCall_T & _taken_rviCall_T_1; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_1 = taken_bits & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T = _GEN_1; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_2; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_2 = _GEN_1; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T = _GEN_1; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T = _GEN_1; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_1 = _taken_rvcBranch_T == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_3 = _taken_rvcBranch_T_2 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch = _taken_rvcBranch_T_1 | _taken_rvcBranch_T_3; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_1 = _taken_rvcJAL_T == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_1 = _taken_rvcJump_T == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump = _taken_rvcJump_T_1; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T = taken_bits[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_1 = taken_bits[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_9 = taken_bits[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_2 = {5{_taken_rvcImm_T_1}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_3 = taken_bits[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_4 = taken_bits[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_15 = taken_bits[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_5 = taken_bits[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_6 = taken_bits[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi = {_taken_rvcImm_T_5, _taken_rvcImm_T_6}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo = {taken_rvcImm_lo_hi, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi = {_taken_rvcImm_T_2, _taken_rvcImm_T_3}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi = {taken_rvcImm_hi_hi, _taken_rvcImm_T_4}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_7 = {taken_rvcImm_hi, taken_rvcImm_lo}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_8 = _taken_rvcImm_T_7; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_10 = {10{_taken_rvcImm_T_9}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_11 = taken_bits[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_12 = taken_bits[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_13 = taken_bits[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_14 = taken_bits[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_16 = taken_bits[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_17 = taken_bits[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo = {_taken_rvcImm_T_17, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_1 = {_taken_rvcImm_T_15, _taken_rvcImm_T_16}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_1 = {taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo = {_taken_rvcImm_T_13, _taken_rvcImm_T_14}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi = {_taken_rvcImm_T_10, _taken_rvcImm_T_11}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_1 = {taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_1 = {taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_18 = {taken_rvcImm_hi_1, taken_rvcImm_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_19 = _taken_rvcImm_T_18; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm = _taken_rvcImm_T ? {{8{_taken_rvcImm_T_8[12]}}, _taken_rvcImm_T_8} : _taken_rvcImm_T_19; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_2 = taken_bits & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T = _GEN_2; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T = _GEN_2; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_1 = _taken_rvcJR_T == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_3 = _taken_rvcJR_T_2 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR = _taken_rvcJR_T_1 & _taken_rvcJR_T_3; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T = taken_bits[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_1 = _taken_rvcReturn_T & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_2 = _taken_rvcReturn_T_1 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn = taken_rvcJR & _taken_rvcReturn_T_2; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_1 = _taken_rvcJALR_T == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_3 = _taken_rvcJALR_T_2 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR = _taken_rvcJALR_T_1 & _taken_rvcJALR_T_3; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall = taken_rvcJALR; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T = taken_rviBits[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_1 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_4 = taken_rviBits[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_2 = _taken_rviImm_sign_T_1; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign = _taken_rviImm_sign_T_2; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_9 = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_1 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_4 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_2 = _taken_rviImm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20 = {11{taken_rviImm_sign}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo = taken_rviImm_b30_20; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_3 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_8 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_4 = _taken_rviImm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12 = _taken_rviImm_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi = taken_rviImm_b19_12; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_4 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_3 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_15 = taken_rviBits[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_11 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_5 = _taken_rviImm_b11_T_4; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_10 = _taken_rviImm_b11_T_5; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_8 = _taken_rviImm_b11_T_7; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11 = _taken_rviImm_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo = taken_rviImm_b11; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_3 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_7 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5 = _taken_rviImm_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_4 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_14 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_6 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_16 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_7 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_17 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_8 = _taken_rviImm_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_9 = _taken_rviImm_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1 = _taken_rviImm_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_5 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_13 = taken_rviBits[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi = {taken_rviImm_b10_5, taken_rviImm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo = {taken_rviImm_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo = {taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi = {taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi = {taken_rviImm_hi_hi, taken_rviImm_hi_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_1 = {taken_rviImm_hi, taken_rviImm_lo}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_2 = _taken_rviImm_T_1; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_5 = _taken_rviImm_sign_T_4; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_1 = _taken_rviImm_sign_T_5; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_1 = taken_rviImm_sign_1; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_5 = _taken_rviImm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_1 = {11{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_1 = taken_rviImm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_9 = _taken_rviImm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_1 = {8{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_1 = taken_rviImm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_16 = _taken_rviImm_b11_T_15; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_19 = _taken_rviImm_b11_T_18; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_20 = _taken_rviImm_b11_T_19; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_21 = _taken_rviImm_b11_T_20; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_1 = _taken_rviImm_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_1 = taken_rviImm_b11_1; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_1 = _taken_rviImm_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_19 = _taken_rviImm_b4_1_T_14; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_18 = _taken_rviImm_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_1 = _taken_rviImm_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_1 = {taken_rviImm_b10_5_1, taken_rviImm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_1 = {taken_rviImm_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_1 = {taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_1 = {taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_1 = {taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_3 = {taken_rviImm_hi_1, taken_rviImm_lo_1}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_4 = _taken_rviImm_T_3; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm = _taken_rviImm_T ? _taken_rviImm_T_2 : _taken_rviImm_T_4; // @[RocketCore.scala:1355:53]
wire taken_predict_taken = _taken_predict_taken_T; // @[Frontend.scala:253:54]
wire _taken_taken_T_1 = taken_rviBranch & taken_predict_taken; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_2 = _taken_taken_T | _taken_taken_T_1; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_3 = taken_prevRVI & _taken_taken_T_2; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_4 = taken_rvcJump | taken_rvcJALR; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_5 = _taken_taken_T_4 | taken_rvcJR; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_6 = taken_rvcBranch & taken_predict_taken; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_7 = _taken_taken_T_5 | _taken_taken_T_6; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_8 = taken_valid & _taken_taken_T_7; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken = _taken_taken_T_3 | _taken_taken_T_8; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_T_28 = taken_taken; // @[Frontend.scala:255:71, :313:51]
wire _taken_predictReturn_T = taken_prevRVI & taken_rviReturn; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_1 = taken_valid & taken_rvcReturn; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_2 = _taken_predictReturn_T | _taken_predictReturn_T_1; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn = _btb_io_ras_head_valid & _taken_predictReturn_T_2; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T = taken_prevRVI & taken_rviJump; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_1 = taken_valid & taken_rvcJump; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump = _taken_predictJump_T | _taken_predictJump_T_1; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_3 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T = _GEN_3; // @[Frontend.scala:259:53]
wire _taken_T_19; // @[Frontend.scala:294:23]
assign _taken_T_19 = _GEN_3; // @[Frontend.scala:259:53, :294:23]
wire _GEN_4 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_1; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_1 = _GEN_4; // @[Frontend.scala:259:75]
wire _taken_T_20; // @[Frontend.scala:294:45]
assign _taken_T_20 = _GEN_4; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_2 = _taken_predictBranch_T | _taken_predictBranch_T_1; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch = taken_predict_taken & _taken_predictBranch_T_2; // @[Frontend.scala:253:54, :259:{41,66}]
wire _GEN_5 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22]
wire _taken_T; // @[Frontend.scala:261:22]
assign _taken_T = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_29; // @[Frontend.scala:261:22]
assign _taken_T_29 = _GEN_5; // @[Frontend.scala:261:22]
wire _taken_T_1 = ~s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69]
wire _taken_T_2 = _taken_T & _taken_T_1; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_3 = _taken_T_2 & taken_valid; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_4 = ~taken_rvc; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_5 = _taken_T_3 & _taken_T_4; // @[Frontend.scala:261:{79,88,91}]
wire _taken_btb_io_ras_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_2 = _taken_btb_io_ras_update_valid_T & _taken_btb_io_ras_update_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_3 = taken_rviCall | taken_rviReturn; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_4 = taken_prevRVI & _taken_btb_io_ras_update_valid_T_3; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_5 = taken_rvcCall | taken_rvcReturn; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_6 = taken_valid & _taken_btb_io_ras_update_valid_T_5; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_7 = _taken_btb_io_ras_update_valid_T_4 | _taken_btb_io_ras_update_valid_T_6; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_8 = _taken_btb_io_ras_update_valid_T_2 & _taken_btb_io_ras_update_valid_T_7; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_4 = _taken_btb_io_ras_update_bits_cfiType_T_2; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_5 = ~_taken_btb_io_ras_update_bits_cfiType_T_4; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala:274:{46,50}, :275:46]
wire _taken_T_7 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_9 = _taken_T_8 & taken_taken; // @[Decoupled.scala:51:35]
wire _taken_T_10 = ~taken_predictBranch; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_11 = _taken_T_9 & _taken_T_10; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_12 = ~taken_predictJump; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_13 = _taken_T_11 & _taken_T_12; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_14 = ~taken_predictReturn; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_15 = _taken_T_13 & _taken_T_14; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala:108:25, :257:49, :283:26]
wire _taken_T_17 = taken_predictBranch | taken_predictJump; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_18 = s2_valid & _taken_T_17; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] _taken_npc_T = taken_pc; // @[Frontend.scala:287:33, :289:32]
wire [32:0] _taken_npc_T_1 = {taken_rviImm[31], taken_rviImm} - 33'h2; // @[Frontend.scala:252:23, :289:61]
wire [32:0] _taken_npc_T_2 = taken_prevRVI ? _taken_npc_T_1 : {{12{taken_rvcImm[20]}}, taken_rvcImm}; // @[Frontend.scala:234:31, :247:23, :289:{44,61}]
wire [40:0] _taken_npc_T_3 = {_taken_npc_T[39], _taken_npc_T} + {{8{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:289:{32,39,44}]
wire [39:0] _taken_npc_T_4 = _taken_npc_T_3[39:0]; // @[Frontend.scala:289:39]
wire [39:0] taken_npc = _taken_npc_T_4; // @[Frontend.scala:289:39]
wire [39:0] _taken_predicted_npc_T = taken_npc; // @[Frontend.scala:289:39, :291:34]
wire _taken_T_21 = _taken_T_19 | _taken_T_20; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_2 = _taken_btb_io_bht_advance_valid_T & _taken_btb_io_bht_advance_valid_T_1; // @[Decoupled.scala:51:35]
wire _taken_T_22 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_24 = taken_predictBranch & _taken_T_23; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_25 = _taken_T_24 | taken_predictJump; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_26 = _taken_T_25 | taken_predictReturn; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_27 = _taken_T_22 & _taken_T_26; // @[Frontend.scala:298:{15,34,106}]
wire _taken_prevRVI_T_4 = _taken_prevRVI_T_3 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala:233:45, :234:34]
wire taken_prevRVI_1 = taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala:234:{31,34}, :235:44]
wire _taken_valid_T_2 = _fq_io_enq_bits_mask_T_1[1]; // @[Frontend.scala:189:50, :235:38]
wire _taken_valid_T_3 = ~taken_prevRVI_1; // @[Frontend.scala:234:31, :235:47]
wire taken_valid_1 = _taken_valid_T_2 & _taken_valid_T_3; // @[Frontend.scala:235:{38,44,47}]
wire [15:0] taken_bits_1 = _icache_io_resp_bits_data[31:16]; // @[Frontend.scala:70:26, :236:37]
wire [1:0] _taken_rvc_T_1 = taken_bits_1[1:0]; // @[Frontend.scala:233:39, :236:37]
wire taken_rvc_1 = _taken_rvc_T_1 != 2'h3; // @[Frontend.scala:233:{39,45}]
wire [31:0] taken_rviBits_1 = {taken_bits_1, taken_bits}; // @[Frontend.scala:236:37, :238:24]
wire [6:0] _taken_rviBranch_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30]
wire [6:0] _taken_rviJump_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28]
wire [6:0] _taken_rviJALR_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28]
wire taken_rviBranch_1 = _taken_rviBranch_T_1 == 7'h63; // @[Frontend.scala:239:{30,36}]
wire taken_rviJump_1 = _taken_rviJump_T_1 == 7'h6F; // @[Frontend.scala:240:{28,34}]
wire taken_rviJALR_1 = _taken_rviJALR_T_1 == 7'h67; // @[Frontend.scala:241:{28,34}]
wire _taken_rviReturn_T_6 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42]
wire _taken_rviCall_T_3 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42, :243:52]
wire _taken_rviImm_b11_T_29 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_17 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviImm_b11_T_40 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39]
wire _taken_rviImm_b0_T_25 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37]
wire _taken_rviReturn_T_7 = ~_taken_rviReturn_T_6; // @[Frontend.scala:242:{34,42}]
wire _taken_rviReturn_T_8 = taken_rviJALR_1 & _taken_rviReturn_T_7; // @[Frontend.scala:241:34, :242:{31,34}]
wire [4:0] _taken_rviReturn_T_9 = taken_rviBits_1[19:15]; // @[Frontend.scala:238:24, :242:77]
wire [4:0] _taken_rviReturn_T_10 = _taken_rviReturn_T_9 & 5'h1B; // @[Frontend.scala:242:{66,77}]
wire _taken_rviReturn_T_11 = _taken_rviReturn_T_10 == 5'h1; // @[Frontend.scala:242:66]
wire taken_rviReturn_1 = _taken_rviReturn_T_8 & _taken_rviReturn_T_11; // @[Frontend.scala:242:{31,46,66}]
wire _GEN_6 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30]
wire _taken_rviCall_T_2; // @[Frontend.scala:243:30]
assign _taken_rviCall_T_2 = _GEN_6; // @[Frontend.scala:243:30]
wire _taken_taken_T_9; // @[Frontend.scala:255:29]
assign _taken_taken_T_9 = _GEN_6; // @[Frontend.scala:243:30, :255:29]
wire taken_rviCall_1 = _taken_rviCall_T_2 & _taken_rviCall_T_3; // @[Frontend.scala:243:{30,42,52}]
wire [15:0] _GEN_7 = taken_bits_1 & 16'hE003; // @[Frontend.scala:236:37, :244:28]
wire [15:0] _taken_rvcBranch_T_4; // @[Frontend.scala:244:28]
assign _taken_rvcBranch_T_4 = _GEN_7; // @[Frontend.scala:244:28]
wire [15:0] _taken_rvcBranch_T_6; // @[Frontend.scala:244:60]
assign _taken_rvcBranch_T_6 = _GEN_7; // @[Frontend.scala:244:{28,60}]
wire [15:0] _taken_rvcJAL_T_2; // @[Frontend.scala:245:43]
assign _taken_rvcJAL_T_2 = _GEN_7; // @[Frontend.scala:244:28, :245:43]
wire [15:0] _taken_rvcJump_T_2; // @[Frontend.scala:246:26]
assign _taken_rvcJump_T_2 = _GEN_7; // @[Frontend.scala:244:28, :246:26]
wire _taken_rvcBranch_T_5 = _taken_rvcBranch_T_4 == 16'hC001; // @[Frontend.scala:244:28]
wire _taken_rvcBranch_T_7 = _taken_rvcBranch_T_6 == 16'hE001; // @[Frontend.scala:244:60]
wire taken_rvcBranch_1 = _taken_rvcBranch_T_5 | _taken_rvcBranch_T_7; // @[Frontend.scala:244:{28,52,60}]
wire _taken_rvcJAL_T_3 = _taken_rvcJAL_T_2 == 16'h2001; // @[Frontend.scala:245:43]
wire _taken_rvcJump_T_3 = _taken_rvcJump_T_2 == 16'hA001; // @[Frontend.scala:246:26]
wire taken_rvcJump_1 = _taken_rvcJump_T_3; // @[Frontend.scala:246:{26,47}]
wire _taken_rvcImm_T_20 = taken_bits_1[14]; // @[Frontend.scala:236:37, :247:28]
wire _taken_rvcImm_T_21 = taken_bits_1[12]; // @[RVC.scala:45:27]
wire _taken_rvcImm_T_29 = taken_bits_1[12]; // @[RVC.scala:44:28, :45:27]
wire [4:0] _taken_rvcImm_T_22 = {5{_taken_rvcImm_T_21}}; // @[RVC.scala:45:{22,27}]
wire [1:0] _taken_rvcImm_T_23 = taken_bits_1[6:5]; // @[RVC.scala:45:35]
wire _taken_rvcImm_T_24 = taken_bits_1[2]; // @[RVC.scala:45:43]
wire _taken_rvcImm_T_35 = taken_bits_1[2]; // @[RVC.scala:44:63, :45:43]
wire [1:0] _taken_rvcImm_T_25 = taken_bits_1[11:10]; // @[RVC.scala:45:49]
wire [1:0] _taken_rvcImm_T_26 = taken_bits_1[4:3]; // @[RVC.scala:45:59]
wire [3:0] taken_rvcImm_lo_hi_2 = {_taken_rvcImm_T_25, _taken_rvcImm_T_26}; // @[RVC.scala:45:{17,49,59}]
wire [4:0] taken_rvcImm_lo_2 = {taken_rvcImm_lo_hi_2, 1'h0}; // @[RVC.scala:45:17]
wire [6:0] taken_rvcImm_hi_hi_2 = {_taken_rvcImm_T_22, _taken_rvcImm_T_23}; // @[RVC.scala:45:{17,22,35}]
wire [7:0] taken_rvcImm_hi_2 = {taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24}; // @[RVC.scala:45:{17,43}]
wire [12:0] _taken_rvcImm_T_27 = {taken_rvcImm_hi_2, taken_rvcImm_lo_2}; // @[RVC.scala:45:17]
wire [12:0] _taken_rvcImm_T_28 = _taken_rvcImm_T_27; // @[RVC.scala:45:17]
wire [9:0] _taken_rvcImm_T_30 = {10{_taken_rvcImm_T_29}}; // @[RVC.scala:44:{22,28}]
wire _taken_rvcImm_T_31 = taken_bits_1[8]; // @[RVC.scala:44:36]
wire [1:0] _taken_rvcImm_T_32 = taken_bits_1[10:9]; // @[RVC.scala:44:42]
wire _taken_rvcImm_T_33 = taken_bits_1[6]; // @[RVC.scala:44:51]
wire _taken_rvcImm_T_34 = taken_bits_1[7]; // @[RVC.scala:44:57]
wire _taken_rvcImm_T_36 = taken_bits_1[11]; // @[RVC.scala:44:69]
wire [2:0] _taken_rvcImm_T_37 = taken_bits_1[5:3]; // @[RVC.scala:44:76]
wire [3:0] taken_rvcImm_lo_lo_1 = {_taken_rvcImm_T_37, 1'h0}; // @[RVC.scala:44:{17,76}]
wire [1:0] taken_rvcImm_lo_hi_3 = {_taken_rvcImm_T_35, _taken_rvcImm_T_36}; // @[RVC.scala:44:{17,63,69}]
wire [5:0] taken_rvcImm_lo_3 = {taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1}; // @[RVC.scala:44:17]
wire [1:0] taken_rvcImm_hi_lo_1 = {_taken_rvcImm_T_33, _taken_rvcImm_T_34}; // @[RVC.scala:44:{17,51,57}]
wire [10:0] taken_rvcImm_hi_hi_hi_1 = {_taken_rvcImm_T_30, _taken_rvcImm_T_31}; // @[RVC.scala:44:{17,22,36}]
wire [12:0] taken_rvcImm_hi_hi_3 = {taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32}; // @[RVC.scala:44:{17,42}]
wire [14:0] taken_rvcImm_hi_3 = {taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_38 = {taken_rvcImm_hi_3, taken_rvcImm_lo_3}; // @[RVC.scala:44:17]
wire [20:0] _taken_rvcImm_T_39 = _taken_rvcImm_T_38; // @[RVC.scala:44:17]
wire [20:0] taken_rvcImm_1 = _taken_rvcImm_T_20 ? {{8{_taken_rvcImm_T_28[12]}}, _taken_rvcImm_T_28} : _taken_rvcImm_T_39; // @[Frontend.scala:247:{23,28,72,118}]
wire [15:0] _GEN_8 = taken_bits_1 & 16'hF003; // @[Frontend.scala:236:37, :248:24]
wire [15:0] _taken_rvcJR_T_4; // @[Frontend.scala:248:24]
assign _taken_rvcJR_T_4 = _GEN_8; // @[Frontend.scala:248:24]
wire [15:0] _taken_rvcJALR_T_4; // @[Frontend.scala:250:26]
assign _taken_rvcJALR_T_4 = _GEN_8; // @[Frontend.scala:248:24, :250:26]
wire _taken_rvcJR_T_5 = _taken_rvcJR_T_4 == 16'h8002; // @[Frontend.scala:248:24]
wire [4:0] _taken_rvcJR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53]
wire [4:0] _taken_rvcJALR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56]
wire _taken_rvcJR_T_7 = _taken_rvcJR_T_6 == 5'h0; // @[Frontend.scala:248:{53,59}]
wire taken_rvcJR_1 = _taken_rvcJR_T_5 & _taken_rvcJR_T_7; // @[Frontend.scala:248:{24,46,59}]
wire [4:0] _taken_rvcReturn_T_3 = taken_bits_1[11:7]; // @[Frontend.scala:236:37, :249:57]
wire [4:0] _taken_rvcReturn_T_4 = _taken_rvcReturn_T_3 & 5'h1B; // @[Frontend.scala:249:{49,57}]
wire _taken_rvcReturn_T_5 = _taken_rvcReturn_T_4 == 5'h1; // @[Frontend.scala:249:49]
wire taken_rvcReturn_1 = taken_rvcJR_1 & _taken_rvcReturn_T_5; // @[Frontend.scala:248:46, :249:{29,49}]
wire _taken_rvcJALR_T_5 = _taken_rvcJALR_T_4 == 16'h9002; // @[Frontend.scala:250:26]
wire _taken_rvcJALR_T_7 = _taken_rvcJALR_T_6 == 5'h0; // @[Frontend.scala:250:{56,62}]
wire taken_rvcJALR_1 = _taken_rvcJALR_T_5 & _taken_rvcJALR_T_7; // @[Frontend.scala:250:{26,49,62}]
wire taken_rvcCall_1 = taken_rvcJALR_1; // @[Frontend.scala:250:49, :251:28]
wire _taken_rviImm_T_5 = taken_rviBits_1[3]; // @[Frontend.scala:238:24, :252:31]
wire _taken_rviImm_sign_T_7 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_10 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44]
wire _taken_rviImm_sign_T_8 = _taken_rviImm_sign_T_7; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_2 = _taken_rviImm_sign_T_8; // @[RocketCore.scala:1341:{19,49}]
wire _taken_rviImm_b11_T_31 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1346:18]
wire taken_rviImm_hi_hi_hi_2 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_7 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_10 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41]
wire [10:0] _taken_rviImm_b30_20_T_8 = _taken_rviImm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_2 = {11{taken_rviImm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_2 = taken_rviImm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_13 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_18 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65]
wire [7:0] _taken_rviImm_b19_12_T_14 = _taken_rviImm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_2 = _taken_rviImm_b19_12_T_14; // @[RocketCore.scala:1343:{21,73}]
wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviImm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_26 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_19 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_37 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39]
wire _taken_rviImm_b0_T_27 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37]
wire _taken_rviImm_b11_T_27 = _taken_rviImm_b11_T_26; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_32 = _taken_rviImm_b11_T_27; // @[RocketCore.scala:1345:{18,44}]
wire _taken_rviImm_b11_T_30 = _taken_rviImm_b11_T_29; // @[RocketCore.scala:1346:{39,43}]
wire taken_rviImm_b11_2 = _taken_rviImm_b11_T_32; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_2 = taken_rviImm_b11_2; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] _taken_rviImm_b10_5_T_11 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] _taken_rviImm_b10_5_T_15 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62]
wire [5:0] taken_rviImm_b10_5_2 = _taken_rviImm_b10_5_T_11; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_24 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_34 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57]
wire [3:0] _taken_rviImm_b4_1_T_26 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_36 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39]
wire [3:0] _taken_rviImm_b4_1_T_27 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_37 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52]
wire [3:0] _taken_rviImm_b4_1_T_28 = _taken_rviImm_b4_1_T_27; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] _taken_rviImm_b4_1_T_29 = _taken_rviImm_b4_1_T_28; // @[RocketCore.scala:1349:19, :1350:19]
wire [3:0] taken_rviImm_b4_1_2 = _taken_rviImm_b4_1_T_29; // @[RocketCore.scala:1348:19, :1349:19]
wire _taken_rviImm_b0_T_21 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire _taken_rviImm_b0_T_29 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37]
wire [9:0] taken_rviImm_lo_hi_2 = {taken_rviImm_b10_5_2, taken_rviImm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_2 = {taken_rviImm_lo_hi_2, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_2 = {taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_2 = {taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_2 = {taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_6 = {taken_rviImm_hi_2, taken_rviImm_lo_2}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_7 = _taken_rviImm_T_6; // @[RocketCore.scala:1355:{8,53}]
wire _taken_rviImm_sign_T_11 = _taken_rviImm_sign_T_10; // @[RocketCore.scala:1341:{44,49}]
wire taken_rviImm_sign_3 = _taken_rviImm_sign_T_11; // @[RocketCore.scala:1341:{19,49}]
wire taken_rviImm_hi_hi_hi_3 = taken_rviImm_sign_3; // @[RocketCore.scala:1341:19, :1355:8]
wire [10:0] _taken_rviImm_b30_20_T_11 = _taken_rviImm_b30_20_T_10; // @[RocketCore.scala:1342:{41,49}]
wire [10:0] taken_rviImm_b30_20_3 = {11{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1342:21]
wire [10:0] taken_rviImm_hi_hi_lo_3 = taken_rviImm_b30_20_3; // @[RocketCore.scala:1342:21, :1355:8]
wire [7:0] _taken_rviImm_b19_12_T_19 = _taken_rviImm_b19_12_T_18; // @[RocketCore.scala:1343:{65,73}]
wire [7:0] taken_rviImm_b19_12_3 = {8{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1343:21]
wire [7:0] taken_rviImm_hi_lo_hi_3 = taken_rviImm_b19_12_3; // @[RocketCore.scala:1343:21, :1355:8]
wire _taken_rviImm_b11_T_38 = _taken_rviImm_b11_T_37; // @[RocketCore.scala:1345:{39,44}]
wire _taken_rviImm_b11_T_41 = _taken_rviImm_b11_T_40; // @[RocketCore.scala:1346:{39,43}]
wire _taken_rviImm_b11_T_42 = _taken_rviImm_b11_T_41; // @[RocketCore.scala:1346:{18,43}]
wire _taken_rviImm_b11_T_43 = _taken_rviImm_b11_T_42; // @[RocketCore.scala:1345:18, :1346:18]
wire taken_rviImm_b11_3 = _taken_rviImm_b11_T_43; // @[RocketCore.scala:1344:18, :1345:18]
wire taken_rviImm_hi_lo_lo_3 = taken_rviImm_b11_3; // @[RocketCore.scala:1344:18, :1355:8]
wire [5:0] taken_rviImm_b10_5_3 = _taken_rviImm_b10_5_T_15; // @[RocketCore.scala:1347:{20,62}]
wire [3:0] _taken_rviImm_b4_1_T_39 = _taken_rviImm_b4_1_T_34; // @[RocketCore.scala:1349:{19,57}]
wire [3:0] _taken_rviImm_b4_1_T_38 = _taken_rviImm_b4_1_T_37; // @[RocketCore.scala:1350:{19,52}]
wire [3:0] taken_rviImm_b4_1_3 = _taken_rviImm_b4_1_T_39; // @[RocketCore.scala:1348:19, :1349:19]
wire [9:0] taken_rviImm_lo_hi_3 = {taken_rviImm_b10_5_3, taken_rviImm_b4_1_3}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8]
wire [10:0] taken_rviImm_lo_3 = {taken_rviImm_lo_hi_3, 1'h0}; // @[RocketCore.scala:1355:8]
wire [8:0] taken_rviImm_hi_lo_3 = {taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3}; // @[RocketCore.scala:1355:8]
wire [11:0] taken_rviImm_hi_hi_3 = {taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [20:0] taken_rviImm_hi_3 = {taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_8 = {taken_rviImm_hi_3, taken_rviImm_lo_3}; // @[RocketCore.scala:1355:8]
wire [31:0] _taken_rviImm_T_9 = _taken_rviImm_T_8; // @[RocketCore.scala:1355:{8,53}]
wire [31:0] taken_rviImm_1 = _taken_rviImm_T_5 ? _taken_rviImm_T_7 : _taken_rviImm_T_9; // @[RocketCore.scala:1355:53]
wire taken_predict_taken_1 = _taken_predict_taken_T_1; // @[Frontend.scala:253:54]
wire _taken_taken_T_10 = taken_rviBranch_1 & taken_predict_taken_1; // @[Frontend.scala:239:36, :253:54, :255:53]
wire _taken_taken_T_11 = _taken_taken_T_9 | _taken_taken_T_10; // @[Frontend.scala:255:{29,40,53}]
wire _taken_taken_T_12 = taken_prevRVI_1 & _taken_taken_T_11; // @[Frontend.scala:234:31, :255:{17,40}]
wire _taken_taken_T_13 = taken_rvcJump_1 | taken_rvcJALR_1; // @[Frontend.scala:246:47, :250:49, :256:27]
wire _taken_taken_T_14 = _taken_taken_T_13 | taken_rvcJR_1; // @[Frontend.scala:248:46, :256:{27,38}]
wire _taken_taken_T_15 = taken_rvcBranch_1 & taken_predict_taken_1; // @[Frontend.scala:244:52, :253:54, :256:60]
wire _taken_taken_T_16 = _taken_taken_T_14 | _taken_taken_T_15; // @[Frontend.scala:256:{38,47,60}]
wire _taken_taken_T_17 = taken_valid_1 & _taken_taken_T_16; // @[Frontend.scala:235:44, :256:{15,47}]
wire taken_taken_1 = _taken_taken_T_12 | _taken_taken_T_17; // @[Frontend.scala:255:{17,71}, :256:15]
wire _taken_predictReturn_T_3 = taken_prevRVI_1 & taken_rviReturn_1; // @[Frontend.scala:234:31, :242:46, :257:61]
wire _taken_predictReturn_T_4 = taken_valid_1 & taken_rvcReturn_1; // @[Frontend.scala:235:44, :249:29, :257:83]
wire _taken_predictReturn_T_5 = _taken_predictReturn_T_3 | _taken_predictReturn_T_4; // @[Frontend.scala:257:{61,74,83}]
wire taken_predictReturn_1 = _btb_io_ras_head_valid & _taken_predictReturn_T_5; // @[Frontend.scala:198:21, :257:{49,74}]
wire _taken_predictJump_T_2 = taken_prevRVI_1 & taken_rviJump_1; // @[Frontend.scala:234:31, :240:34, :258:33]
wire _taken_predictJump_T_3 = taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:235:44, :246:47, :258:53]
wire taken_predictJump_1 = _taken_predictJump_T_2 | _taken_predictJump_T_3; // @[Frontend.scala:258:{33,44,53}]
wire _GEN_9 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53]
wire _taken_predictBranch_T_3; // @[Frontend.scala:259:53]
assign _taken_predictBranch_T_3 = _GEN_9; // @[Frontend.scala:259:53]
wire _taken_T_48; // @[Frontend.scala:294:23]
assign _taken_T_48 = _GEN_9; // @[Frontend.scala:259:53, :294:23]
wire _GEN_10 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75]
wire _taken_predictBranch_T_4; // @[Frontend.scala:259:75]
assign _taken_predictBranch_T_4 = _GEN_10; // @[Frontend.scala:259:75]
wire _taken_T_49; // @[Frontend.scala:294:45]
assign _taken_T_49 = _GEN_10; // @[Frontend.scala:259:75, :294:45]
wire _taken_predictBranch_T_5 = _taken_predictBranch_T_3 | _taken_predictBranch_T_4; // @[Frontend.scala:259:{53,66,75}]
wire taken_predictBranch_1 = taken_predict_taken_1 & _taken_predictBranch_T_5; // @[Frontend.scala:253:54, :259:{41,66}]
wire _taken_T_31 = _taken_T_29 & _taken_T_30; // @[Frontend.scala:261:{22,43,69}]
wire _taken_T_32 = _taken_T_31 & taken_valid_1; // @[Frontend.scala:235:44, :261:{43,79}]
wire _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91]
wire _taken_T_34 = _taken_T_32 & _taken_T_33; // @[Frontend.scala:261:{79,88,91}]
assign _taken_T_35 = ~_taken_T_28; // @[Frontend.scala:270:13, :313:51]
assign taken_idx = _taken_T_35; // @[Frontend.scala:223:25, :270:13]
assign after_idx = _taken_T_35 ? 2'h2 : 2'h1; // @[Frontend.scala:224:25, :270:{13,25}, :272:19]
wire _taken_btb_io_ras_update_valid_T_10 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52]
wire _taken_btb_io_ras_update_valid_T_11 = _taken_btb_io_ras_update_valid_T_9 & _taken_btb_io_ras_update_valid_T_10; // @[Decoupled.scala:51:35]
wire _taken_btb_io_ras_update_valid_T_12 = taken_rviCall_1 | taken_rviReturn_1; // @[Frontend.scala:242:46, :243:42, :273:90]
wire _taken_btb_io_ras_update_valid_T_13 = taken_prevRVI_1 & _taken_btb_io_ras_update_valid_T_12; // @[Frontend.scala:234:31, :273:{78,90}]
wire _taken_btb_io_ras_update_valid_T_14 = taken_rvcCall_1 | taken_rvcReturn_1; // @[Frontend.scala:249:29, :251:28, :273:125]
wire _taken_btb_io_ras_update_valid_T_15 = taken_valid_1 & _taken_btb_io_ras_update_valid_T_14; // @[Frontend.scala:235:44, :273:{113,125}]
wire _taken_btb_io_ras_update_valid_T_16 = _taken_btb_io_ras_update_valid_T_13 | _taken_btb_io_ras_update_valid_T_15; // @[Frontend.scala:273:{78,104,113}]
wire _taken_btb_io_ras_update_valid_T_17 = _taken_btb_io_ras_update_valid_T_11 & _taken_btb_io_ras_update_valid_T_16; // @[Frontend.scala:273:{51,66,104}]
wire _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50]
wire _taken_btb_io_ras_update_bits_cfiType_T_12 = _taken_btb_io_ras_update_bits_cfiType_T_10; // @[Frontend.scala:276:{50,82}]
wire _taken_btb_io_ras_update_bits_cfiType_T_13 = ~_taken_btb_io_ras_update_bits_cfiType_T_12; // @[Frontend.scala:276:{46,82}]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala:275:{46,50}, :276:46]
wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala:274:{46,50}, :275:46]
assign btb_io_ras_update_bits_cfiType = _taken_T_35 ? _taken_btb_io_ras_update_bits_cfiType_T_15 : _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala:270:{13,25}, :274:{40,46}]
wire _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15]
wire _taken_T_38 = _taken_T_37 & taken_taken_1; // @[Decoupled.scala:51:35]
wire _taken_T_39 = ~taken_predictBranch_1; // @[Frontend.scala:259:41, :280:44]
wire _taken_T_40 = _taken_T_38 & _taken_T_39; // @[Frontend.scala:280:{32,41,44}]
wire _taken_T_41 = ~taken_predictJump_1; // @[Frontend.scala:258:44, :280:62]
wire _taken_T_42 = _taken_T_40 & _taken_T_41; // @[Frontend.scala:280:{41,59,62}]
wire _taken_T_43 = ~taken_predictReturn_1; // @[Frontend.scala:257:49, :280:78]
wire _taken_T_44 = _taken_T_42 & _taken_T_43; // @[Frontend.scala:280:{59,75,78}]
wire _taken_T_45 = s2_valid & taken_predictReturn_1; // @[Frontend.scala:108:25, :257:49, :283:26]
assign useRAS = _taken_T_35 & _taken_T_36 & _taken_T_45 | _taken_T_7 & _taken_T_16; // @[Frontend.scala:225:29, :270:{13,25}, :279:{15,30}, :283:{26,44}, :284:20]
wire _taken_T_46 = taken_predictBranch_1 | taken_predictJump_1; // @[Frontend.scala:258:44, :259:41, :286:44]
wire _taken_T_47 = s2_valid & _taken_T_46; // @[Frontend.scala:108:25, :286:{26,44}]
wire [39:0] taken_pc_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | 2'h2}; // @[Frontend.scala:222:22, :287:33, :323:50]
wire [40:0] _taken_npc_T_5 = {1'h0, taken_pc_1} - 41'h2; // @[Frontend.scala:287:33, :290:36]
wire [39:0] _taken_npc_T_6 = _taken_npc_T_5[39:0]; // @[Frontend.scala:290:36]
wire [39:0] _taken_npc_T_7 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala:234:31, :287:33, :290:{23,36}]
wire [39:0] _taken_npc_T_8 = _taken_npc_T_7; // @[Frontend.scala:290:{23,59}]
wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? taken_rviImm_1 : {{11{taken_rvcImm_1[20]}}, taken_rvcImm_1}; // @[Frontend.scala:234:31, :247:23, :252:23, :290:71]
wire [40:0] _taken_npc_T_10 = {_taken_npc_T_8[39], _taken_npc_T_8} + {{9{_taken_npc_T_9[31]}}, _taken_npc_T_9}; // @[Frontend.scala:290:{59,66,71}]
wire [39:0] _taken_npc_T_11 = _taken_npc_T_10[39:0]; // @[Frontend.scala:290:66]
wire [39:0] taken_npc_1 = _taken_npc_T_11; // @[Frontend.scala:290:66]
wire [39:0] _taken_predicted_npc_T_1 = taken_npc_1; // @[Frontend.scala:290:66, :291:34]
wire _taken_T_50 = _taken_T_48 | _taken_T_49; // @[Frontend.scala:294:{23,36,45}]
wire _taken_btb_io_bht_advance_valid_T_4 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52]
wire _taken_btb_io_bht_advance_valid_T_5 = _taken_btb_io_bht_advance_valid_T_3 & _taken_btb_io_bht_advance_valid_T_4; // @[Decoupled.scala:51:35]
wire _taken_T_51 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15]
wire _taken_T_53 = taken_predictBranch_1 & _taken_T_52; // @[Frontend.scala:259:41, :298:52]
wire _taken_T_54 = _taken_T_53 | taken_predictJump_1; // @[Frontend.scala:258:44, :298:{52,91}]
wire _taken_T_55 = _taken_T_54 | taken_predictReturn_1; // @[Frontend.scala:257:49, :298:{91,106}]
wire _taken_T_56 = _taken_T_51 & _taken_T_55; // @[Frontend.scala:298:{15,34,106}]
assign updateBTB = _taken_T_35 & _taken_T_56 | _taken_T_27; // @[Frontend.scala:226:32, :270:{13,25}, :298:{34,125}, :299:21]
wire _taken_T_58 = ~_taken_T_28; // @[Frontend.scala:270:13, :306:26, :313:51]
wire _taken_T_59 = taken_valid_1 & _taken_T_58; // @[Frontend.scala:235:44, :306:{23,26}]
wire _taken_T_60 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91, :306:40]
wire _taken_T_61 = _taken_T_59 & _taken_T_60; // @[Frontend.scala:306:{23,37,40}]
wire [15:0] _taken_s2_partial_insn_T = {taken_bits_1[15:2], 2'h3}; // @[Frontend.scala:236:37, :308:37]
wire taken = _taken_T_28 | taken_taken_1; // @[Frontend.scala:255:71, :311:19, :313:51]
assign predicted_npc = useRAS ? {1'h0, _btb_io_ras_head_bits} : _taken_T_35 & _taken_T_36 & _taken_T_47 ? _taken_predicted_npc_T_1 : _taken_T_7 & _taken_T_18 ? _taken_predicted_npc_T : predicted_taken ? _predicted_npc_T_1 : ntpc; // @[package.scala:132:15]
wire _GEN_11 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34]
assign s2_redirect = ~s2_btb_taken & taken & _T_37 | io_cpu_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_68( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
| module cc_banks_6_5( // @[DescribedSRAM.scala:17:26]
input [14:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [63:0] RW0_wdata,
output [63:0] RW0_rdata
);
cc_banks_0_ext cc_banks_0_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
); // @[DescribedSRAM.scala:17:26]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
| module AsyncValidSync_102( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_113 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
| module dataMems_33( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File primitives.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object lowMask
{
def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt =
{
require(topBound != bottomBound)
val numInVals = BigInt(1)<<in.getWidth
if (topBound < bottomBound) {
lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound)
} else if (numInVals > 64 /* Empirical */) {
// For simulation performance, we should avoid generating
// exteremely wide shifters, so we divide and conquer.
// Empirically, this does not impact synthesis QoR.
val mid = numInVals / 2
val msb = in(in.getWidth - 1)
val lsbs = in(in.getWidth - 2, 0)
if (mid < topBound) {
if (mid <= bottomBound) {
Mux(msb,
lowMask(lsbs, topBound - mid, bottomBound - mid),
0.U
)
} else {
Mux(msb,
lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U,
lowMask(lsbs, mid, bottomBound)
)
}
} else {
~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound))
}
} else {
val shift = (BigInt(-1)<<numInVals.toInt).S>>in
Reverse(
shift(
(numInVals - 1 - bottomBound).toInt,
(numInVals - topBound).toInt
)
)
}
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object countLeadingZeros
{
def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy2
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 1)>>1
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 2 + 1, ix * 2).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 2).orR
reducedVec.asUInt
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
object orReduceBy4
{
def apply(in: UInt): UInt =
{
val reducedWidth = (in.getWidth + 3)>>2
val reducedVec = Wire(Vec(reducedWidth, Bool()))
for (ix <- 0 until reducedWidth - 1) {
reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR
}
reducedVec(reducedWidth - 1) :=
in(in.getWidth - 1, (reducedWidth - 1) * 4).orR
reducedVec.asUInt
}
}
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
| module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_2( // @[RoundAnyRawFNToRecFN.scala:48:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16]
input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16]
input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49]
wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22]
wire _common_underflow_T_7 = io_detectTininess_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :222:49]
wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33]
wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53]
wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53]
wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53]
wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53]
wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53]
wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53]
wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27]
wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66]
wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}]
wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}]
wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57]
wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37]
wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31]
wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16]
wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31]
wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50]
wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31]
wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40]
wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49]
wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37]
wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21]
wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25]
wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26]
wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26]
wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26]
wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26]
wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26]
wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56]
wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22]
wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22]
wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20]
wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20]
wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20]
wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20]
wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20]
wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22]
wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20]
wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20]
wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20]
wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20]
wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20]
wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20]
wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20]
wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20]
wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20]
wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20]
wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}]
wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}]
wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17]
wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56]
wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22]
wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22]
wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20]
wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20]
wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20]
wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22]
wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20]
wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20]
wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58]
wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24]
wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24]
wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}]
wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41]
wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}]
wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28]
wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}]
wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40]
wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}]
wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42]
wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}]
wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36]
wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38]
wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38]
assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38]
wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38]
assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38]
wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32]
assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32]
wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}]
wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29]
wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29]
wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32]
wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}]
wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}]
wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49]
wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30]
wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30]
wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35]
wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35]
wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}]
wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21]
wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32]
wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}]
wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}]
wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42]
wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67]
wire [25:0] _roundedSig_T_15 = _roundedSig_T_13 ? _roundedSig_T_14 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:{24,42,67}]
wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24]
wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47]
wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54]
wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}]
wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}]
assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37]
assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37]
wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27]
wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27]
assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27]
assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16]
wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30]
assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}]
assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50]
assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31]
assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31]
wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45]
wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44]
wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61]
wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}]
wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}]
wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63]
wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}]
wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}]
wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}]
wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29]
wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29]
wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27]
wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27]
wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27]
wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49]
wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}]
wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}]
wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57]
wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49]
wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71]
wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}]
wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30]
wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49]
wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49]
wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}]
wire _common_underflow_T_12 = _common_underflow_T_7 & _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:{49,77}, :223:34]
wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38]
wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45]
wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}]
wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60]
wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27]
assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76]
assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40]
assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49]
assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49]
wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34]
wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22]
wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36]
wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}]
wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64]
wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}]
wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32]
wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32]
wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43]
wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}]
wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}]
wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20]
wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60]
wire pegMinNonzeroMagOut = _pegMinNonzeroMagOut_T & _pegMinNonzeroMagOut_T_1; // @[RoundAnyRawFNToRecFN.scala:245:{20,45,60}]
wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42]
wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}]
wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45]
wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}]
wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22]
wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32]
wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}]
wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}]
wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14]
wire [8:0] _expOut_T_5 = pegMinNonzeroMagOut ? 9'h194 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :257:18]
wire [8:0] _expOut_T_6 = ~_expOut_T_5; // @[RoundAnyRawFNToRecFN.scala:257:{14,18}]
wire [8:0] _expOut_T_7 = _expOut_T_3 & _expOut_T_6; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17, :257:14]
wire [8:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 7'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18]
wire [8:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}]
wire [8:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14]
wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18]
wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}]
wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14]
wire [8:0] _expOut_T_14 = pegMinNonzeroMagOut ? 9'h6B : 9'h0; // @[RoundAnyRawFNToRecFN.scala:245:45, :269:16]
wire [8:0] _expOut_T_15 = _expOut_T_13 | _expOut_T_14; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18, :269:16]
wire [8:0] _expOut_T_16 = pegMaxFiniteMagOut ? 9'h17F : 9'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16]
wire [8:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16]
wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16]
wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16]
wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16]
wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16]
wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22]
wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}]
wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16]
wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16]
wire [22:0] _fractOut_T_4 = {23{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13]
wire [22:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13]
wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23]
assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}]
assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33]
wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23]
wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}]
wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}]
assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
| module EgressUnit_30( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27] |
Generate the Verilog code corresponding to the following Chisel files.
File MulAddRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle
{
//*** ENCODE SOME OF THESE CASES IN FEWER BITS?:
val isSigNaNAny = Bool()
val isNaNAOrB = Bool()
val isInfA = Bool()
val isZeroA = Bool()
val isInfB = Bool()
val isZeroB = Bool()
val signProd = Bool()
val isNaNC = Bool()
val isInfC = Bool()
val isZeroC = Bool()
val sExpSum = SInt((expWidth + 2).W)
val doSubMags = Bool()
val CIsDominant = Bool()
val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W)
val highAlignedSigC = UInt((sigWidth + 2).W)
val bit0AlignedSigC = UInt(1.W)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val mulAddA = Output(UInt(sigWidth.W))
val mulAddB = Output(UInt(sigWidth.W))
val mulAddC = Output(UInt((sigWidth * 2).W))
val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
//*** POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN
//*** UNSHIFTED C AND PRODUCT):
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a)
val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b)
val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c)
val signProd = rawA.sign ^ rawB.sign ^ io.op(1)
//*** REVIEW THE BIAS FOR 'sExpAlignedProd':
val sExpAlignedProd =
rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S
val doSubMags = signProd ^ rawC.sign ^ io.op(0)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sNatCAlignDist = sExpAlignedProd - rawC.sExp
val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0)
val isMinCAlign = rawA.isZero || rawB.isZero || (sNatCAlignDist < 0.S)
val CIsDominant =
! rawC.isZero && (isMinCAlign || (posNatCAlignDist <= sigWidth.U))
val CAlignDist =
Mux(isMinCAlign,
0.U,
Mux(posNatCAlignDist < (sigSumWidth - 1).U,
posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0),
(sigSumWidth - 1).U
)
)
val mainAlignedSigC =
(Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist
val reduced4CExtra =
(orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) &
lowMask(
CAlignDist>>2,
//*** NOT NEEDED?:
// (sigSumWidth + 2)>>2,
(sigSumWidth - 1)>>2,
(sigSumWidth - sigWidth - 1)>>2
)
).orR
val alignedSigC =
Cat(mainAlignedSigC>>3,
Mux(doSubMags,
mainAlignedSigC(2, 0).andR && ! reduced4CExtra,
mainAlignedSigC(2, 0).orR || reduced4CExtra
)
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
io.mulAddA := rawA.sig
io.mulAddB := rawB.sig
io.mulAddC := alignedSigC(sigWidth * 2, 1)
io.toPostMul.isSigNaNAny :=
isSigNaNRawFloat(rawA) || isSigNaNRawFloat(rawB) ||
isSigNaNRawFloat(rawC)
io.toPostMul.isNaNAOrB := rawA.isNaN || rawB.isNaN
io.toPostMul.isInfA := rawA.isInf
io.toPostMul.isZeroA := rawA.isZero
io.toPostMul.isInfB := rawB.isInf
io.toPostMul.isZeroB := rawB.isZero
io.toPostMul.signProd := signProd
io.toPostMul.isNaNC := rawC.isNaN
io.toPostMul.isInfC := rawC.isInf
io.toPostMul.isZeroC := rawC.isZero
io.toPostMul.sExpSum :=
Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S)
io.toPostMul.doSubMags := doSubMags
io.toPostMul.CIsDominant := CIsDominant
io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0)
io.toPostMul.highAlignedSigC :=
alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1)
io.toPostMul.bit0AlignedSigC := alignedSigC(0)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth))
val mulAddResult = Input(UInt((sigWidth * 2 + 1).W))
val roundingMode = Input(UInt(3.W))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigSumWidth = sigWidth * 3 + 3
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_min = (io.roundingMode === round_min)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags
val sigSum =
Cat(Mux(io.mulAddResult(sigWidth * 2),
io.fromPreMul.highAlignedSigC + 1.U,
io.fromPreMul.highAlignedSigC
),
io.mulAddResult(sigWidth * 2 - 1, 0),
io.fromPreMul.bit0AlignedSigC
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val CDom_sign = opSignC
val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext
val CDom_absSigSum =
Mux(io.fromPreMul.doSubMags,
~sigSum(sigSumWidth - 1, sigWidth + 1),
0.U(1.W) ##
//*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO:
io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ##
sigSum(sigSumWidth - 3, sigWidth + 2)
)
val CDom_absSigSumExtra =
Mux(io.fromPreMul.doSubMags,
(~sigSum(sigWidth, 1)).orR,
sigSum(sigWidth + 1, 1).orR
)
val CDom_mainSig =
(CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)(
sigWidth * 2 + 1, sigWidth - 3)
val CDom_reduced4SigExtra =
(orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) &
lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR
val CDom_sig =
Cat(CDom_mainSig>>3,
CDom_mainSig(2, 0).orR || CDom_reduced4SigExtra ||
CDom_absSigSumExtra
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notCDom_signSigSum = sigSum(sigWidth * 2 + 3)
val notCDom_absSigSum =
Mux(notCDom_signSigSum,
~sigSum(sigWidth * 2 + 2, 0),
sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags
)
val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum)
val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum)
val notCDom_nearNormDist = notCDom_normDistReduced2<<1
val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext
val notCDom_mainSig =
(notCDom_absSigSum<<notCDom_nearNormDist)(
sigWidth * 2 + 3, sigWidth - 1)
val notCDom_reduced4SigExtra =
(orReduceBy2(
notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) &
lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2)
).orR
val notCDom_sig =
Cat(notCDom_mainSig>>3,
notCDom_mainSig(2, 0).orR || notCDom_reduced4SigExtra
)
val notCDom_completeCancellation =
(notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U)
val notCDom_sign =
Mux(notCDom_completeCancellation,
roundingMode_min,
io.fromPreMul.signProd ^ notCDom_signSigSum
)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val notNaN_isInfProd = io.fromPreMul.isInfA || io.fromPreMul.isInfB
val notNaN_isInfOut = notNaN_isInfProd || io.fromPreMul.isInfC
val notNaN_addZeros =
(io.fromPreMul.isZeroA || io.fromPreMul.isZeroB) &&
io.fromPreMul.isZeroC
io.invalidExc :=
io.fromPreMul.isSigNaNAny ||
(io.fromPreMul.isInfA && io.fromPreMul.isZeroB) ||
(io.fromPreMul.isZeroA && io.fromPreMul.isInfB) ||
(! io.fromPreMul.isNaNAOrB &&
(io.fromPreMul.isInfA || io.fromPreMul.isInfB) &&
io.fromPreMul.isInfC &&
io.fromPreMul.doSubMags)
io.rawOut.isNaN := io.fromPreMul.isNaNAOrB || io.fromPreMul.isNaNC
io.rawOut.isInf := notNaN_isInfOut
//*** IMPROVE?:
io.rawOut.isZero :=
notNaN_addZeros ||
(! io.fromPreMul.CIsDominant && notCDom_completeCancellation)
io.rawOut.sign :=
(notNaN_isInfProd && io.fromPreMul.signProd) ||
(io.fromPreMul.isInfC && opSignC) ||
(notNaN_addZeros && ! roundingMode_min &&
io.fromPreMul.signProd && opSignC) ||
(notNaN_addZeros && roundingMode_min &&
(io.fromPreMul.signProd || opSignC)) ||
(! notNaN_isInfOut && ! notNaN_addZeros &&
Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign))
io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule
{
override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul =
Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul =
Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
mulAddRecFNToRaw_postMul.io.fromPreMul :=
mulAddRecFNToRaw_preMul.io.toPostMul
mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult
mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
| module MulAddRecFNToRaw_preMul_e11_s53( // @[MulAddRecFN.scala:71:7]
input [1:0] io_op, // @[MulAddRecFN.scala:74:16]
input [64:0] io_a, // @[MulAddRecFN.scala:74:16]
input [64:0] io_b, // @[MulAddRecFN.scala:74:16]
input [64:0] io_c, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16]
output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16]
output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16]
output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16]
output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16]
output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16]
output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16]
);
wire rawA_isNaN = (&(io_a[63:62])) & io_a[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawB_isNaN = (&(io_b[63:62])) & io_b[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire rawC_isNaN = (&(io_c[63:62])) & io_c[61]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
wire signProd = io_a[64] ^ io_b[64] ^ io_op[1]; // @[rawFloatFromRecFN.scala:59:25]
wire [13:0] _sExpAlignedProd_T_1 = {2'h0, io_a[63:52]} + {2'h0, io_b[63:52]} - 14'h7C8; // @[rawFloatFromRecFN.scala:51:21]
wire doSubMags = signProd ^ io_c[64] ^ io_op[0]; // @[rawFloatFromRecFN.scala:59:25]
wire [13:0] _sNatCAlignDist_T = _sExpAlignedProd_T_1 - {2'h0, io_c[63:52]}; // @[rawFloatFromRecFN.scala:51:21]
wire isMinCAlign = ~(|(io_a[63:61])) | ~(|(io_b[63:61])) | $signed(_sNatCAlignDist_T) < 14'sh0; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire CIsDominant = (|(io_c[63:61])) & (isMinCAlign | _sNatCAlignDist_T[12:0] < 13'h36); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _sNatCAlignDist_T[12:0] < 13'hA1 ? _sNatCAlignDist_T[7:0] : 8'hA1; // @[MulAddRecFN.scala:106:42, :107:42, :108:{35,50}, :112:12, :114:{16,34}, :115:33]
wire [164:0] mainAlignedSigC = $signed($signed({doSubMags ? {1'h1, ~(|(io_c[63:61])), ~(io_c[51:0])} : {1'h0, |(io_c[63:61]), io_c[51:0]}, {111{doSubMags}}}) >>> CAlignDist); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}]
wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> CAlignDist[7:2]); // @[primitives.scala:76:56]
wire [12:0] _GEN = {|(io_c[51:48]), |(io_c[47:44]), |(io_c[43:40]), |(io_c[39:36]), |(io_c[35:32]), |(io_c[31:28]), |(io_c[27:24]), |(io_c[23:20]), |(io_c[19:16]), |(io_c[15:12]), |(io_c[11:8]), |(io_c[7:4]), |(io_c[3:0])} & {reduced4CExtra_shift[24], reduced4CExtra_shift[25], reduced4CExtra_shift[26], reduced4CExtra_shift[27], reduced4CExtra_shift[28], reduced4CExtra_shift[29], reduced4CExtra_shift[30], reduced4CExtra_shift[31], reduced4CExtra_shift[32], reduced4CExtra_shift[33], reduced4CExtra_shift[34], reduced4CExtra_shift[35], reduced4CExtra_shift[36]}; // @[primitives.scala:76:56, :77:20, :78:22, :120:{33,54}]
assign io_mulAddA = {|(io_a[63:61]), io_a[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddB = {|(io_b[63:61]), io_b[51:0]}; // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:49]
assign io_mulAddC = mainAlignedSigC[108:3]; // @[MulAddRecFN.scala:71:7, :120:100, :143:30]
assign io_toPostMul_isSigNaNAny = rawA_isNaN & ~(io_a[51]) | rawB_isNaN & ~(io_b[51]) | rawC_isNaN & ~(io_c[51]); // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isNaNAOrB = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfA = (&(io_a[63:62])) & ~(io_a[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroA = ~(|(io_a[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_isInfB = (&(io_b[63:62])) & ~(io_b[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroB = ~(|(io_b[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_signProd = signProd; // @[MulAddRecFN.scala:71:7, :97:{30,42}]
assign io_toPostMul_isNaNC = rawC_isNaN; // @[rawFloatFromRecFN.scala:56:33]
assign io_toPostMul_isInfC = (&(io_c[63:62])) & ~(io_c[61]); // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
assign io_toPostMul_isZeroC = ~(|(io_c[63:61])); // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
assign io_toPostMul_sExpSum = CIsDominant ? {1'h0, io_c[63:52]} : _sExpAlignedProd_T_1[12:0] - 13'h35; // @[rawFloatFromRecFN.scala:51:21]
assign io_toPostMul_doSubMags = doSubMags; // @[MulAddRecFN.scala:71:7, :102:{30,42}]
assign io_toPostMul_CIsDominant = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23]
assign io_toPostMul_CDom_CAlignDist = CAlignDist[5:0]; // @[MulAddRecFN.scala:71:7, :112:12, :161:47]
assign io_toPostMul_highAlignedSigC = mainAlignedSigC[163:109]; // @[MulAddRecFN.scala:71:7, :120:100, :163:20]
assign io_toPostMul_bit0AlignedSigC = doSubMags ? (&(mainAlignedSigC[2:0])) & _GEN == 13'h0 : (|{mainAlignedSigC[2:0], _GEN}); // @[MulAddRecFN.scala:71:7, :102:{30,42}, :120:100, :122:68, :130:11, :133:16, :134:{32,39,44}, :135:{39,44}]
endmodule |
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
| module TLMonitor_34( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [5:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_first_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_set_wo_ready_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_wo_ready_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_interm_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_interm_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_opcodes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_opcodes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_sizes_set_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_sizes_set_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _c_probe_ack_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _c_probe_ack_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_1_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_2_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_3_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [5:0] _same_cycle_resp_WIRE_4_bits_source = 6'h0; // @[Bundles.scala:265:74]
wire [5:0] _same_cycle_resp_WIRE_5_bits_source = 6'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [514:0] _c_opcodes_set_T_1 = 515'h0; // @[Monitor.scala:767:54]
wire [514:0] _c_sizes_set_T_1 = 515'h0; // @[Monitor.scala:768:52]
wire [8:0] _c_opcodes_set_T = 9'h0; // @[Monitor.scala:767:79]
wire [8:0] _c_sizes_set_T = 9'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [63:0] _c_set_wo_ready_T = 64'h1; // @[OneHot.scala:58:35]
wire [63:0] _c_set_T = 64'h1; // @[OneHot.scala:58:35]
wire [131:0] c_opcodes_set = 132'h0; // @[Monitor.scala:740:34]
wire [131:0] c_sizes_set = 132'h0; // @[Monitor.scala:741:34]
wire [32:0] c_set = 33'h0; // @[Monitor.scala:738:34]
wire [32:0] c_set_wo_ready = 33'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [5:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_1 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_7 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_13 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_19 = io_in_a_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_28 = _source_ok_T_27 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_29 = _source_ok_T_28 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_29 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_30 = io_in_d_bits_source_0 == 6'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] _source_ok_T_31 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_37 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_43 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire [3:0] _source_ok_T_49 = io_in_d_bits_source_0[5:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 4'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_38 = _source_ok_T_37 == 4'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_42; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_44 = _source_ok_T_43 == 4'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_50 = _source_ok_T_49 == 4'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire _source_ok_T_55 = io_in_d_bits_source_0 == 6'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_55; // @[Parameters.scala:1138:31]
wire _source_ok_T_56 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_59 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire sink_ok = io_in_d_bits_sink_0 != 3'h7; // @[Monitor.scala:36:7, :309:31]
wire _T_1003 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1003; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1003; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1076 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1076; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1076; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1076; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [32:0] inflight; // @[Monitor.scala:614:27]
reg [131:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [131:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [32:0] a_set; // @[Monitor.scala:626:34]
wire [32:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [131:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [131:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [8:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [8:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [8:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [8:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [8:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [8:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [8:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [8:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [8:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [131:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [131:0] _a_opcode_lookup_T_6 = {128'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [131:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [131:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [131:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [131:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[131:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [63:0] _GEN_2 = 64'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [63:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_929 = _T_1003 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_929 ? _a_set_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_929 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_929 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [8:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [8:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [8:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [514:0] _a_opcodes_set_T_1 = {511'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_929 ? _a_opcodes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [514:0] _a_sizes_set_T_1 = {511'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_929 ? _a_sizes_set_T_1[131:0] : 132'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [32:0] d_clr; // @[Monitor.scala:664:34]
wire [32:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [131:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [131:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_975 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [63:0] _GEN_5 = 64'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [63:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_975 & ~d_release_ack ? _d_clr_wo_ready_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_944 = _T_1076 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_944 ? _d_clr_T[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_5 = 527'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_944 ? _d_opcodes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [526:0] _d_sizes_clr_T_5 = 527'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_944 ? _d_sizes_clr_T_5[131:0] : 132'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [32:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [32:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [32:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [131:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [131:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [131:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [131:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [131:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [131:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [32:0] inflight_1; // @[Monitor.scala:726:35]
wire [32:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [131:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [131:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [131:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [131:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [131:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [131:0] _c_opcode_lookup_T_6 = {128'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [131:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[131:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [131:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [131:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [131:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[131:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [32:0] d_clr_1; // @[Monitor.scala:774:34]
wire [32:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [131:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [131:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1047 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1047 & d_release_ack_1 ? _d_clr_wo_ready_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire _T_1029 = _T_1076 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1029 ? _d_clr_T_1[32:0] : 33'h0; // @[OneHot.scala:58:35]
wire [526:0] _d_opcodes_clr_T_11 = 527'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1029 ? _d_opcodes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [526:0] _d_sizes_clr_T_11 = 527'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1029 ? _d_sizes_clr_T_11[131:0] : 132'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 6'h0; // @[Monitor.scala:36:7, :795:113]
wire [32:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [32:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [131:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [131:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [131:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [131:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to the following Chisel files.
File Breakpoint.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat}
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tile.{CoreBundle, HasCoreParameters}
import freechips.rocketchip.util._
class BPControl(implicit p: Parameters) extends CoreBundle()(p) {
val ttype = UInt(4.W)
val dmode = Bool()
val maskmax = UInt(6.W)
val reserved = UInt((xLen - (if (coreParams.useBPWatch) 26 else 24)).W)
val action = UInt((if (coreParams.useBPWatch) 3 else 1).W)
val chain = Bool()
val zero = UInt(2.W)
val tmatch = UInt(2.W)
val m = Bool()
val h = Bool()
val s = Bool()
val u = Bool()
val x = Bool()
val w = Bool()
val r = Bool()
def tType = 2
def maskMax = 4
def enabled(mstatus: MStatus) = !mstatus.debug && Cat(m, h, s, u)(mstatus.prv)
}
class TExtra(implicit p: Parameters) extends CoreBundle()(p) {
def mvalueBits: Int = if (xLen == 32) coreParams.mcontextWidth min 6 else coreParams.mcontextWidth min 13
def svalueBits: Int = if (xLen == 32) coreParams.scontextWidth min 16 else coreParams.scontextWidth min 34
def mselectPos: Int = if (xLen == 32) 25 else 50
def mvaluePos : Int = mselectPos + 1
def sselectPos: Int = 0
def svaluePos : Int = 2
val mvalue = UInt(mvalueBits.W)
val mselect = Bool()
val pad2 = UInt((mselectPos - svalueBits - 2).W)
val svalue = UInt(svalueBits.W)
val pad1 = UInt(1.W)
val sselect = Bool()
}
class BP(implicit p: Parameters) extends CoreBundle()(p) {
val control = new BPControl
val address = UInt(vaddrBits.W)
val textra = new TExtra
def contextMatch(mcontext: UInt, scontext: UInt) =
(if (coreParams.mcontextWidth > 0) (!textra.mselect || (mcontext(textra.mvalueBits-1,0) === textra.mvalue)) else true.B) &&
(if (coreParams.scontextWidth > 0) (!textra.sselect || (scontext(textra.svalueBits-1,0) === textra.svalue)) else true.B)
def mask(dummy: Int = 0) =
(0 until control.maskMax-1).scanLeft(control.tmatch(0))((m, i) => m && address(i)).asUInt
def pow2AddressMatch(x: UInt) =
(~x | mask()) === (~address | mask())
def rangeAddressMatch(x: UInt) =
(x >= address) ^ control.tmatch(0)
def addressMatch(x: UInt) =
Mux(control.tmatch(1), rangeAddressMatch(x), pow2AddressMatch(x))
}
class BPWatch (val n: Int) extends Bundle() {
val valid = Vec(n, Bool())
val rvalid = Vec(n, Bool())
val wvalid = Vec(n, Bool())
val ivalid = Vec(n, Bool())
val action = UInt(3.W)
}
class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with HasCoreParameters {
val io = IO(new Bundle {
val status = Input(new MStatus())
val bp = Input(Vec(n, new BP))
val pc = Input(UInt(vaddrBits.W))
val ea = Input(UInt(vaddrBits.W))
val mcontext = Input(UInt(coreParams.mcontextWidth.W))
val scontext = Input(UInt(coreParams.scontextWidth.W))
val xcpt_if = Output(Bool())
val xcpt_ld = Output(Bool())
val xcpt_st = Output(Bool())
val debug_if = Output(Bool())
val debug_ld = Output(Bool())
val debug_st = Output(Bool())
val bpwatch = Output(Vec(n, new BPWatch(1)))
})
io.xcpt_if := false.B
io.xcpt_ld := false.B
io.xcpt_st := false.B
io.debug_if := false.B
io.debug_ld := false.B
io.debug_st := false.B
(io.bpwatch zip io.bp).foldLeft((true.B, true.B, true.B)) { case ((ri, wi, xi), (bpw, bp)) =>
val en = bp.control.enabled(io.status)
val cx = bp.contextMatch(io.mcontext, io.scontext)
val r = en && bp.control.r && bp.addressMatch(io.ea) && cx
val w = en && bp.control.w && bp.addressMatch(io.ea) && cx
val x = en && bp.control.x && bp.addressMatch(io.pc) && cx
val end = !bp.control.chain
val action = bp.control.action
bpw.action := action
bpw.valid(0) := false.B
bpw.rvalid(0) := false.B
bpw.wvalid(0) := false.B
bpw.ivalid(0) := false.B
when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B }
when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B }
when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B }
(end || r, end || w, end || x)
}
}
| module BreakpointUnit_7( // @[Breakpoint.scala:79:7]
input clock, // @[Breakpoint.scala:79:7]
input reset, // @[Breakpoint.scala:79:7]
input io_status_debug, // @[Breakpoint.scala:80:14]
input io_status_cease, // @[Breakpoint.scala:80:14]
input io_status_wfi, // @[Breakpoint.scala:80:14]
input [1:0] io_status_dprv, // @[Breakpoint.scala:80:14]
input io_status_dv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_prv, // @[Breakpoint.scala:80:14]
input io_status_v, // @[Breakpoint.scala:80:14]
input io_status_sd, // @[Breakpoint.scala:80:14]
input io_status_mpv, // @[Breakpoint.scala:80:14]
input io_status_gva, // @[Breakpoint.scala:80:14]
input io_status_tsr, // @[Breakpoint.scala:80:14]
input io_status_tw, // @[Breakpoint.scala:80:14]
input io_status_tvm, // @[Breakpoint.scala:80:14]
input io_status_mxr, // @[Breakpoint.scala:80:14]
input io_status_sum, // @[Breakpoint.scala:80:14]
input io_status_mprv, // @[Breakpoint.scala:80:14]
input [1:0] io_status_fs, // @[Breakpoint.scala:80:14]
input [1:0] io_status_mpp, // @[Breakpoint.scala:80:14]
input io_status_spp, // @[Breakpoint.scala:80:14]
input io_status_mpie, // @[Breakpoint.scala:80:14]
input io_status_spie, // @[Breakpoint.scala:80:14]
input io_status_mie, // @[Breakpoint.scala:80:14]
input io_status_sie, // @[Breakpoint.scala:80:14]
input [38:0] io_pc // @[Breakpoint.scala:80:14]
);
wire io_status_debug_0 = io_status_debug; // @[Breakpoint.scala:79:7]
wire io_status_cease_0 = io_status_cease; // @[Breakpoint.scala:79:7]
wire io_status_wfi_0 = io_status_wfi; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[Breakpoint.scala:79:7]
wire io_status_dv_0 = io_status_dv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[Breakpoint.scala:79:7]
wire io_status_v_0 = io_status_v; // @[Breakpoint.scala:79:7]
wire io_status_sd_0 = io_status_sd; // @[Breakpoint.scala:79:7]
wire io_status_mpv_0 = io_status_mpv; // @[Breakpoint.scala:79:7]
wire io_status_gva_0 = io_status_gva; // @[Breakpoint.scala:79:7]
wire io_status_tsr_0 = io_status_tsr; // @[Breakpoint.scala:79:7]
wire io_status_tw_0 = io_status_tw; // @[Breakpoint.scala:79:7]
wire io_status_tvm_0 = io_status_tvm; // @[Breakpoint.scala:79:7]
wire io_status_mxr_0 = io_status_mxr; // @[Breakpoint.scala:79:7]
wire io_status_sum_0 = io_status_sum; // @[Breakpoint.scala:79:7]
wire io_status_mprv_0 = io_status_mprv; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[Breakpoint.scala:79:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[Breakpoint.scala:79:7]
wire io_status_spp_0 = io_status_spp; // @[Breakpoint.scala:79:7]
wire io_status_mpie_0 = io_status_mpie; // @[Breakpoint.scala:79:7]
wire io_status_spie_0 = io_status_spie; // @[Breakpoint.scala:79:7]
wire io_status_mie_0 = io_status_mie; // @[Breakpoint.scala:79:7]
wire io_status_sie_0 = io_status_sie; // @[Breakpoint.scala:79:7]
wire [38:0] io_pc_0 = io_pc; // @[Breakpoint.scala:79:7]
wire [38:0] io_ea = 39'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_sxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_uxl = 2'h2; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_xs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [1:0] io_status_vs = 2'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [7:0] io_status_zero1 = 8'h0; // @[Breakpoint.scala:79:7, :80:14]
wire io_status_mbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sbe = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_sd_rv32 = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_ube = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_upie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_hie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_status_uie = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_xcpt_st = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_if = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_ld = 1'h0; // @[Breakpoint.scala:79:7]
wire io_debug_st = 1'h0; // @[Breakpoint.scala:79:7]
wire [22:0] io_status_zero2 = 23'h0; // @[Breakpoint.scala:79:7, :80:14]
wire [31:0] io_status_isa = 32'h14112D; // @[Breakpoint.scala:79:7, :80:14]
endmodule |
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